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93f1e401
EI		 1/*
2 * QEMU model of Xilinx AXI-Ethernet.
3 *
4 * Copyright (c) 2011 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "sysbus.h"
26#include "qemu-char.h"
27#include "qemu-log.h"
28#include "net.h"
29#include "net/checksum.h"
30
669b4983 31#include "stream.h"
93f1e401
EI		 32
33#define DPHY(x)
34
35/* Advertisement control register. */
36#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
37#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
38#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
39#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
40
41struct PHY {
42 uint32_t regs[32];
43
44 int link;
45
46 unsigned int (*read)(struct PHY *phy, unsigned int req);
47 void (*write)(struct PHY *phy, unsigned int req,
48 unsigned int data);
49};
50
51static unsigned int tdk_read(struct PHY *phy, unsigned int req)
52{
53 int regnum;
54 unsigned r = 0;
55
56 regnum = req & 0x1f;
57
58 switch (regnum) {
59 case 1:
60 if (!phy->link) {
61 break;
62 }
63 /* MR1. */
64 /* Speeds and modes. */
65 r |= (1 << 13) | (1 << 14);
66 r |= (1 << 11) | (1 << 12);
67 r |= (1 << 5); /* Autoneg complete. */
68 r |= (1 << 3); /* Autoneg able. */
69 r |= (1 << 2); /* link. */
70 r |= (1 << 1); /* link. */
71 break;
72 case 5:
73 /* Link partner ability.
74 We are kind; always agree with whatever best mode
75 the guest advertises. */
76 r = 1 << 14; /* Success. */
77 /* Copy advertised modes. */
78 r |= phy->regs[4] & (15 << 5);
79 /* Autoneg support. */
80 r |= 1;
81 break;
82 case 17:
83 /* Marvel PHY on many xilinx boards. */
84 r = 0x8000; /* 1000Mb */
85 break;
86 case 18:
87 {
88 /* Diagnostics reg. */
89 int duplex = 0;
90 int speed_100 = 0;
91
92 if (!phy->link) {
93 break;
94 }
95
96 /* Are we advertising 100 half or 100 duplex ? */
97 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
98 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
99
100 /* Are we advertising 10 duplex or 100 duplex ? */
101 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
102 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
103 r = (speed_100 << 10) | (duplex << 11);
104 }
105 break;
106
107 default:
108 r = phy->regs[regnum];
109 break;
110 }
111 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
112 return r;
113}
114
115static void
116tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
117{
118 int regnum;
119
120 regnum = req & 0x1f;
121 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
122 switch (regnum) {
123 default:
124 phy->regs[regnum] = data;
125 break;
126 }
127}
128
129static void
130tdk_init(struct PHY *phy)
131{
132 phy->regs[0] = 0x3100;
133 /* PHY Id. */
134 phy->regs[2] = 0x0300;
135 phy->regs[3] = 0xe400;
136 /* Autonegotiation advertisement reg. */
137 phy->regs[4] = 0x01E1;
138 phy->link = 1;
139
140 phy->read = tdk_read;
141 phy->write = tdk_write;
142}
143
144struct MDIOBus {
145 /* bus. */
146 int mdc;
147 int mdio;
148
149 /* decoder. */
150 enum {
151 PREAMBLE,
152 SOF,
153 OPC,
154 ADDR,
155 REQ,
156 TURNAROUND,
157 DATA
158 } state;
159 unsigned int drive;
160
161 unsigned int cnt;
162 unsigned int addr;
163 unsigned int opc;
164 unsigned int req;
165 unsigned int data;
166
167 struct PHY *devs[32];
168};
169
170static void
171mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
172{
173 bus->devs[addr & 0x1f] = phy;
174}
175
176#ifdef USE_THIS_DEAD_CODE
177static void
178mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
179{
180 bus->devs[addr & 0x1f] = NULL;
181}
182#endif
183
184static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
185 unsigned int reg)
186{
187 struct PHY *phy;
188 uint16_t data;
189
190 phy = bus->devs[addr];
191 if (phy && phy->read) {
192 data = phy->read(phy, reg);
193 } else {
194 data = 0xffff;
195 }
196 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
197 return data;
198}
199
200static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
201 unsigned int reg, uint16_t data)
202{
203 struct PHY *phy;
204
205 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
206 phy = bus->devs[addr];
207 if (phy && phy->write) {
208 phy->write(phy, reg, data);
209 }
210}
211
212#define DENET(x)
213
214#define R_RAF (0x000 / 4)
215enum {
216 RAF_MCAST_REJ = (1 << 1),
217 RAF_BCAST_REJ = (1 << 2),
218 RAF_EMCF_EN = (1 << 12),
219 RAF_NEWFUNC_EN = (1 << 11)
220};
221
222#define R_IS (0x00C / 4)
223enum {
224 IS_HARD_ACCESS_COMPLETE = 1,
225 IS_AUTONEG = (1 << 1),
226 IS_RX_COMPLETE = (1 << 2),
227 IS_RX_REJECT = (1 << 3),
228 IS_TX_COMPLETE = (1 << 5),
229 IS_RX_DCM_LOCK = (1 << 6),
230 IS_MGM_RDY = (1 << 7),
231 IS_PHY_RST_DONE = (1 << 8),
232};
233
234#define R_IP (0x010 / 4)
235#define R_IE (0x014 / 4)
236#define R_UAWL (0x020 / 4)
237#define R_UAWU (0x024 / 4)
238#define R_PPST (0x030 / 4)
239enum {
240 PPST_LINKSTATUS = (1 << 0),
241 PPST_PHY_LINKSTATUS = (1 << 7),
242};
243
244#define R_STATS_RX_BYTESL (0x200 / 4)
245#define R_STATS_RX_BYTESH (0x204 / 4)
246#define R_STATS_TX_BYTESL (0x208 / 4)
247#define R_STATS_TX_BYTESH (0x20C / 4)
248#define R_STATS_RXL (0x290 / 4)
249#define R_STATS_RXH (0x294 / 4)
250#define R_STATS_RX_BCASTL (0x2a0 / 4)
251#define R_STATS_RX_BCASTH (0x2a4 / 4)
252#define R_STATS_RX_MCASTL (0x2a8 / 4)
253#define R_STATS_RX_MCASTH (0x2ac / 4)
254
255#define R_RCW0 (0x400 / 4)
256#define R_RCW1 (0x404 / 4)
257enum {
258 RCW1_VLAN = (1 << 27),
259 RCW1_RX = (1 << 28),
260 RCW1_FCS = (1 << 29),
261 RCW1_JUM = (1 << 30),
262 RCW1_RST = (1 << 31),
263};
264
265#define R_TC (0x408 / 4)
266enum {
267 TC_VLAN = (1 << 27),
268 TC_TX = (1 << 28),
269 TC_FCS = (1 << 29),
270 TC_JUM = (1 << 30),
271 TC_RST = (1 << 31),
272};
273
274#define R_EMMC (0x410 / 4)
275enum {
276 EMMC_LINKSPEED_10MB = (0 << 30),
277 EMMC_LINKSPEED_100MB = (1 << 30),
278 EMMC_LINKSPEED_1000MB = (2 << 30),
279};
280
281#define R_PHYC (0x414 / 4)
282
283#define R_MC (0x500 / 4)
284#define MC_EN (1 << 6)
285
286#define R_MCR (0x504 / 4)
287#define R_MWD (0x508 / 4)
288#define R_MRD (0x50c / 4)
289#define R_MIS (0x600 / 4)
290#define R_MIP (0x620 / 4)
291#define R_MIE (0x640 / 4)
292#define R_MIC (0x640 / 4)
293
294#define R_UAW0 (0x700 / 4)
295#define R_UAW1 (0x704 / 4)
296#define R_FMI (0x708 / 4)
297#define R_AF0 (0x710 / 4)
298#define R_AF1 (0x714 / 4)
299#define R_MAX (0x34 / 4)
300
301/* Indirect registers. */
302struct TEMAC {
303 struct MDIOBus mdio_bus;
304 struct PHY phy;
305
306 void *parent;
307};
308
309struct XilinxAXIEnet {
310 SysBusDevice busdev;
0dc31f3b 311 MemoryRegion iomem;
93f1e401 312 qemu_irq irq;
669b4983 313 StreamSlave *tx_dev;
93f1e401
EI		 314 NICState *nic;
315 NICConf conf;
316
317
318 uint32_t c_rxmem;
319 uint32_t c_txmem;
320 uint32_t c_phyaddr;
321
322 struct TEMAC TEMAC;
323
324 /* MII regs. */
325 union {
326 uint32_t regs[4];
327 struct {
328 uint32_t mc;
329 uint32_t mcr;
330 uint32_t mwd;
331 uint32_t mrd;
332 };
333 } mii;
334
335 struct {
336 uint64_t rx_bytes;
337 uint64_t tx_bytes;
338
339 uint64_t rx;
340 uint64_t rx_bcast;
341 uint64_t rx_mcast;
342 } stats;
343
344 /* Receive configuration words. */
345 uint32_t rcw[2];
346 /* Transmit config. */
347 uint32_t tc;
348 uint32_t emmc;
349 uint32_t phyc;
350
351 /* Unicast Address Word. */
352 uint32_t uaw[2];
353 /* Unicast address filter used with extended mcast. */
354 uint32_t ext_uaw[2];
355 uint32_t fmi;
356
357 uint32_t regs[R_MAX];
358
359 /* Multicast filter addrs. */
360 uint32_t maddr[4][2];
361 /* 32K x 1 lookup filter. */
362 uint32_t ext_mtable[1024];
363
364
365 uint8_t *rxmem;
366};
367
368static void axienet_rx_reset(struct XilinxAXIEnet *s)
369{
370 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
371}
372
373static void axienet_tx_reset(struct XilinxAXIEnet *s)
374{
375 s->tc = TC_JUM | TC_TX | TC_VLAN;
376}
377
378static inline int axienet_rx_resetting(struct XilinxAXIEnet *s)
379{
380 return s->rcw[1] & RCW1_RST;
381}
382
383static inline int axienet_rx_enabled(struct XilinxAXIEnet *s)
384{
385 return s->rcw[1] & RCW1_RX;
386}
387
388static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s)
389{
390 return !!(s->regs[R_RAF] & RAF_EMCF_EN);
391}
392
393static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s)
394{
395 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
396}
397
398static void axienet_reset(struct XilinxAXIEnet *s)
399{
400 axienet_rx_reset(s);
401 axienet_tx_reset(s);
402
403 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
404 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
405
406 s->emmc = EMMC_LINKSPEED_100MB;
407}
408
409static void enet_update_irq(struct XilinxAXIEnet *s)
410{
411 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
412 qemu_set_irq(s->irq, !!s->regs[R_IP]);
413}
414
a8170e5e 415static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
93f1e401
EI		 416{
417 struct XilinxAXIEnet *s = opaque;
418 uint32_t r = 0;
419 addr >>= 2;
420
421 switch (addr) {
422 case R_RCW0:
423 case R_RCW1:
424 r = s->rcw[addr & 1];
425 break;
426
427 case R_TC:
428 r = s->tc;
429 break;
430
431 case R_EMMC:
432 r = s->emmc;
433 break;
434
435 case R_PHYC:
436 r = s->phyc;
437 break;
438
439 case R_MCR:
440 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */
441 break;
442
443 case R_STATS_RX_BYTESL:
444 case R_STATS_RX_BYTESH:
445 r = s->stats.rx_bytes >> (32 * (addr & 1));
446 break;
447
448 case R_STATS_TX_BYTESL:
449 case R_STATS_TX_BYTESH:
450 r = s->stats.tx_bytes >> (32 * (addr & 1));
451 break;
452
453 case R_STATS_RXL:
454 case R_STATS_RXH:
455 r = s->stats.rx >> (32 * (addr & 1));
456 break;
457 case R_STATS_RX_BCASTL:
458 case R_STATS_RX_BCASTH:
459 r = s->stats.rx_bcast >> (32 * (addr & 1));
460 break;
461 case R_STATS_RX_MCASTL:
462 case R_STATS_RX_MCASTH:
463 r = s->stats.rx_mcast >> (32 * (addr & 1));
464 break;
465
466 case R_MC:
467 case R_MWD:
468 case R_MRD:
469 r = s->mii.regs[addr & 3];
470 break;
471
472 case R_UAW0:
473 case R_UAW1:
474 r = s->uaw[addr & 1];
475 break;
476
477 case R_UAWU:
478 case R_UAWL:
479 r = s->ext_uaw[addr & 1];
480 break;
481
482 case R_FMI:
483 r = s->fmi;
484 break;
485
486 case R_AF0:
487 case R_AF1:
488 r = s->maddr[s->fmi & 3][addr & 1];
489 break;
490
491 case 0x8000 ... 0x83ff:
492 r = s->ext_mtable[addr - 0x8000];
493 break;
494
495 default:
496 if (addr < ARRAY_SIZE(s->regs)) {
497 r = s->regs[addr];
498 }
499 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
500 __func__, addr * 4, r));
501 break;
502 }
503 return r;
504}
505
a8170e5e 506static void enet_write(void *opaque, hwaddr addr,
0dc31f3b 507 uint64_t value, unsigned size)
93f1e401
EI		 508{
509 struct XilinxAXIEnet *s = opaque;
510 struct TEMAC *t = &s->TEMAC;
511
512 addr >>= 2;
513 switch (addr) {
514 case R_RCW0:
515 case R_RCW1:
516 s->rcw[addr & 1] = value;
517 if ((addr & 1) && value & RCW1_RST) {
518 axienet_rx_reset(s);
519 }
520 break;
521
522 case R_TC:
523 s->tc = value;
524 if (value & TC_RST) {
525 axienet_tx_reset(s);
526 }
527 break;
528
529 case R_EMMC:
530 s->emmc = value;
531 break;
532
533 case R_PHYC:
534 s->phyc = value;
535 break;
536
537 case R_MC:
538 value &= ((1 < 7) - 1);
539
540 /* Enable the MII. */
541 if (value & MC_EN) {
542 unsigned int miiclkdiv = value & ((1 << 6) - 1);
543 if (!miiclkdiv) {
544 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
545 }
546 }
547 s->mii.mc = value;
548 break;
549
550 case R_MCR: {
551 unsigned int phyaddr = (value >> 24) & 0x1f;
552 unsigned int regaddr = (value >> 16) & 0x1f;
553 unsigned int op = (value >> 14) & 3;
554 unsigned int initiate = (value >> 11) & 1;
555
556 if (initiate) {
557 if (op == 1) {
558 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
559 } else if (op == 2) {
560 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
561 } else {
562 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
563 }
564 }
565 s->mii.mcr = value;
566 break;
567 }
568
569 case R_MWD:
570 case R_MRD:
571 s->mii.regs[addr & 3] = value;
572 break;
573
574
575 case R_UAW0:
576 case R_UAW1:
577 s->uaw[addr & 1] = value;
578 break;
579
580 case R_UAWL:
581 case R_UAWU:
582 s->ext_uaw[addr & 1] = value;
583 break;
584
585 case R_FMI:
586 s->fmi = value;
587 break;
588
589 case R_AF0:
590 case R_AF1:
591 s->maddr[s->fmi & 3][addr & 1] = value;
592 break;
593
d4d230da
PC		 594 case R_IS:
595 s->regs[addr] &= ~value;
596 break;
597
93f1e401
EI		 598 case 0x8000 ... 0x83ff:
599 s->ext_mtable[addr - 0x8000] = value;
600 break;
601
602 default:
603 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
0dc31f3b 604 __func__, addr * 4, (unsigned)value));
93f1e401
EI		 605 if (addr < ARRAY_SIZE(s->regs)) {
606 s->regs[addr] = value;
607 }
608 break;
609 }
610 enet_update_irq(s);
611}
612
0dc31f3b
AK		 613static const MemoryRegionOps enet_ops = {
614 .read = enet_read,
615 .write = enet_write,
616 .endianness = DEVICE_LITTLE_ENDIAN,
93f1e401
EI		 617};
618
4e68f7a0 619static int eth_can_rx(NetClientState *nc)
93f1e401
EI		 620{
621 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
622
623 /* RX enabled? */
624 return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
625}
626
627static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
628{
629 int match = 1;
630
631 if (memcmp(buf, &f0, 4)) {
632 match = 0;
633 }
634
635 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
636 match = 0;
637 }
638
639 return match;
640}
641
4e68f7a0 642static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
93f1e401
EI		 643{
644 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
645 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
646 0xff, 0xff, 0xff};
647 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
648 uint32_t app[6] = {0};
649 int promisc = s->fmi & (1 << 31);
650 int unicast, broadcast, multicast, ip_multicast = 0;
651 uint32_t csum32;
652 uint16_t csum16;
653 int i;
654
93f1e401
EI		 655 DENET(qemu_log("%s: %zd bytes\n", __func__, size));
656
657 unicast = ~buf[0] & 0x1;
658 broadcast = memcmp(buf, sa_bcast, 6) == 0;
659 multicast = !unicast && !broadcast;
660 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
661 ip_multicast = 1;
662 }
663
664 /* Jumbo or vlan sizes ? */
665 if (!(s->rcw[1] & RCW1_JUM)) {
666 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
667 return size;
668 }
669 }
670
671 /* Basic Address filters. If you want to use the extended filters
672 you'll generally have to place the ethernet mac into promiscuous mode
673 to avoid the basic filtering from dropping most frames. */
674 if (!promisc) {
675 if (unicast) {
676 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
677 return size;
678 }
679 } else {
680 if (broadcast) {
681 /* Broadcast. */
682 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
683 return size;
684 }
685 } else {
686 int drop = 1;
687
688 /* Multicast. */
689 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
690 return size;
691 }
692
693 for (i = 0; i < 4; i++) {
694 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
695 drop = 0;
696 break;
697 }
698 }
699
700 if (drop) {
701 return size;
702 }
703 }
704 }
705 }
706
707 /* Extended mcast filtering enabled? */
708 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
709 if (unicast) {
710 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
711 return size;
712 }
713 } else {
714 if (broadcast) {
715 /* Broadcast. ??? */
716 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
717 return size;
718 }
719 } else {
720 int idx, bit;
721
722 /* Multicast. */
723 if (!memcmp(buf, sa_ipmcast, 3)) {
724 return size;
725 }
726
727 idx = (buf[4] & 0x7f) << 8;
728 idx |= buf[5];
729
730 bit = 1 << (idx & 0x1f);
731 idx >>= 5;
732
733 if (!(s->ext_mtable[idx] & bit)) {
734 return size;
735 }
736 }
737 }
738 }
739
740 if (size < 12) {
741 s->regs[R_IS] |= IS_RX_REJECT;
742 enet_update_irq(s);
743 return -1;
744 }
745
746 if (size > (s->c_rxmem - 4)) {
747 size = s->c_rxmem - 4;
748 }
749
750 memcpy(s->rxmem, buf, size);
751 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */
752
753 if (s->rcw[1] & RCW1_FCS) {
754 size += 4; /* fcs is inband. */
755 }
756
757 app[0] = 5 << 28;
758 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
759 /* Fold it once. */
760 csum32 = (csum32 & 0xffff) + (csum32 >> 16);
761 /* And twice to get rid of possible carries. */
762 csum16 = (csum32 & 0xffff) + (csum32 >> 16);
763 app[3] = csum16;
764 app[4] = size & 0xffff;
765
766 s->stats.rx_bytes += size;
767 s->stats.rx++;
768 if (multicast) {
769 s->stats.rx_mcast++;
770 app[2] |= 1 | (ip_multicast << 1);
771 } else if (broadcast) {
772 s->stats.rx_bcast++;
773 app[2] |= 1 << 3;
774 }
775
776 /* Good frame. */
777 app[2] |= 1 << 6;
778
669b4983 779 stream_push(s->tx_dev, (void *)s->rxmem, size, app);
93f1e401
EI		 780
781 s->regs[R_IS] |= IS_RX_COMPLETE;
782 enet_update_irq(s);
783 return size;
784}
785
4e68f7a0 786static void eth_cleanup(NetClientState *nc)
93f1e401
EI		 787{
788 /* FIXME. */
789 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
7267c094
AL		 790 g_free(s->rxmem);
791 g_free(s);
93f1e401
EI		 792}
793
794static void
669b4983 795axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr)
93f1e401 796{
669b4983 797 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
93f1e401
EI		 798
799 /* TX enable ? */
800 if (!(s->tc & TC_TX)) {
801 return;
802 }
803
804 /* Jumbo or vlan sizes ? */
805 if (!(s->tc & TC_JUM)) {
806 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
807 return;
808 }
809 }
810
811 if (hdr[0] & 1) {
812 unsigned int start_off = hdr[1] >> 16;
813 unsigned int write_off = hdr[1] & 0xffff;
814 uint32_t tmp_csum;
815 uint16_t csum;
816
817 tmp_csum = net_checksum_add(size - start_off,
818 (uint8_t *)buf + start_off);
819 /* Accumulate the seed. */
820 tmp_csum += hdr[2] & 0xffff;
821
822 /* Fold the 32bit partial checksum. */
823 csum = net_checksum_finish(tmp_csum);
824
825 /* Writeback. */
826 buf[write_off] = csum >> 8;
827 buf[write_off + 1] = csum & 0xff;
828 }
829
830 qemu_send_packet(&s->nic->nc, buf, size);
831
832 s->stats.tx_bytes += size;
833 s->regs[R_IS] |= IS_TX_COMPLETE;
834 enet_update_irq(s);
835}
836
837static NetClientInfo net_xilinx_enet_info = {
2be64a68 838 .type = NET_CLIENT_OPTIONS_KIND_NIC,
93f1e401
EI		 839 .size = sizeof(NICState),
840 .can_receive = eth_can_rx,
841 .receive = eth_rx,
842 .cleanup = eth_cleanup,
843};
844
845static int xilinx_enet_init(SysBusDevice *dev)
846{
847 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
93f1e401
EI		 848
849 sysbus_init_irq(dev, &s->irq);
850
0dc31f3b 851 memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
750ecd44 852 sysbus_init_mmio(dev, &s->iomem);
93f1e401
EI		 853
854 qemu_macaddr_default_if_unset(&s->conf.macaddr);
855 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
f79f2bfc 856 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
93f1e401
EI		 857 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
858
859 tdk_init(&s->TEMAC.phy);
860 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
861
862 s->TEMAC.parent = s;
863
7267c094 864 s->rxmem = g_malloc(s->c_rxmem);
93f1e401
EI		 865 axienet_reset(s);
866
867 return 0;
868}
869
669b4983
PC		 870static void xilinx_enet_initfn(Object *obj)
871{
872 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
873
874 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
875 (Object **) &s->tx_dev, NULL);
876}
877
999e12bb
AL		 878static Property xilinx_enet_properties[] = {
879 DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7),
ab034c26
PC		 880 DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000),
881 DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000),
999e12bb
AL		 882 DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf),
883 DEFINE_PROP_END_OF_LIST(),
884};
885
886static void xilinx_enet_class_init(ObjectClass *klass, void *data)
887{
39bffca2 888 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 889 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
669b4983 890 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
999e12bb
AL		 891
892 k->init = xilinx_enet_init;
39bffca2 893 dc->props = xilinx_enet_properties;
669b4983 894 ssc->push = axienet_stream_push;
999e12bb
AL		 895}
896
39bffca2 897static TypeInfo xilinx_enet_info = {
cec6f8ca 898 .name = "xlnx.axi-ethernet",
39bffca2
AL		 899 .parent = TYPE_SYS_BUS_DEVICE,
900 .instance_size = sizeof(struct XilinxAXIEnet),
901 .class_init = xilinx_enet_class_init,
669b4983
PC		 902 .instance_init = xilinx_enet_initfn,
903 .interfaces = (InterfaceInfo[]) {
904 { TYPE_STREAM_SLAVE },
905 { }
906 }
93f1e401 907};
83f7d43a
AF		 908
909static void xilinx_enet_register_types(void)
93f1e401 910{
39bffca2 911 type_register_static(&xilinx_enet_info);
93f1e401
EI		 912}
913
83f7d43a 914type_init(xilinx_enet_register_types)
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