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1 | /* |
2 | * linux/include/asm-arm/arch-clps711x/hardware.h | |
3 | * | |
4 | * This file contains the hardware definitions of the Prospector P720T. | |
5 | * | |
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #ifndef __ASM_ARCH_HARDWARE_H | |
23 | #define __ASM_ARCH_HARDWARE_H | |
24 | ||
1da177e4 LT |
25 | |
26 | #define CLPS7111_VIRT_BASE 0xff000000 | |
27 | #define CLPS7111_BASE CLPS7111_VIRT_BASE | |
28 | ||
29 | /* | |
30 | * The physical addresses that the external chip select signals map to is | |
31 | * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 | |
32 | * processors. CONFIG_EP72XX_BOOT_ROM is only available if these | |
33 | * processors are in use. | |
34 | */ | |
35 | #ifndef CONFIG_EP72XX_ROM_BOOT | |
36 | #define CS0_PHYS_BASE (0x00000000) | |
37 | #define CS1_PHYS_BASE (0x10000000) | |
38 | #define CS2_PHYS_BASE (0x20000000) | |
39 | #define CS3_PHYS_BASE (0x30000000) | |
40 | #define CS4_PHYS_BASE (0x40000000) | |
41 | #define CS5_PHYS_BASE (0x50000000) | |
42 | #define CS6_PHYS_BASE (0x60000000) | |
43 | #define CS7_PHYS_BASE (0x70000000) | |
44 | #else | |
45 | #define CS0_PHYS_BASE (0x70000000) | |
46 | #define CS1_PHYS_BASE (0x60000000) | |
47 | #define CS2_PHYS_BASE (0x50000000) | |
48 | #define CS3_PHYS_BASE (0x40000000) | |
49 | #define CS4_PHYS_BASE (0x30000000) | |
50 | #define CS5_PHYS_BASE (0x20000000) | |
51 | #define CS6_PHYS_BASE (0x10000000) | |
52 | #define CS7_PHYS_BASE (0x00000000) | |
53 | #endif | |
54 | ||
55 | #if defined (CONFIG_ARCH_EP7211) | |
56 | ||
57 | #define EP7211_VIRT_BASE CLPS7111_VIRT_BASE | |
58 | #define EP7211_BASE CLPS7111_VIRT_BASE | |
59 | #include <asm/hardware/ep7211.h> | |
60 | ||
61 | #elif defined (CONFIG_ARCH_EP7212) | |
62 | ||
63 | #define EP7212_VIRT_BASE CLPS7111_VIRT_BASE | |
64 | #define EP7212_BASE CLPS7111_VIRT_BASE | |
65 | #include <asm/hardware/ep7212.h> | |
66 | ||
67 | #endif | |
68 | ||
69 | #define SYSPLD_VIRT_BASE 0xfe000000 | |
70 | #define SYSPLD_BASE SYSPLD_VIRT_BASE | |
71 | ||
72 | #ifndef __ASSEMBLER__ | |
73 | ||
74 | #define PCIO_BASE IO_BASE | |
75 | ||
76 | #endif | |
77 | ||
78 | ||
79 | #if defined (CONFIG_ARCH_AUTCPU12) | |
80 | ||
81 | #define CS89712_VIRT_BASE CLPS7111_VIRT_BASE | |
82 | #define CS89712_BASE CLPS7111_VIRT_BASE | |
83 | ||
84 | #include <asm/hardware/clps7111.h> | |
85 | #include <asm/hardware/ep7212.h> | |
86 | #include <asm/hardware/cs89712.h> | |
87 | ||
88 | #endif | |
89 | ||
90 | ||
91 | #if defined (CONFIG_ARCH_CDB89712) | |
92 | ||
93 | #include <asm/hardware/clps7111.h> | |
94 | #include <asm/hardware/ep7212.h> | |
95 | #include <asm/hardware/cs89712.h> | |
96 | ||
97 | /* dynamic ioremap() areas */ | |
98 | #define FLASH_START 0x00000000 | |
99 | #define FLASH_SIZE 0x800000 | |
100 | #define FLASH_WIDTH 4 | |
101 | ||
102 | #define SRAM_START 0x60000000 | |
103 | #define SRAM_SIZE 0xc000 | |
104 | #define SRAM_WIDTH 4 | |
105 | ||
106 | #define BOOTROM_START 0x70000000 | |
107 | #define BOOTROM_SIZE 0x80 | |
108 | #define BOOTROM_WIDTH 4 | |
109 | ||
110 | ||
111 | /* static cdb89712_map_io() areas */ | |
112 | #define REGISTER_START 0x80000000 | |
113 | #define REGISTER_SIZE 0x4000 | |
114 | #define REGISTER_BASE 0xff000000 | |
115 | ||
116 | #define ETHER_START 0x20000000 | |
117 | #define ETHER_SIZE 0x1000 | |
118 | #define ETHER_BASE 0xfe000000 | |
119 | ||
120 | #endif | |
121 | ||
122 | ||
123 | #if defined (CONFIG_ARCH_EDB7211) | |
124 | ||
125 | /* | |
126 | * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) | |
127 | * and repeat across it. This is the mapping for it. | |
128 | * | |
129 | * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This | |
130 | * was cause for much consternation and headscratching. This should probably | |
131 | * be made a compile/run time kernel option. | |
132 | */ | |
133 | #define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */ | |
134 | ||
135 | #define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */ | |
136 | ||
137 | ||
138 | /* | |
139 | * The CS8900A ethernet chip has its I/O registers wired to chip select 2 | |
140 | * (nCS2). This is the mapping for it. | |
141 | * | |
142 | * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This | |
143 | * was cause for much consternation and headscratching. This should probably | |
144 | * be made a compile/run time kernel option. | |
145 | */ | |
146 | #define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */ | |
147 | ||
148 | #define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */ | |
149 | ||
150 | ||
151 | /* | |
152 | * The two flash banks are wired to chip selects 0 and 1. This is the mapping | |
153 | * for them. | |
154 | * | |
155 | * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running | |
156 | * in jumpered boot mode. | |
157 | */ | |
158 | #define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ | |
159 | #define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ | |
160 | ||
161 | #define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */ | |
162 | #define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */ | |
163 | ||
164 | #endif /* CONFIG_ARCH_EDB7211 */ | |
165 | ||
166 | ||
167 | /* | |
168 | * Relevant bits in port D, which controls power to the various parts of | |
169 | * the LCD on the EDB7211. | |
170 | */ | |
171 | #define EDB_PD1_LCD_DC_DC_EN (1<<1) | |
172 | #define EDB_PD2_LCDEN (1<<2) | |
173 | #define EDB_PD3_LCDBL (1<<3) | |
174 | ||
175 | ||
176 | #if defined (CONFIG_ARCH_CEIVA) | |
177 | ||
178 | #define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE | |
179 | #define CEIVA_BASE CLPS7111_VIRT_BASE | |
180 | ||
181 | #include <asm/hardware/clps7111.h> | |
182 | #include <asm/hardware/ep7212.h> | |
183 | ||
184 | ||
185 | /* | |
186 | * The two flash banks are wired to chip selects 0 and 1. This is the mapping | |
187 | * for them. | |
188 | * | |
189 | * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running | |
190 | * in jumpered boot mode. | |
191 | */ | |
192 | #define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ | |
193 | #define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ | |
194 | ||
195 | #define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */ | |
196 | #define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */ | |
197 | ||
198 | #define CEIVA_FLASH_SIZE 0x100000 | |
199 | #define CEIVA_FLASH_WIDTH 2 | |
200 | ||
201 | #define SRAM_START 0x60000000 | |
202 | #define SRAM_SIZE 0xc000 | |
203 | #define SRAM_WIDTH 4 | |
204 | ||
205 | #define BOOTROM_START 0x70000000 | |
206 | #define BOOTROM_SIZE 0x80 | |
207 | #define BOOTROM_WIDTH 4 | |
208 | ||
209 | /* | |
210 | * SED1355 LCD controller | |
211 | */ | |
212 | #define CEIVA_PHYS_SED1355 CS2_PHYS_BASE | |
213 | #define CEIVA_VIRT_SED1355 (0xfc000000) | |
214 | ||
215 | /* | |
216 | * Relevant bits in port D, which controls power to the various parts of | |
217 | * the LCD on the Ceiva Photo Max, and reset to the LCD controller. | |
218 | */ | |
219 | ||
220 | // Reset line to SED1355 (must be high to operate) | |
221 | #define CEIVA_PD1_LCDRST (1<<1) | |
222 | // LCD panel enable (set to one, to enable LCD) | |
223 | #define CEIVA_PD4_LCDEN (1<<4) | |
224 | // Backlight (set to one, to turn on backlight | |
225 | #define CEIVA_PD5_LCDBL (1<<5) | |
226 | ||
227 | /* | |
228 | * Relevant bits in port B, which report the status of the buttons. | |
229 | */ | |
230 | ||
231 | // White button | |
232 | #define CEIVA_PB4_WHT_BTN (1<<4) | |
233 | // Black button | |
234 | #define CEIVA_PB0_BLK_BTN (1<<0) | |
235 | #endif // #if defined (CONFIG_ARCH_CEIVA) | |
236 | ||
237 | #endif |