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1 | /* |
2 | * linux/include/asm-arm/arch-ixp2000/io.h | |
3 | * | |
4 | * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> | |
5 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | |
6 | * | |
7 | * Copyright (C) 2002 Intel Corp. | |
8 | * Copyrgiht (C) 2003-2004 MontaVista Software, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #ifndef __ASM_ARM_ARCH_IO_H | |
16 | #define __ASM_ARM_ARCH_IO_H | |
17 | ||
18 | #define IO_SPACE_LIMIT 0xffffffff | |
19 | #define __mem_pci(a) (a) | |
20 | #define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) | |
21 | ||
22 | /* | |
23 | * The IXP2400 before revision B0 asserts byte lanes for PCI I/O | |
24 | * transactions the other way round (MEM transactions don't have this | |
25 | * issue), so we need to override the standard functions. B0 and later | |
26 | * have a bit that can be set to 1 to get the 'proper' behavior, but | |
27 | * since that isn't available on the A? revisions we just keep doing | |
28 | * things manually. | |
29 | */ | |
30 | #define alignb(addr) (void __iomem *)((unsigned long)addr ^ 3) | |
31 | #define alignw(addr) (void __iomem *)((unsigned long)addr ^ 2) | |
32 | ||
33 | #define outb(v,p) __raw_writeb((v),alignb(___io(p))) | |
34 | #define outw(v,p) __raw_writew((v),alignw(___io(p))) | |
35 | #define outl(v,p) __raw_writel((v),___io(p)) | |
36 | ||
37 | #define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; }) | |
38 | #define inw(p) \ | |
39 | ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; }) | |
40 | #define inl(p) \ | |
41 | ({ unsigned int __v = (__raw_readl(___io(p))); __v; }) | |
42 | ||
43 | #define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l) | |
44 | #define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l) | |
45 | #define outsl(p,d,l) __raw_writesl(___io(p),d,l) | |
46 | ||
47 | #define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l) | |
48 | #define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) | |
49 | #define insl(p,d,l) __raw_readsl(___io(p),d,l) | |
50 | ||
51 | ||
52 | #ifdef CONFIG_ARCH_IXDP2X01 | |
53 | /* | |
54 | * This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort | |
55 | * of "I/O space" and is just direct mapped into a 32-bit-only addressable | |
56 | * bus. The address space for this bus is such that we can't really easily | |
57 | * make it contiguous to the PCI I/O address range, and it also does not | |
58 | * need swapping like PCI addresses do (IXDP2x01 is a BE platform). | |
59 | * B/C of this we can't use the standard in/out functions and need to | |
60 | * runtime check if the incoming address is a PCI address or for | |
61 | * the CS89x0. | |
62 | */ | |
63 | #undef inw | |
64 | #undef outw | |
65 | #undef insw | |
66 | #undef outsw | |
67 | ||
68 | #include <asm/mach-types.h> | |
69 | ||
70 | static inline void insw(u32 ptr, void *buf, int length) | |
71 | { | |
72 | register volatile u32 *port = (volatile u32 *)ptr; | |
73 | ||
74 | /* | |
75 | * Is this cycle meant for the CS8900? | |
76 | */ | |
77 | if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && | |
78 | ((port >= IXDP2X01_CS8900_VIRT_BASE) && | |
79 | (port <= IXDP2X01_CS8900_VIRT_END))) { | |
80 | u8 *buf8 = (u8*)buf; | |
81 | register u32 tmp32; | |
82 | ||
83 | do { | |
84 | tmp32 = *port; | |
85 | *buf8++ = (u8)tmp32; | |
86 | *buf8++ = (u8)(tmp32 >> 8); | |
87 | } while(--length); | |
88 | ||
89 | return; | |
90 | } | |
91 | ||
92 | __raw_readsw(alignw(___io(ptr)),buf,length); | |
93 | } | |
94 | ||
95 | static inline void outsw(u32 ptr, void *buf, int length) | |
96 | { | |
97 | register volatile u32 *port = (volatile u32 *)ptr; | |
98 | ||
99 | /* | |
100 | * Is this cycle meant for the CS8900? | |
101 | */ | |
102 | if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && | |
103 | ((port >= IXDP2X01_CS8900_VIRT_BASE) && | |
104 | (port <= IXDP2X01_CS8900_VIRT_END))) { | |
105 | register u32 tmp32; | |
106 | u8 *buf8 = (u8*)buf; | |
107 | do { | |
108 | tmp32 = *buf8++; | |
109 | tmp32 |= (*buf8++) << 8; | |
110 | *port = tmp32; | |
111 | } while(--length); | |
112 | return; | |
113 | } | |
114 | ||
115 | __raw_writesw(alignw(___io(ptr)),buf,length); | |
116 | } | |
117 | ||
118 | ||
119 | static inline u16 inw(u32 ptr) | |
120 | { | |
121 | register volatile u32 *port = (volatile u32 *)ptr; | |
122 | ||
123 | /* | |
124 | * Is this cycle meant for the CS8900? | |
125 | */ | |
126 | if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && | |
127 | ((port >= IXDP2X01_CS8900_VIRT_BASE) && | |
128 | (port <= IXDP2X01_CS8900_VIRT_END))) { | |
129 | return (u16)(*port); | |
130 | } | |
131 | ||
132 | return __raw_readw(alignw(___io(ptr))); | |
133 | } | |
134 | ||
135 | static inline void outw(u16 value, u32 ptr) | |
136 | { | |
137 | register volatile u32 *port = (volatile u32 *)ptr; | |
138 | ||
139 | if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && | |
140 | ((port >= IXDP2X01_CS8900_VIRT_BASE) && | |
141 | (port <= IXDP2X01_CS8900_VIRT_END))) { | |
142 | *port = value; | |
143 | return; | |
144 | } | |
145 | ||
146 | __raw_writew((value),alignw(___io(ptr))); | |
147 | } | |
148 | #endif /* IXDP2x01 */ | |
149 | ||
150 | #endif |