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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/arch-ixp4xx/io.h | |
3 | * | |
4 | * Author: Deepak Saxena <dsaxena@plexity.net> | |
5 | * | |
450008b5 | 6 | * Copyright (C) 2002-2005 MontaVista Software, Inc. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARM_ARCH_IO_H | |
14 | #define __ASM_ARM_ARCH_IO_H | |
15 | ||
8e93675e RW |
16 | #include <linux/bitops.h> |
17 | ||
be509729 | 18 | #include <asm/arch/hardware.h> |
1da177e4 LT |
19 | |
20 | #define IO_SPACE_LIMIT 0xffff0000 | |
21 | ||
1da177e4 LT |
22 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); |
23 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |
24 | ||
25 | ||
26 | /* | |
27 | * IXP4xx provides two methods of accessing PCI memory space: | |
28 | * | |
29 | * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | |
30 | * To access PCI via this space, we simply ioremap() the BAR | |
31 | * into the kernel and we can use the standard read[bwl]/write[bwl] | |
32 | * macros. This is the preffered method due to speed but it | |
33 | * limits the system to just 64MB of PCI memory. This can be | |
34 | * problamatic if using video cards and other memory-heavy | |
35 | * targets. | |
36 | * | |
37 | * 2) If > 64MB of memory space is required, the IXP4xx can be configured | |
38 | * to use indirect registers to access PCI (as we do below for I/O | |
39 | * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) | |
fd245f00 | 40 | * of memory on the bus. The disadvantage of this is that every |
1da177e4 LT |
41 | * PCI access requires three local register accesses plus a spinlock, |
42 | * but in some cases the performance hit is acceptable. In addition, | |
43 | * you cannot mmap() PCI devices in this case. | |
44 | * | |
45 | */ | |
46 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
47 | ||
48 | #define __mem_pci(a) (a) | |
49 | ||
50 | #else | |
51 | ||
52 | #include <linux/mm.h> | |
53 | ||
54 | /* | |
55 | * In the case of using indirect PCI, we simply return the actual PCI | |
56 | * address and our read/write implementation use that to drive the | |
57 | * access registers. If something outside of PCI is ioremap'd, we | |
58 | * fallback to the default. | |
59 | */ | |
60 | static inline void __iomem * | |
3603ab2b | 61 | __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) |
1da177e4 | 62 | { |
45fba084 | 63 | if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) |
3603ab2b | 64 | return __arm_ioremap(addr, size, mtype); |
1da177e4 | 65 | |
d2936b19 | 66 | return (void __iomem *)addr; |
1da177e4 LT |
67 | } |
68 | ||
69 | static inline void | |
70 | __ixp4xx_iounmap(void __iomem *addr) | |
71 | { | |
d2936b19 | 72 | if ((__force u32)addr >= VMALLOC_START) |
1da177e4 LT |
73 | __iounmap(addr); |
74 | } | |
75 | ||
67a1901f | 76 | #define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) |
1da177e4 LT |
77 | #define __arch_iounmap(a) __ixp4xx_iounmap(a) |
78 | ||
bfca9459 JB |
79 | #define writeb(v, p) __ixp4xx_writeb(v, p) |
80 | #define writew(v, p) __ixp4xx_writew(v, p) | |
81 | #define writel(v, p) __ixp4xx_writel(v, p) | |
1da177e4 LT |
82 | |
83 | #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) | |
84 | #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) | |
85 | #define writesl(p, v, l) __ixp4xx_writesl(p, v, l) | |
86 | ||
87 | #define readb(p) __ixp4xx_readb(p) | |
88 | #define readw(p) __ixp4xx_readw(p) | |
89 | #define readl(p) __ixp4xx_readl(p) | |
90 | ||
91 | #define readsb(p, v, l) __ixp4xx_readsb(p, v, l) | |
92 | #define readsw(p, v, l) __ixp4xx_readsw(p, v, l) | |
93 | #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) | |
94 | ||
95 | static inline void | |
bfca9459 | 96 | __ixp4xx_writeb(u8 value, volatile void __iomem *p) |
1da177e4 | 97 | { |
bfca9459 | 98 | u32 addr = (u32)p; |
1da177e4 LT |
99 | u32 n, byte_enables, data; |
100 | ||
101 | if (addr >= VMALLOC_START) { | |
102 | __raw_writeb(value, addr); | |
103 | return; | |
104 | } | |
105 | ||
106 | n = addr % 4; | |
107 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
108 | data = value << (8*n); | |
109 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
110 | } | |
111 | ||
112 | static inline void | |
bfca9459 | 113 | __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) |
1da177e4 LT |
114 | { |
115 | while (count--) | |
116 | writeb(*vaddr++, bus_addr); | |
117 | } | |
118 | ||
119 | static inline void | |
bfca9459 | 120 | __ixp4xx_writew(u16 value, volatile void __iomem *p) |
1da177e4 | 121 | { |
bfca9459 | 122 | u32 addr = (u32)p; |
1da177e4 LT |
123 | u32 n, byte_enables, data; |
124 | ||
125 | if (addr >= VMALLOC_START) { | |
126 | __raw_writew(value, addr); | |
127 | return; | |
128 | } | |
129 | ||
130 | n = addr % 4; | |
131 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
132 | data = value << (8*n); | |
133 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | |
134 | } | |
135 | ||
136 | static inline void | |
bfca9459 | 137 | __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) |
1da177e4 LT |
138 | { |
139 | while (count--) | |
140 | writew(*vaddr++, bus_addr); | |
141 | } | |
142 | ||
143 | static inline void | |
bfca9459 | 144 | __ixp4xx_writel(u32 value, volatile void __iomem *p) |
1da177e4 | 145 | { |
d2936b19 | 146 | u32 addr = (__force u32)p; |
1da177e4 | 147 | if (addr >= VMALLOC_START) { |
d2936b19 | 148 | __raw_writel(value, p); |
1da177e4 LT |
149 | return; |
150 | } | |
151 | ||
152 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | |
153 | } | |
154 | ||
155 | static inline void | |
bfca9459 | 156 | __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) |
1da177e4 LT |
157 | { |
158 | while (count--) | |
159 | writel(*vaddr++, bus_addr); | |
160 | } | |
161 | ||
162 | static inline unsigned char | |
bfca9459 | 163 | __ixp4xx_readb(const volatile void __iomem *p) |
1da177e4 | 164 | { |
bfca9459 | 165 | u32 addr = (u32)p; |
1da177e4 LT |
166 | u32 n, byte_enables, data; |
167 | ||
168 | if (addr >= VMALLOC_START) | |
169 | return __raw_readb(addr); | |
170 | ||
171 | n = addr % 4; | |
172 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
173 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
174 | return 0xff; | |
175 | ||
176 | return data >> (8*n); | |
177 | } | |
178 | ||
179 | static inline void | |
bfca9459 | 180 | __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) |
1da177e4 LT |
181 | { |
182 | while (count--) | |
183 | *vaddr++ = readb(bus_addr); | |
184 | } | |
185 | ||
186 | static inline unsigned short | |
bfca9459 | 187 | __ixp4xx_readw(const volatile void __iomem *p) |
1da177e4 | 188 | { |
bfca9459 | 189 | u32 addr = (u32)p; |
1da177e4 LT |
190 | u32 n, byte_enables, data; |
191 | ||
192 | if (addr >= VMALLOC_START) | |
193 | return __raw_readw(addr); | |
194 | ||
195 | n = addr % 4; | |
196 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
197 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | |
198 | return 0xffff; | |
199 | ||
200 | return data>>(8*n); | |
201 | } | |
202 | ||
203 | static inline void | |
bfca9459 | 204 | __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) |
1da177e4 LT |
205 | { |
206 | while (count--) | |
207 | *vaddr++ = readw(bus_addr); | |
208 | } | |
209 | ||
210 | static inline unsigned long | |
bfca9459 | 211 | __ixp4xx_readl(const volatile void __iomem *p) |
1da177e4 | 212 | { |
d2936b19 | 213 | u32 addr = (__force u32)p; |
1da177e4 LT |
214 | u32 data; |
215 | ||
216 | if (addr >= VMALLOC_START) | |
d2936b19 | 217 | return __raw_readl(p); |
1da177e4 LT |
218 | |
219 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) | |
220 | return 0xffffffff; | |
221 | ||
222 | return data; | |
223 | } | |
224 | ||
225 | static inline void | |
bfca9459 | 226 | __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) |
1da177e4 LT |
227 | { |
228 | while (count--) | |
229 | *vaddr++ = readl(bus_addr); | |
230 | } | |
231 | ||
232 | ||
233 | /* | |
234 | * We can use the built-in functions b/c they end up calling writeb/readb | |
235 | */ | |
236 | #define memset_io(c,v,l) _memset_io((c),(v),(l)) | |
237 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | |
238 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | |
239 | ||
1da177e4 LT |
240 | #endif |
241 | ||
76bbb002 DS |
242 | #ifndef CONFIG_PCI |
243 | ||
244 | #define __io(v) v | |
245 | ||
246 | #else | |
247 | ||
1da177e4 LT |
248 | /* |
249 | * IXP4xx does not have a transparent cpu -> PCI I/O translation | |
250 | * window. Instead, it has a set of registers that must be tweaked | |
251 | * with the proper byte lanes, command types, and address for the | |
252 | * transaction. This means that we need to override the default | |
253 | * I/O functions. | |
254 | */ | |
255 | #define outb(p, v) __ixp4xx_outb(p, v) | |
256 | #define outw(p, v) __ixp4xx_outw(p, v) | |
257 | #define outl(p, v) __ixp4xx_outl(p, v) | |
258 | ||
259 | #define outsb(p, v, l) __ixp4xx_outsb(p, v, l) | |
260 | #define outsw(p, v, l) __ixp4xx_outsw(p, v, l) | |
261 | #define outsl(p, v, l) __ixp4xx_outsl(p, v, l) | |
262 | ||
263 | #define inb(p) __ixp4xx_inb(p) | |
264 | #define inw(p) __ixp4xx_inw(p) | |
265 | #define inl(p) __ixp4xx_inl(p) | |
266 | ||
267 | #define insb(p, v, l) __ixp4xx_insb(p, v, l) | |
268 | #define insw(p, v, l) __ixp4xx_insw(p, v, l) | |
269 | #define insl(p, v, l) __ixp4xx_insl(p, v, l) | |
270 | ||
271 | ||
272 | static inline void | |
273 | __ixp4xx_outb(u8 value, u32 addr) | |
274 | { | |
275 | u32 n, byte_enables, data; | |
276 | n = addr % 4; | |
277 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
278 | data = value << (8*n); | |
279 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
280 | } | |
281 | ||
282 | static inline void | |
283 | __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) | |
284 | { | |
285 | while (count--) | |
286 | outb(*vaddr++, io_addr); | |
287 | } | |
288 | ||
289 | static inline void | |
290 | __ixp4xx_outw(u16 value, u32 addr) | |
291 | { | |
292 | u32 n, byte_enables, data; | |
293 | n = addr % 4; | |
294 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
295 | data = value << (8*n); | |
296 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | |
297 | } | |
298 | ||
299 | static inline void | |
300 | __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) | |
301 | { | |
302 | while (count--) | |
303 | outw(cpu_to_le16(*vaddr++), io_addr); | |
304 | } | |
305 | ||
306 | static inline void | |
307 | __ixp4xx_outl(u32 value, u32 addr) | |
308 | { | |
309 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); | |
310 | } | |
311 | ||
312 | static inline void | |
313 | __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) | |
314 | { | |
315 | while (count--) | |
316 | outl(*vaddr++, io_addr); | |
317 | } | |
318 | ||
319 | static inline u8 | |
320 | __ixp4xx_inb(u32 addr) | |
321 | { | |
322 | u32 n, byte_enables, data; | |
323 | n = addr % 4; | |
324 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | |
325 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
326 | return 0xff; | |
327 | ||
328 | return data >> (8*n); | |
329 | } | |
330 | ||
331 | static inline void | |
332 | __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) | |
333 | { | |
334 | while (count--) | |
335 | *vaddr++ = inb(io_addr); | |
336 | } | |
337 | ||
338 | static inline u16 | |
339 | __ixp4xx_inw(u32 addr) | |
340 | { | |
341 | u32 n, byte_enables, data; | |
342 | n = addr % 4; | |
343 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | |
344 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | |
345 | return 0xffff; | |
346 | ||
347 | return data>>(8*n); | |
348 | } | |
349 | ||
350 | static inline void | |
351 | __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) | |
352 | { | |
353 | while (count--) | |
354 | *vaddr++ = le16_to_cpu(inw(io_addr)); | |
355 | } | |
356 | ||
357 | static inline u32 | |
358 | __ixp4xx_inl(u32 addr) | |
359 | { | |
360 | u32 data; | |
361 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) | |
362 | return 0xffffffff; | |
363 | ||
364 | return data; | |
365 | } | |
366 | ||
367 | static inline void | |
368 | __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) | |
369 | { | |
370 | while (count--) | |
371 | *vaddr++ = inl(io_addr); | |
372 | } | |
373 | ||
147056fb DV |
374 | #define PIO_OFFSET 0x10000UL |
375 | #define PIO_MASK 0x0ffffUL | |
376 | ||
377 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | |
378 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | |
450008b5 | 379 | static inline unsigned int |
bfca9459 | 380 | __ixp4xx_ioread8(const void __iomem *addr) |
450008b5 | 381 | { |
147056fb | 382 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 383 | if (__is_io_address(port)) |
147056fb | 384 | return (unsigned int)__ixp4xx_inb(port & PIO_MASK); |
450008b5 DS |
385 | else |
386 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 387 | return (unsigned int)__raw_readb(port); |
450008b5 | 388 | #else |
bfca9459 | 389 | return (unsigned int)__ixp4xx_readb(addr); |
450008b5 DS |
390 | #endif |
391 | } | |
392 | ||
393 | static inline void | |
bfca9459 | 394 | __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) |
450008b5 | 395 | { |
147056fb | 396 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 397 | if (__is_io_address(port)) |
147056fb | 398 | __ixp4xx_insb(port & PIO_MASK, vaddr, count); |
450008b5 DS |
399 | else |
400 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 401 | __raw_readsb(addr, vaddr, count); |
450008b5 | 402 | #else |
bfca9459 | 403 | __ixp4xx_readsb(addr, vaddr, count); |
450008b5 DS |
404 | #endif |
405 | } | |
406 | ||
407 | static inline unsigned int | |
bfca9459 | 408 | __ixp4xx_ioread16(const void __iomem *addr) |
450008b5 | 409 | { |
147056fb | 410 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 411 | if (__is_io_address(port)) |
147056fb | 412 | return (unsigned int)__ixp4xx_inw(port & PIO_MASK); |
450008b5 DS |
413 | else |
414 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
415 | return le16_to_cpu(__raw_readw((u32)port)); | |
416 | #else | |
bfca9459 | 417 | return (unsigned int)__ixp4xx_readw(addr); |
450008b5 DS |
418 | #endif |
419 | } | |
420 | ||
421 | static inline void | |
bfca9459 | 422 | __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) |
450008b5 | 423 | { |
147056fb | 424 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 425 | if (__is_io_address(port)) |
147056fb | 426 | __ixp4xx_insw(port & PIO_MASK, vaddr, count); |
450008b5 DS |
427 | else |
428 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 429 | __raw_readsw(addr, vaddr, count); |
450008b5 | 430 | #else |
bfca9459 | 431 | __ixp4xx_readsw(addr, vaddr, count); |
450008b5 DS |
432 | #endif |
433 | } | |
434 | ||
435 | static inline unsigned int | |
bfca9459 | 436 | __ixp4xx_ioread32(const void __iomem *addr) |
450008b5 | 437 | { |
147056fb | 438 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 439 | if (__is_io_address(port)) |
147056fb | 440 | return (unsigned int)__ixp4xx_inl(port & PIO_MASK); |
450008b5 DS |
441 | else { |
442 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 443 | return le32_to_cpu((__force __le32)__raw_readl(addr)); |
450008b5 | 444 | #else |
bfca9459 | 445 | return (unsigned int)__ixp4xx_readl(addr); |
450008b5 DS |
446 | #endif |
447 | } | |
448 | } | |
449 | ||
450 | static inline void | |
bfca9459 | 451 | __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) |
450008b5 | 452 | { |
147056fb | 453 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 454 | if (__is_io_address(port)) |
147056fb | 455 | __ixp4xx_insl(port & PIO_MASK, vaddr, count); |
450008b5 DS |
456 | else |
457 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 458 | __raw_readsl(addr, vaddr, count); |
450008b5 | 459 | #else |
bfca9459 | 460 | __ixp4xx_readsl(addr, vaddr, count); |
450008b5 DS |
461 | #endif |
462 | } | |
463 | ||
464 | static inline void | |
147056fb | 465 | __ixp4xx_iowrite8(u8 value, void __iomem *addr) |
450008b5 | 466 | { |
147056fb | 467 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 468 | if (__is_io_address(port)) |
147056fb | 469 | __ixp4xx_outb(value, port & PIO_MASK); |
450008b5 DS |
470 | else |
471 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 472 | __raw_writeb(value, port); |
450008b5 | 473 | #else |
bfca9459 | 474 | __ixp4xx_writeb(value, addr); |
450008b5 DS |
475 | #endif |
476 | } | |
477 | ||
478 | static inline void | |
147056fb | 479 | __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) |
450008b5 | 480 | { |
147056fb | 481 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 482 | if (__is_io_address(port)) |
147056fb DV |
483 | __ixp4xx_outsb(port & PIO_MASK, vaddr, count); |
484 | else | |
450008b5 | 485 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 486 | __raw_writesb(addr, vaddr, count); |
450008b5 | 487 | #else |
bfca9459 | 488 | __ixp4xx_writesb(addr, vaddr, count); |
450008b5 DS |
489 | #endif |
490 | } | |
491 | ||
492 | static inline void | |
147056fb | 493 | __ixp4xx_iowrite16(u16 value, void __iomem *addr) |
450008b5 | 494 | { |
147056fb | 495 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 496 | if (__is_io_address(port)) |
147056fb | 497 | __ixp4xx_outw(value, port & PIO_MASK); |
450008b5 DS |
498 | else |
499 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
147056fb | 500 | __raw_writew(cpu_to_le16(value), addr); |
450008b5 | 501 | #else |
bfca9459 | 502 | __ixp4xx_writew(value, addr); |
450008b5 DS |
503 | #endif |
504 | } | |
505 | ||
506 | static inline void | |
147056fb | 507 | __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) |
450008b5 | 508 | { |
147056fb | 509 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 510 | if (__is_io_address(port)) |
147056fb DV |
511 | __ixp4xx_outsw(port & PIO_MASK, vaddr, count); |
512 | else | |
450008b5 | 513 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 514 | __raw_writesw(addr, vaddr, count); |
450008b5 | 515 | #else |
bfca9459 | 516 | __ixp4xx_writesw(addr, vaddr, count); |
450008b5 DS |
517 | #endif |
518 | } | |
519 | ||
520 | static inline void | |
147056fb | 521 | __ixp4xx_iowrite32(u32 value, void __iomem *addr) |
450008b5 | 522 | { |
147056fb | 523 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 524 | if (__is_io_address(port)) |
147056fb | 525 | __ixp4xx_outl(value, port & PIO_MASK); |
450008b5 DS |
526 | else |
527 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
d2936b19 | 528 | __raw_writel((u32 __force)cpu_to_le32(value), addr); |
450008b5 | 529 | #else |
bfca9459 | 530 | __ixp4xx_writel(value, addr); |
450008b5 DS |
531 | #endif |
532 | } | |
533 | ||
534 | static inline void | |
147056fb | 535 | __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) |
450008b5 | 536 | { |
147056fb | 537 | unsigned long port = (unsigned long __force)addr; |
450008b5 | 538 | if (__is_io_address(port)) |
147056fb DV |
539 | __ixp4xx_outsl(port & PIO_MASK, vaddr, count); |
540 | else | |
450008b5 | 541 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
147056fb | 542 | __raw_writesl(addr, vaddr, count); |
450008b5 | 543 | #else |
bfca9459 | 544 | __ixp4xx_writesl(addr, vaddr, count); |
450008b5 DS |
545 | #endif |
546 | } | |
547 | ||
548 | #define ioread8(p) __ixp4xx_ioread8(p) | |
549 | #define ioread16(p) __ixp4xx_ioread16(p) | |
550 | #define ioread32(p) __ixp4xx_ioread32(p) | |
551 | ||
552 | #define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) | |
553 | #define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) | |
554 | #define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) | |
555 | ||
556 | #define iowrite8(v,p) __ixp4xx_iowrite8(v,p) | |
557 | #define iowrite16(v,p) __ixp4xx_iowrite16(v,p) | |
558 | #define iowrite32(v,p) __ixp4xx_iowrite32(v,p) | |
559 | ||
560 | #define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) | |
561 | #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) | |
562 | #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) | |
563 | ||
147056fb | 564 | #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) |
450008b5 | 565 | #define ioport_unmap(addr) |
76bbb002 | 566 | #endif // !CONFIG_PCI |
1da177e4 LT |
567 | |
568 | #endif // __ASM_ARM_ARCH_IO_H | |
569 |