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1da177e4 LT |
1 | /* include/asm-arm/arch-lh7a40x/constants.h |
2 | * | |
3 | * Copyright (C) 2004 Coastal Environmental Systems | |
4 | * Copyright (C) 2004 Logic Product Development | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #ifndef __ASM_ARCH_CONSTANTS_H | |
13 | #define __ASM_ARCH_CONSTANTS_H | |
14 | ||
1da177e4 LT |
15 | |
16 | /* Addressing constants */ | |
17 | ||
18 | /* SoC CPU IO addressing */ | |
19 | #define IO_PHYS (0x80000000) | |
20 | #define IO_VIRT (0xf8000000) | |
21 | #define IO_SIZE (0x0000B000) | |
22 | ||
23 | #ifdef CONFIG_MACH_KEV7A400 | |
24 | # define CPLD_PHYS (0x20000000) | |
25 | # define CPLD_VIRT (0xf2000000) | |
26 | # define CPLD_SIZE PAGE_SIZE | |
27 | #endif | |
28 | ||
29 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | |
30 | ||
2295196c | 31 | # define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */ |
1da177e4 LT |
32 | # define IOBARRIER_VIRT 0xf0000000 |
33 | # define IOBARRIER_SIZE PAGE_SIZE | |
34 | ||
35 | # define CF_PHYS 0x60200000 | |
36 | # define CF_VIRT 0xf6020000 | |
37 | # define CF_SIZE (8*1024) | |
38 | ||
39 | /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */ | |
40 | # define CPLDX_PHYS(x) (0x70000000 | ((x) << 20)) | |
41 | # define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16)) | |
42 | # define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */ | |
43 | # define CPLD00_VIRT CPLDX_VIRT (0x00) | |
44 | # define CPLD00_SIZE PAGE_SIZE | |
45 | # define CPLD02_PHYS CPLDX_PHYS (0x02) | |
46 | # define CPLD02_VIRT CPLDX_VIRT (0x02) | |
47 | # define CPLD02_SIZE PAGE_SIZE | |
48 | # define CPLD06_PHYS CPLDX_PHYS (0x06) | |
49 | # define CPLD06_VIRT CPLDX_VIRT (0x06) | |
50 | # define CPLD06_SIZE PAGE_SIZE | |
51 | # define CPLD08_PHYS CPLDX_PHYS (0x08) | |
52 | # define CPLD08_VIRT CPLDX_VIRT (0x08) | |
53 | # define CPLD08_SIZE PAGE_SIZE | |
2295196c MS |
54 | # define CPLD0A_PHYS CPLDX_PHYS (0x0a) |
55 | # define CPLD0A_VIRT CPLDX_VIRT (0x0a) | |
56 | # define CPLD0A_SIZE PAGE_SIZE | |
1da177e4 LT |
57 | # define CPLD0C_PHYS CPLDX_PHYS (0x0c) |
58 | # define CPLD0C_VIRT CPLDX_VIRT (0x0c) | |
59 | # define CPLD0C_SIZE PAGE_SIZE | |
60 | # define CPLD0E_PHYS CPLDX_PHYS (0x0e) | |
61 | # define CPLD0E_VIRT CPLDX_VIRT (0x0e) | |
62 | # define CPLD0E_SIZE PAGE_SIZE | |
63 | # define CPLD10_PHYS CPLDX_PHYS (0x10) | |
64 | # define CPLD10_VIRT CPLDX_VIRT (0x10) | |
65 | # define CPLD10_SIZE PAGE_SIZE | |
66 | # define CPLD12_PHYS CPLDX_PHYS (0x12) | |
67 | # define CPLD12_VIRT CPLDX_VIRT (0x12) | |
68 | # define CPLD12_SIZE PAGE_SIZE | |
69 | # define CPLD14_PHYS CPLDX_PHYS (0x14) | |
70 | # define CPLD14_VIRT CPLDX_VIRT (0x14) | |
71 | # define CPLD14_SIZE PAGE_SIZE | |
72 | # define CPLD16_PHYS CPLDX_PHYS (0x16) | |
73 | # define CPLD16_VIRT CPLDX_VIRT (0x16) | |
74 | # define CPLD16_SIZE PAGE_SIZE | |
75 | # define CPLD18_PHYS CPLDX_PHYS (0x18) | |
76 | # define CPLD18_VIRT CPLDX_VIRT (0x18) | |
77 | # define CPLD18_SIZE PAGE_SIZE | |
78 | # define CPLD1A_PHYS CPLDX_PHYS (0x1a) | |
79 | # define CPLD1A_VIRT CPLDX_VIRT (0x1a) | |
80 | # define CPLD1A_SIZE PAGE_SIZE | |
81 | #endif | |
82 | ||
83 | /* Timing constants */ | |
84 | ||
85 | #define XTAL_IN 14745600 /* 14.7456 MHz crystal */ | |
86 | #define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ | |
87 | #define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ | |
2295196c MS |
88 | #define HCLK (99993600) |
89 | //#define HCLK (119808000) | |
1da177e4 LT |
90 | |
91 | #endif /* __ASM_ARCH_CONSTANTS_H */ |