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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/arch-rpc/hardware.h | |
3 | * | |
4 | * Copyright (C) 1996-1999 Russell King. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This file contains the hardware definitions of the RiscPC series machines. | |
11 | */ | |
12 | #ifndef __ASM_ARCH_HARDWARE_H | |
13 | #define __ASM_ARCH_HARDWARE_H | |
14 | ||
15 | #include <asm/arch/memory.h> | |
16 | ||
17 | #ifndef __ASSEMBLY__ | |
272cd2b7 | 18 | #define IOMEM(x) ((void __iomem *)(unsigned long)(x)) |
1da177e4 LT |
19 | #else |
20 | #define IOMEM(x) x | |
21 | #endif /* __ASSEMBLY__ */ | |
22 | ||
23 | /* | |
24 | * What hardware must be present | |
25 | */ | |
26 | #define HAS_IOMD | |
27 | #define HAS_VIDC20 | |
28 | ||
29 | /* Hardware addresses of major areas. | |
30 | * *_START is the physical address | |
31 | * *_SIZE is the size of the region | |
32 | * *_BASE is the virtual address | |
33 | */ | |
34 | #define RAM_SIZE 0x10000000 | |
35 | #define RAM_START 0x10000000 | |
36 | ||
37 | #define EASI_SIZE 0x08000000 /* EASI I/O */ | |
38 | #define EASI_START 0x08000000 | |
39 | #define EASI_BASE 0xe5000000 | |
40 | ||
41 | #define IO_START 0x03000000 /* I/O */ | |
42 | #define IO_SIZE 0x01000000 | |
43 | #define IO_BASE IOMEM(0xe0000000) | |
44 | ||
45 | #define SCREEN_START 0x02000000 /* VRAM */ | |
46 | #define SCREEN_END 0xdfc00000 | |
47 | #define SCREEN_BASE 0xdf800000 | |
48 | ||
1da177e4 LT |
49 | #define UNCACHEABLE_ADDR 0xdf010000 |
50 | ||
51 | /* | |
52 | * IO Addresses | |
53 | */ | |
272cd2b7 | 54 | #define VIDC_BASE IOMEM(0xe0400000) |
1da177e4 LT |
55 | #define EXPMASK_BASE 0xe0360000 |
56 | #define IOMD_BASE IOMEM(0xe0200000) | |
57 | #define IOC_BASE IOMEM(0xe0200000) | |
58 | #define PCIO_BASE IOMEM(0xe0010000) | |
59 | #define FLOPPYDMA_BASE IOMEM(0xe002a000) | |
60 | ||
1da177e4 LT |
61 | #define vidc_writel(val) __raw_writel(val, VIDC_BASE) |
62 | ||
63 | #define IO_EC_EASI_BASE 0x81400000 | |
64 | #define IO_EC_IOC4_BASE 0x8009c000 | |
65 | #define IO_EC_IOC_BASE 0x80090000 | |
66 | #define IO_EC_MEMC8_BASE 0x8000ac00 | |
67 | #define IO_EC_MEMC_BASE 0x80000000 | |
68 | ||
69 | #define NETSLOT_BASE 0x0302b000 | |
70 | #define NETSLOT_SIZE 0x00001000 | |
71 | ||
72 | #define PODSLOT_IOC0_BASE 0x03240000 | |
73 | #define PODSLOT_IOC4_BASE 0x03270000 | |
74 | #define PODSLOT_IOC_SIZE (1 << 14) | |
75 | #define PODSLOT_MEMC_BASE 0x03000000 | |
76 | #define PODSLOT_MEMC_SIZE (1 << 14) | |
77 | #define PODSLOT_EASI_BASE 0x08000000 | |
78 | #define PODSLOT_EASI_SIZE (1 << 24) | |
79 | ||
80 | #define EXPMASK_STATUS (EXPMASK_BASE + 0x00) | |
81 | #define EXPMASK_ENABLE (EXPMASK_BASE + 0x04) | |
82 | ||
83 | #endif |