[mirror_ubuntu-jammy-kernel.git] / include / asm-arm / arch-s3c2410 / dma.h

/* linux/include/asm-arm/arch-bast/dma.h
 *
 * Copyright (C) 2003,2004 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C2410X DMA support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Changelog:
 *  ??-May-2003 BJD   Created file
 *  ??-Jun-2003 BJD   Added more dma functionality to go with arch
 *  10-Nov-2004 BJD   Added sys_device support
*/

#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__

#include <linux/sysdev.h>
#include "hardware.h"


/*
 * This is the maximum DMA address(physical address) that can be DMAd to.
 *
 */
#define MAX_DMA_ADDRESS		0x20000000
#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */


/* we have 4 dma channels */
#define S3C2410_DMA_CHANNELS        (4)

/* types */

enum s3c2410_dma_state {
	S3C2410_DMA_IDLE,
	S3C2410_DMA_RUNNING,
	S3C2410_DMA_PAUSED
};


/* enum s3c2410_dma_loadst
 *
 * This represents the state of the DMA engine, wrt to the loaded / running
 * transfers. Since we don't have any way of knowing exactly the state of
 * the DMA transfers, we need to know the state to make decisions on wether
 * we can
 *
 * S3C2410_DMA_NONE
 *
 * There are no buffers loaded (the channel should be inactive)
 *
 * S3C2410_DMA_1LOADED
 *
 * There is one buffer loaded, however it has not been confirmed to be
 * loaded by the DMA engine. This may be because the channel is not
 * yet running, or the DMA driver decided that it was too costly to
 * sit and wait for it to happen.
 *
 * S3C2410_DMA_1RUNNING
 *
 * The buffer has been confirmed running, and not finisged
 *
 * S3C2410_DMA_1LOADED_1RUNNING
 *
 * There is a buffer waiting to be loaded by the DMA engine, and one
 * currently running.
*/

enum s3c2410_dma_loadst {
	S3C2410_DMALOAD_NONE,
	S3C2410_DMALOAD_1LOADED,
	S3C2410_DMALOAD_1RUNNING,
	S3C2410_DMALOAD_1LOADED_1RUNNING,
};

enum s3c2410_dma_buffresult {
	S3C2410_RES_OK,
	S3C2410_RES_ERR,
	S3C2410_RES_ABORT
};


enum s3c2410_dmasrc {
	S3C2410_DMASRC_HW,      /* source is memory */
	S3C2410_DMASRC_MEM      /* source is hardware */
};

/* enum s3c2410_chan_op
 *
 * operation codes passed to the DMA code by the user, and also used
 * to inform the current channel owner of any changes to the system state
*/

enum s3c2410_chan_op {
	S3C2410_DMAOP_START,
	S3C2410_DMAOP_STOP,
	S3C2410_DMAOP_PAUSE,
	S3C2410_DMAOP_RESUME,
	S3C2410_DMAOP_FLUSH,
	S3C2410_DMAOP_TIMEOUT,           /* internal signal to handler */
	S3C2410_DMAOP_STARTED,		/* indicate channel started */
};

/* flags */

#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
					    * waiting for reloads */
#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */

/* dma buffer */

struct s3c2410_dma_client {
	char                *name;
};

/* s3c2410_dma_buf_s
 *
 * internally used buffer structure to describe a queued or running
 * buffer.
*/

struct s3c2410_dma_buf;
struct s3c2410_dma_buf {
	struct s3c2410_dma_buf   *next;
	int                  magic;        /* magic */
	int                  size;         /* buffer size in bytes */
	dma_addr_t           data;         /* start of DMA data */
	dma_addr_t           ptr;          /* where the DMA got to [1] */
	void                *id;           /* client's id */
};

/* [1] is this updated for both recv/send modes? */

struct s3c2410_dma_chan;

/* s3c2410_dma_cbfn_t
 *
 * buffer callback routine type
*/

typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
				   void *buf, int size,
				   enum s3c2410_dma_buffresult result);

typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
				   enum s3c2410_chan_op );

struct s3c2410_dma_stats {
	unsigned long          loads;
	unsigned long          timeout_longest;
	unsigned long          timeout_shortest;
	unsigned long          timeout_avg;
	unsigned long          timeout_failed;
};

/* struct s3c2410_dma_chan
 *
 * full state information for each DMA channel
*/

struct s3c2410_dma_chan {
	/* channel state flags and information */
	unsigned char          number;      /* number of this dma channel */
	unsigned char          in_use;      /* channel allocated */
	unsigned char          irq_claimed; /* irq claimed for channel */
	unsigned char          irq_enabled; /* irq enabled for channel */
	unsigned char          xfer_unit;   /* size of an transfer */

	/* channel state */

	enum s3c2410_dma_state    state;
	enum s3c2410_dma_loadst   load_state;
	struct s3c2410_dma_client  *client;

	/* channel configuration */
	enum s3c2410_dmasrc       source;
	unsigned long          dev_addr;
	unsigned long          load_timeout;
	unsigned int           flags;        /* channel flags */

	/* channel's hardware position and configuration */
	void __iomem           *regs;        /* channels registers */
	void __iomem           *addr_reg;    /* data address register */
	unsigned int           irq;          /* channel irq */
	unsigned long          dcon;         /* default value of DCON */

	/* driver handles */
	s3c2410_dma_cbfn_t     callback_fn;  /* buffer done callback */
	s3c2410_dma_opfn_t     op_fn;        /* channel operation callback */

	/* stats gathering */
	struct s3c2410_dma_stats   *stats;
	struct s3c2410_dma_stats    stats_store;

	/* buffer list and information */
	struct s3c2410_dma_buf      *curr;        /* current dma buffer */
	struct s3c2410_dma_buf      *next;        /* next buffer to load */
	struct s3c2410_dma_buf      *end;         /* end of queue */

	/* system device */
	struct sys_device	dev;
};

/* the currently allocated channel information */
extern struct s3c2410_dma_chan s3c2410_chans[];

/* note, we don't really use dma_device_t at the moment */
typedef unsigned long dma_device_t;

/* functions --------------------------------------------------------------- */

/* s3c2410_dma_request
 *
 * request a dma channel exclusivley
*/

extern int s3c2410_dma_request(dmach_t channel,
			       struct s3c2410_dma_client *, void *dev);


/* s3c2410_dma_ctrl
 *
 * change the state of the dma channel
*/

extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);

/* s3c2410_dma_setflags
 *
 * set the channel's flags to a given state
*/

extern int s3c2410_dma_setflags(dmach_t channel,
				unsigned int flags);

/* s3c2410_dma_free
 *
 * free the dma channel (will also abort any outstanding operations)
*/

extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);

/* s3c2410_dma_enqueue
 *
 * place the given buffer onto the queue of operations for the channel.
 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 * drained before the buffer is given to the DMA system.
*/

extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
			       dma_addr_t data, int size);

/* s3c2410_dma_config
 *
 * configure the dma channel
*/

extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);

/* s3c2410_dma_devconfig
 *
 * configure the device we're talking to
*/

extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
				 int hwcfg, unsigned long devaddr);

/* s3c2410_dma_getposition
 *
 * get the position that the dma transfer is currently at
*/

extern int s3c2410_dma_getposition(dmach_t channel,
				   dma_addr_t *src, dma_addr_t *dest);

extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);

/* DMA Register definitions */

#define S3C2410_DMA_DISRC       (0x00)
#define S3C2410_DMA_DISRCC      (0x04)
#define S3C2410_DMA_DIDST       (0x08)
#define S3C2410_DMA_DIDSTC      (0x0C)
#define S3C2410_DMA_DCON        (0x10)
#define S3C2410_DMA_DSTAT       (0x14)
#define S3C2410_DMA_DCSRC       (0x18)
#define S3C2410_DMA_DCDST       (0x1C)
#define S3C2410_DMA_DMASKTRIG   (0x20)

#define S3C2410_DISRCC_INC	(1<<0)
#define S3C2410_DISRCC_APB	(1<<1)

#define S3C2410_DMASKTRIG_STOP   (1<<2)
#define S3C2410_DMASKTRIG_ON     (1<<1)
#define S3C2410_DMASKTRIG_SWTRIG (1<<0)

#define S3C2410_DCON_DEMAND     (0<<31)
#define S3C2410_DCON_HANDSHAKE  (1<<31)
#define S3C2410_DCON_SYNC_PCLK  (0<<30)
#define S3C2410_DCON_SYNC_HCLK  (1<<30)

#define S3C2410_DCON_INTREQ     (1<<29)

#define S3C2410_DCON_CH0_XDREQ0	(0<<24)
#define S3C2410_DCON_CH0_UART0	(1<<24)
#define S3C2410_DCON_CH0_SDI	(2<<24)
#define S3C2410_DCON_CH0_TIMER	(3<<24)
#define S3C2410_DCON_CH0_USBEP1	(4<<24)

#define S3C2410_DCON_CH1_XDREQ1	(0<<24)
#define S3C2410_DCON_CH1_UART1	(1<<24)
#define S3C2410_DCON_CH1_I2SSDI	(2<<24)
#define S3C2410_DCON_CH1_SPI	(3<<24)
#define S3C2410_DCON_CH1_USBEP2	(4<<24)

#define S3C2410_DCON_CH2_I2SSDO	(0<<24)
#define S3C2410_DCON_CH2_I2SSDI	(1<<24)
#define S3C2410_DCON_CH2_SDI	(2<<24)
#define S3C2410_DCON_CH2_TIMER	(3<<24)
#define S3C2410_DCON_CH2_USBEP3	(4<<24)

#define S3C2410_DCON_CH3_UART2	(0<<24)
#define S3C2410_DCON_CH3_SDI	(1<<24)
#define S3C2410_DCON_CH3_SPI	(2<<24)
#define S3C2410_DCON_CH3_TIMER	(3<<24)
#define S3C2410_DCON_CH3_USBEP4	(4<<24)

#define S3C2410_DCON_SRCSHIFT   (24)
#define S3C2410_DCON_SRCMASK	(7<<24)

#define S3C2410_DCON_BYTE       (0<<20)
#define S3C2410_DCON_HALFWORD   (1<<20)
#define S3C2410_DCON_WORD       (2<<20)

#define S3C2410_DCON_AUTORELOAD (0<<22)
#define S3C2410_DCON_NORELOAD   (1<<22)
#define S3C2410_DCON_HWTRIG     (1<<23)

#ifdef CONFIG_CPU_S3C2440
#define S3C2440_DIDSTC_CHKINT	(1<<2)

#define S3C2440_DCON_CH0_I2SSDO	(5<<24)
#define S3C2440_DCON_CH0_PCMIN	(6<<24)

#define S3C2440_DCON_CH1_PCMOUT	(5<<24)
#define S3C2440_DCON_CH1_SDI	(6<<24)

#define S3C2440_DCON_CH2_PCMIN	(5<<24)
#define S3C2440_DCON_CH2_MICIN	(6<<24)

#define S3C2440_DCON_CH3_MICIN	(5<<24)
#define S3C2440_DCON_CH3_PCMOUT	(6<<24)
#endif

#endif /* __ASM_ARCH_DMA_H */
Commit	Line	Data
1da177e4 LT	1	/* linux/include/asm-arm/arch-bast/dma.h
	2	*
	3	* Copyright (C) 2003,2004 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* Samsung S3C2410X DMA support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* Changelog:
	13	* ??-May-2003 BJD Created file
	14	* ??-Jun-2003 BJD Added more dma functionality to go with arch
	15	* 10-Nov-2004 BJD Added sys_device support
	16	*/
	17
	18	#ifndef __ASM_ARCH_DMA_H
	19	#define __ASM_ARCH_DMA_H __FILE__
	20
1da177e4 LT	21	#include <linux/sysdev.h>
	22	#include "hardware.h"
	23
	24
	25	/*
	26	* This is the maximum DMA address(physical address) that can be DMAd to.
	27	*
	28	*/
	29	#define MAX_DMA_ADDRESS 0x20000000
	30	#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
	31
	32
1da177e4 LT	33	/* we have 4 dma channels */
	34	#define S3C2410_DMA_CHANNELS (4)
	35
	36	/* types */
	37
f105a7df	38	enum s3c2410_dma_state {
1da177e4 LT	39	S3C2410_DMA_IDLE,
	40	S3C2410_DMA_RUNNING,
	41	S3C2410_DMA_PAUSED
f105a7df	42	};
1da177e4 LT	43
1da177e4 LT	44
f105a7df	45	/* enum s3c2410_dma_loadst
1da177e4 LT	46	*
	47	* This represents the state of the DMA engine, wrt to the loaded / running
	48	* transfers. Since we don't have any way of knowing exactly the state of
	49	* the DMA transfers, we need to know the state to make decisions on wether
	50	* we can
	51	*
	52	* S3C2410_DMA_NONE
	53	*
	54	* There are no buffers loaded (the channel should be inactive)
	55	*
	56	* S3C2410_DMA_1LOADED
	57	*
	58	* There is one buffer loaded, however it has not been confirmed to be
	59	* loaded by the DMA engine. This may be because the channel is not
	60	* yet running, or the DMA driver decided that it was too costly to
	61	* sit and wait for it to happen.
	62	*
	63	* S3C2410_DMA_1RUNNING
	64	*
	65	* The buffer has been confirmed running, and not finisged
	66	*
	67	* S3C2410_DMA_1LOADED_1RUNNING
	68	*
	69	* There is a buffer waiting to be loaded by the DMA engine, and one
	70	* currently running.
	71	*/
	72
f105a7df	73	enum s3c2410_dma_loadst {
1da177e4 LT	74	S3C2410_DMALOAD_NONE,
	75	S3C2410_DMALOAD_1LOADED,
	76	S3C2410_DMALOAD_1RUNNING,
	77	S3C2410_DMALOAD_1LOADED_1RUNNING,
f105a7df	78	};
1da177e4	79
f105a7df	80	enum s3c2410_dma_buffresult {
1da177e4 LT	81	S3C2410_RES_OK,
	82	S3C2410_RES_ERR,
	83	S3C2410_RES_ABORT
f105a7df	84	};
1da177e4	85
1da177e4	86
f105a7df	87	enum s3c2410_dmasrc {
1da177e4 LT	88	S3C2410_DMASRC_HW, /* source is memory */
	89	S3C2410_DMASRC_MEM /* source is hardware */
	90	};
	91
f105a7df	92	/* enum s3c2410_chan_op
1da177e4 LT	93	*
	94	* operation codes passed to the DMA code by the user, and also used
	95	* to inform the current channel owner of any changes to the system state
	96	*/
	97
f105a7df	98	enum s3c2410_chan_op {
1da177e4 LT	99	S3C2410_DMAOP_START,
	100	S3C2410_DMAOP_STOP,
	101	S3C2410_DMAOP_PAUSE,
	102	S3C2410_DMAOP_RESUME,
	103	S3C2410_DMAOP_FLUSH,
	104	S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
f57e1abd	105	S3C2410_DMAOP_STARTED, /* indicate channel started */
1da177e4 LT	106	};
1da177e4 LT	107
1da177e4 LT	108	/* flags */
	109
	110	#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
	111	* waiting for reloads */
	112	#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
	113
	114	/* dma buffer */
	115
1da177e4 LT	116	struct s3c2410_dma_client {
	117	char *name;
	118	};
	119
1da177e4 LT	120	/* s3c2410_dma_buf_s
	121	*
	122	* internally used buffer structure to describe a queued or running
	123	* buffer.
	124	*/
	125
f105a7df BD	126	struct s3c2410_dma_buf;
	127	struct s3c2410_dma_buf {
	128	struct s3c2410_dma_buf *next;
1da177e4 LT	129	int magic; /* magic */
	130	int size; /* buffer size in bytes */
	131	dma_addr_t data; /* start of DMA data */
	132	dma_addr_t ptr; /* where the DMA got to [1] */
	133	void id; / client's id */
	134	};
	135
	136	/* [1] is this updated for both recv/send modes? */
	137
f105a7df	138	struct s3c2410_dma_chan;
1da177e4 LT	139
	140	/* s3c2410_dma_cbfn_t
	141	*
	142	* buffer callback routine type
	143	*/
	144
f105a7df BD	145	typedef void (s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan ,
	146	void *buf, int size,
	147	enum s3c2410_dma_buffresult result);
1da177e4	148
f105a7df BD	149	typedef int (s3c2410_dma_opfn_t)(struct s3c2410_dma_chan ,
f105a7df BD	150	enum s3c2410_chan_op );
1da177e4	151
f105a7df	152	struct s3c2410_dma_stats {
1da177e4 LT	153	unsigned long loads;
	154	unsigned long timeout_longest;
	155	unsigned long timeout_shortest;
	156	unsigned long timeout_avg;
	157	unsigned long timeout_failed;
	158	};
	159
f105a7df	160	/* struct s3c2410_dma_chan
1da177e4 LT	161	*
	162	* full state information for each DMA channel
	163	*/
	164
f105a7df	165	struct s3c2410_dma_chan {
1da177e4 LT	166	/* channel state flags and information */
	167	unsigned char number; /* number of this dma channel */
	168	unsigned char in_use; /* channel allocated */
	169	unsigned char irq_claimed; /* irq claimed for channel */
	170	unsigned char irq_enabled; /* irq enabled for channel */
	171	unsigned char xfer_unit; /* size of an transfer */
	172
	173	/* channel state */
	174
f105a7df BD	175	enum s3c2410_dma_state state;
	176	enum s3c2410_dma_loadst load_state;
	177	struct s3c2410_dma_client *client;
1da177e4 LT	178
1da177e4 LT	179	/* channel configuration */
f105a7df	180	enum s3c2410_dmasrc source;
1da177e4 LT	181	unsigned long dev_addr;
	182	unsigned long load_timeout;
	183	unsigned int flags; /* channel flags */
	184
	185	/* channel's hardware position and configuration */
	186	void __iomem regs; / channels registers */
	187	void __iomem addr_reg; / data address register */
	188	unsigned int irq; /* channel irq */
	189	unsigned long dcon; /* default value of DCON */
	190
	191	/* driver handles */
	192	s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
	193	s3c2410_dma_opfn_t op_fn; /* channel operation callback */
	194
	195	/* stats gathering */
f105a7df BD	196	struct s3c2410_dma_stats *stats;
f105a7df BD	197	struct s3c2410_dma_stats stats_store;
1da177e4 LT	198
1da177e4 LT	199	/* buffer list and information */
f105a7df BD	200	struct s3c2410_dma_buf curr; / current dma buffer */
	201	struct s3c2410_dma_buf next; / next buffer to load */
	202	struct s3c2410_dma_buf end; / end of queue */
1da177e4 LT	203
	204	/* system device */
	205	struct sys_device dev;
	206	};
	207
	208	/* the currently allocated channel information */
f105a7df	209	extern struct s3c2410_dma_chan s3c2410_chans[];
1da177e4 LT	210
	211	/* note, we don't really use dma_device_t at the moment */
	212	typedef unsigned long dma_device_t;
	213
	214	/* functions --------------------------------------------------------------- */
	215
	216	/* s3c2410_dma_request
	217	*
	218	* request a dma channel exclusivley
	219	*/
	220
	221	extern int s3c2410_dma_request(dmach_t channel,
f105a7df	222	struct s3c2410_dma_client , void dev);
1da177e4 LT	223
	224
	225	/* s3c2410_dma_ctrl
	226	*
	227	* change the state of the dma channel
	228	*/
	229
f105a7df	230	extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
1da177e4 LT	231
	232	/* s3c2410_dma_setflags
	233	*
	234	* set the channel's flags to a given state
	235	*/
	236
	237	extern int s3c2410_dma_setflags(dmach_t channel,
	238	unsigned int flags);
	239
	240	/* s3c2410_dma_free
	241	*
	242	* free the dma channel (will also abort any outstanding operations)
	243	*/
	244
f105a7df	245	extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
1da177e4 LT	246
	247	/* s3c2410_dma_enqueue
	248	*
	249	* place the given buffer onto the queue of operations for the channel.
	250	* The buffer must be allocated from dma coherent memory, or the Dcache/WB
	251	* drained before the buffer is given to the DMA system.
	252	*/
	253
	254	extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
	255	dma_addr_t data, int size);
	256
	257	/* s3c2410_dma_config
	258	*
	259	* configure the dma channel
	260	*/
	261
	262	extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
	263
	264	/* s3c2410_dma_devconfig
	265	*
	266	* configure the device we're talking to
	267	*/
	268
f105a7df	269	extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
1da177e4 LT	270	int hwcfg, unsigned long devaddr);
	271
	272	/* s3c2410_dma_getposition
	273	*
	274	* get the position that the dma transfer is currently at
	275	*/
	276
	277	extern int s3c2410_dma_getposition(dmach_t channel,
	278	dma_addr_t src, dma_addr_t dest);
	279
	280	extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
	281	extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
	282
	283	/* DMA Register definitions */
	284
	285	#define S3C2410_DMA_DISRC (0x00)
	286	#define S3C2410_DMA_DISRCC (0x04)
	287	#define S3C2410_DMA_DIDST (0x08)
	288	#define S3C2410_DMA_DIDSTC (0x0C)
	289	#define S3C2410_DMA_DCON (0x10)
	290	#define S3C2410_DMA_DSTAT (0x14)
	291	#define S3C2410_DMA_DCSRC (0x18)
	292	#define S3C2410_DMA_DCDST (0x1C)
	293	#define S3C2410_DMA_DMASKTRIG (0x20)
	294
	295	#define S3C2410_DISRCC_INC (1<<0)
	296	#define S3C2410_DISRCC_APB (1<<1)
	297
	298	#define S3C2410_DMASKTRIG_STOP (1<<2)
	299	#define S3C2410_DMASKTRIG_ON (1<<1)
	300	#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
	301
	302	#define S3C2410_DCON_DEMAND (0<<31)
	303	#define S3C2410_DCON_HANDSHAKE (1<<31)
	304	#define S3C2410_DCON_SYNC_PCLK (0<<30)
	305	#define S3C2410_DCON_SYNC_HCLK (1<<30)
	306
	307	#define S3C2410_DCON_INTREQ (1<<29)
	308
	309	#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
	310	#define S3C2410_DCON_CH0_UART0 (1<<24)
	311	#define S3C2410_DCON_CH0_SDI (2<<24)
	312	#define S3C2410_DCON_CH0_TIMER (3<<24)
	313	#define S3C2410_DCON_CH0_USBEP1 (4<<24)
	314
	315	#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
	316	#define S3C2410_DCON_CH1_UART1 (1<<24)
	317	#define S3C2410_DCON_CH1_I2SSDI (2<<24)
	318	#define S3C2410_DCON_CH1_SPI (3<<24)
	319	#define S3C2410_DCON_CH1_USBEP2 (4<<24)
	320
	321	#define S3C2410_DCON_CH2_I2SSDO (0<<24)
	322	#define S3C2410_DCON_CH2_I2SSDI (1<<24)
	323	#define S3C2410_DCON_CH2_SDI (2<<24)
	324	#define S3C2410_DCON_CH2_TIMER (3<<24)
	325	#define S3C2410_DCON_CH2_USBEP3 (4<<24)
	326
	327	#define S3C2410_DCON_CH3_UART2 (0<<24)
	328	#define S3C2410_DCON_CH3_SDI (1<<24)
	329	#define S3C2410_DCON_CH3_SPI (2<<24)
	330	#define S3C2410_DCON_CH3_TIMER (3<<24)
	331	#define S3C2410_DCON_CH3_USBEP4 (4<<24)
	332
	333	#define S3C2410_DCON_SRCSHIFT (24)
334	#define S3C2410_DCON_SRCMASK (7<<24)
335
336	#define S3C2410_DCON_BYTE (0<<20)
337	#define S3C2410_DCON_HALFWORD (1<<20)
338	#define S3C2410_DCON_WORD (2<<20)
339
340	#define S3C2410_DCON_AUTORELOAD (0<<22)
341	#define S3C2410_DCON_NORELOAD (1<<22)
342	#define S3C2410_DCON_HWTRIG (1<<23)
343
344	#ifdef CONFIG_CPU_S3C2440
345	#define S3C2440_DIDSTC_CHKINT (1<<2)
346
347	#define S3C2440_DCON_CH0_I2SSDO (5<<24)
348	#define S3C2440_DCON_CH0_PCMIN (6<<24)
349
350	#define S3C2440_DCON_CH1_PCMOUT (5<<24)
351	#define S3C2440_DCON_CH1_SDI (6<<24)
352
353	#define S3C2440_DCON_CH2_PCMIN (5<<24)
354	#define S3C2440_DCON_CH2_MICIN (6<<24)
355
356	#define S3C2440_DCON_CH3_MICIN (5<<24)
357	#define S3C2440_DCON_CH3_PCMOUT (6<<24)
358	#endif
359
360	#endif /* __ASM_ARCH_DMA_H */