[mirror_ubuntu-zesty-kernel.git] / include / asm-arm / arch-s3c2410 / regs-mem.h

/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
 *
 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
 *		http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * S3C2410 Memory Control register definitions
*/

#ifndef __ASM_ARM_MEMREGS_H
#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"

#ifndef S3C2410_MEMREG
#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#endif

/* bus width, and wait state control */
#define S3C2410_BWSCON			S3C2410_MEMREG(0x0000)

/* bank zero config - note, pinstrapped from OM pins! */
#define S3C2410_BWSCON_DW0_16		(1<<1)
#define S3C2410_BWSCON_DW0_32		(2<<1)

/* bank one configs */
#define S3C2410_BWSCON_DW1_8		(0<<4)
#define S3C2410_BWSCON_DW1_16		(1<<4)
#define S3C2410_BWSCON_DW1_32		(2<<4)
#define S3C2410_BWSCON_WS1		(1<<6)
#define S3C2410_BWSCON_ST1		(1<<7)

/* bank 2 configurations */
#define S3C2410_BWSCON_DW2_8		(0<<8)
#define S3C2410_BWSCON_DW2_16		(1<<8)
#define S3C2410_BWSCON_DW2_32		(2<<8)
#define S3C2410_BWSCON_WS2		(1<<10)
#define S3C2410_BWSCON_ST2		(1<<11)

/* bank 3 configurations */
#define S3C2410_BWSCON_DW3_8		(0<<12)
#define S3C2410_BWSCON_DW3_16		(1<<12)
#define S3C2410_BWSCON_DW3_32		(2<<12)
#define S3C2410_BWSCON_WS3		(1<<14)
#define S3C2410_BWSCON_ST3		(1<<15)

/* bank 4 configurations */
#define S3C2410_BWSCON_DW4_8		(0<<16)
#define S3C2410_BWSCON_DW4_16		(1<<16)
#define S3C2410_BWSCON_DW4_32		(2<<16)
#define S3C2410_BWSCON_WS4		(1<<18)
#define S3C2410_BWSCON_ST4		(1<<19)

/* bank 5 configurations */
#define S3C2410_BWSCON_DW5_8		(0<<20)
#define S3C2410_BWSCON_DW5_16		(1<<20)
#define S3C2410_BWSCON_DW5_32		(2<<20)
#define S3C2410_BWSCON_WS5		(1<<22)
#define S3C2410_BWSCON_ST5		(1<<23)

/* bank 6 configurations */
#define S3C2410_BWSCON_DW6_8		(0<<24)
#define S3C2410_BWSCON_DW6_16		(1<<24)
#define S3C2410_BWSCON_DW6_32		(2<<24)
#define S3C2410_BWSCON_WS6		(1<<26)
#define S3C2410_BWSCON_ST6		(1<<27)

/* bank 7 configurations */
#define S3C2410_BWSCON_DW7_8		(0<<28)
#define S3C2410_BWSCON_DW7_16		(1<<28)
#define S3C2410_BWSCON_DW7_32		(2<<28)
#define S3C2410_BWSCON_WS7		(1<<30)
#define S3C2410_BWSCON_ST7		(1<<31)

/* memory set (rom, ram) */
#define S3C2410_BANKCON0		S3C2410_MEMREG(0x0004)
#define S3C2410_BANKCON1		S3C2410_MEMREG(0x0008)
#define S3C2410_BANKCON2		S3C2410_MEMREG(0x000C)
#define S3C2410_BANKCON3		S3C2410_MEMREG(0x0010)
#define S3C2410_BANKCON4		S3C2410_MEMREG(0x0014)
#define S3C2410_BANKCON5		S3C2410_MEMREG(0x0018)
#define S3C2410_BANKCON6		S3C2410_MEMREG(0x001C)
#define S3C2410_BANKCON7		S3C2410_MEMREG(0x0020)

/* bank configuration registers */

#define S3C2410_BANKCON_PMCnorm		(0x00)
#define S3C2410_BANKCON_PMC4		(0x01)
#define S3C2410_BANKCON_PMC8		(0x02)
#define S3C2410_BANKCON_PMC16		(0x03)

/* bank configurations for banks 0..7, note banks
 * 6 and 7 have differnt configurations depending on
 * the memory type bits */

#define S3C2410_BANKCON_Tacp2		(0x0 << 2)
#define S3C2410_BANKCON_Tacp3		(0x1 << 2)
#define S3C2410_BANKCON_Tacp4		(0x2 << 2)
#define S3C2410_BANKCON_Tacp6		(0x3 << 2)
#define S3C2410_BANKCON_Tacp_SHIFT	(2)

#define S3C2410_BANKCON_Tcah0		(0x0 << 4)
#define S3C2410_BANKCON_Tcah1		(0x1 << 4)
#define S3C2410_BANKCON_Tcah2		(0x2 << 4)
#define S3C2410_BANKCON_Tcah4		(0x3 << 4)
#define S3C2410_BANKCON_Tcah_SHIFT	(4)

#define S3C2410_BANKCON_Tcoh0		(0x0 << 6)
#define S3C2410_BANKCON_Tcoh1		(0x1 << 6)
#define S3C2410_BANKCON_Tcoh2		(0x2 << 6)
#define S3C2410_BANKCON_Tcoh4		(0x3 << 6)
#define S3C2410_BANKCON_Tcoh_SHIFT	(6)

#define S3C2410_BANKCON_Tacc1		(0x0 << 8)
#define S3C2410_BANKCON_Tacc2		(0x1 << 8)
#define S3C2410_BANKCON_Tacc3		(0x2 << 8)
#define S3C2410_BANKCON_Tacc4		(0x3 << 8)
#define S3C2410_BANKCON_Tacc6		(0x4 << 8)
#define S3C2410_BANKCON_Tacc8		(0x5 << 8)
#define S3C2410_BANKCON_Tacc10		(0x6 << 8)
#define S3C2410_BANKCON_Tacc14		(0x7 << 8)
#define S3C2410_BANKCON_Tacc_SHIFT	(8)

#define S3C2410_BANKCON_Tcos0		(0x0 << 11)
#define S3C2410_BANKCON_Tcos1		(0x1 << 11)
#define S3C2410_BANKCON_Tcos2		(0x2 << 11)
#define S3C2410_BANKCON_Tcos4		(0x3 << 11)
#define S3C2410_BANKCON_Tcos_SHIFT	(11)

#define S3C2410_BANKCON_Tacs0		(0x0 << 13)
#define S3C2410_BANKCON_Tacs1		(0x1 << 13)
#define S3C2410_BANKCON_Tacs2		(0x2 << 13)
#define S3C2410_BANKCON_Tacs4		(0x3 << 13)
#define S3C2410_BANKCON_Tacs_SHIFT	(13)

#define S3C2410_BANKCON_SRAM		(0x0 << 15)
#define S3C2400_BANKCON_EDODRAM		(0x2 << 15)
#define S3C2410_BANKCON_SDRAM		(0x3 << 15)

/* next bits only for EDO DRAM in 6,7 */
#define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
#define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
#define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
#define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)

/* CAS pulse width */
#define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
#define S3C2400_BANKCON_EDO_PULSE2     (0x01 << 3)

/* CAS pre-charge */
#define S3C2400_BANKCON_EDO_TCP1       (0x00 << 2)
#define S3C2400_BANKCON_EDO_TCP2       (0x01 << 2)

/* control column address select */
#define S3C2400_BANKCON_EDO_SCANb8     (0x00 << 0)
#define S3C2400_BANKCON_EDO_SCANb9     (0x01 << 0)
#define S3C2400_BANKCON_EDO_SCANb10    (0x02 << 0)
#define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)

/* next bits only for SDRAM in 6,7 */
#define S3C2410_BANKCON_Trcd2		(0x00 << 2)
#define S3C2410_BANKCON_Trcd3		(0x01 << 2)
#define S3C2410_BANKCON_Trcd4		(0x02 << 2)

/* control column address select */
#define S3C2410_BANKCON_SCANb8		(0x00 << 0)
#define S3C2410_BANKCON_SCANb9		(0x01 << 0)
#define S3C2410_BANKCON_SCANb10		(0x02 << 0)

#define S3C2410_REFRESH			S3C2410_MEMREG(0x0024)
#define S3C2410_BANKSIZE		S3C2410_MEMREG(0x0028)
#define S3C2410_MRSRB6			S3C2410_MEMREG(0x002C)
#define S3C2410_MRSRB7			S3C2410_MEMREG(0x0030)

/* refresh control */

#define S3C2410_REFRESH_REFEN		(1<<23)
#define S3C2410_REFRESH_SELF		(1<<22)
#define S3C2410_REFRESH_REFCOUNTER	((1<<11)-1)

#define S3C2410_REFRESH_TRP_MASK	(3<<20)
#define S3C2410_REFRESH_TRP_2clk	(0<<20)
#define S3C2410_REFRESH_TRP_3clk	(1<<20)
#define S3C2410_REFRESH_TRP_4clk	(2<<20)

#define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)

#define S3C2410_REFRESH_TSRC_MASK	(3<<18)
#define S3C2410_REFRESH_TSRC_4clk	(0<<18)
#define S3C2410_REFRESH_TSRC_5clk	(1<<18)
#define S3C2410_REFRESH_TSRC_6clk	(2<<18)
#define S3C2410_REFRESH_TSRC_7clk	(3<<18)


/* mode select register(s) */

#define  S3C2410_MRSRB_CL1		(0x00 << 4)
#define  S3C2410_MRSRB_CL2		(0x02 << 4)
#define  S3C2410_MRSRB_CL3		(0x03 << 4)

/* bank size register */
#define S3C2410_BANKSIZE_128M		(0x2 << 0)
#define S3C2410_BANKSIZE_64M		(0x1 << 0)
#define S3C2410_BANKSIZE_32M		(0x0 << 0)
#define S3C2410_BANKSIZE_16M		(0x7 << 0)
#define S3C2410_BANKSIZE_8M		(0x6 << 0)
#define S3C2410_BANKSIZE_4M		(0x5 << 0)
#define S3C2410_BANKSIZE_2M		(0x4 << 0)
#define S3C2410_BANKSIZE_MASK		(0x7 << 0)
#define S3C2400_BANKSIZE_MASK           (0x4 << 0)
#define S3C2410_BANKSIZE_SCLK_EN	(1<<4)
#define S3C2410_BANKSIZE_SCKE_EN	(1<<5)
#define S3C2410_BANKSIZE_BURST		(1<<7)

#endif /* __ASM_ARM_MEMREGS_H */
Commit	Line	Data
1da177e4 LT	1	/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
	2	*
	3	* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
	4	* http://www.simtec.co.uk/products/SWLINUX/
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* S3C2410 Memory Control register definitions
1da177e4 LT	11	*/
	12
	13	#ifndef __ASM_ARM_MEMREGS_H
	14	#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
	15
	16	#ifndef S3C2410_MEMREG
	17	#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
	18	#endif
	19
	20	/* bus width, and wait state control */
	21	#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
	22
	23	/* bank zero config - note, pinstrapped from OM pins! */
	24	#define S3C2410_BWSCON_DW0_16 (1<<1)
	25	#define S3C2410_BWSCON_DW0_32 (2<<1)
	26
	27	/* bank one configs */
	28	#define S3C2410_BWSCON_DW1_8 (0<<4)
	29	#define S3C2410_BWSCON_DW1_16 (1<<4)
	30	#define S3C2410_BWSCON_DW1_32 (2<<4)
	31	#define S3C2410_BWSCON_WS1 (1<<6)
	32	#define S3C2410_BWSCON_ST1 (1<<7)
	33
	34	/* bank 2 configurations */
	35	#define S3C2410_BWSCON_DW2_8 (0<<8)
	36	#define S3C2410_BWSCON_DW2_16 (1<<8)
	37	#define S3C2410_BWSCON_DW2_32 (2<<8)
	38	#define S3C2410_BWSCON_WS2 (1<<10)
	39	#define S3C2410_BWSCON_ST2 (1<<11)
	40
	41	/* bank 3 configurations */
	42	#define S3C2410_BWSCON_DW3_8 (0<<12)
	43	#define S3C2410_BWSCON_DW3_16 (1<<12)
	44	#define S3C2410_BWSCON_DW3_32 (2<<12)
	45	#define S3C2410_BWSCON_WS3 (1<<14)
	46	#define S3C2410_BWSCON_ST3 (1<<15)
	47
	48	/* bank 4 configurations */
	49	#define S3C2410_BWSCON_DW4_8 (0<<16)
	50	#define S3C2410_BWSCON_DW4_16 (1<<16)
	51	#define S3C2410_BWSCON_DW4_32 (2<<16)
	52	#define S3C2410_BWSCON_WS4 (1<<18)
	53	#define S3C2410_BWSCON_ST4 (1<<19)
	54
	55	/* bank 5 configurations */
	56	#define S3C2410_BWSCON_DW5_8 (0<<20)
	57	#define S3C2410_BWSCON_DW5_16 (1<<20)
	58	#define S3C2410_BWSCON_DW5_32 (2<<20)
	59	#define S3C2410_BWSCON_WS5 (1<<22)
	60	#define S3C2410_BWSCON_ST5 (1<<23)
	61
	62	/* bank 6 configurations */
	63	#define S3C2410_BWSCON_DW6_8 (0<<24)
	64	#define S3C2410_BWSCON_DW6_16 (1<<24)
	65	#define S3C2410_BWSCON_DW6_32 (2<<24)
	66	#define S3C2410_BWSCON_WS6 (1<<26)
	67	#define S3C2410_BWSCON_ST6 (1<<27)
	68
	69	/* bank 7 configurations */
	70	#define S3C2410_BWSCON_DW7_8 (0<<28)
	71	#define S3C2410_BWSCON_DW7_16 (1<<28)
	72	#define S3C2410_BWSCON_DW7_32 (2<<28)
	73	#define S3C2410_BWSCON_WS7 (1<<30)
	74	#define S3C2410_BWSCON_ST7 (1<<31)
75
76	/* memory set (rom, ram) */
77	#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
78	#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
79	#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
80	#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
81	#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
82	#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
83	#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
84	#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
85
86	/* bank configuration registers */
87
88	#define S3C2410_BANKCON_PMCnorm (0x00)
89	#define S3C2410_BANKCON_PMC4 (0x01)
90	#define S3C2410_BANKCON_PMC8 (0x02)
91	#define S3C2410_BANKCON_PMC16 (0x03)
92
93	/* bank configurations for banks 0..7, note banks
94	* 6 and 7 have differnt configurations depending on
95	* the memory type bits */
96
97	#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
98	#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
99	#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
100	#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
e5812bf6	101	#define S3C2410_BANKCON_Tacp_SHIFT (2)
1da177e4 LT	102
	103	#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
	104	#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
	105	#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
	106	#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
e5812bf6	107	#define S3C2410_BANKCON_Tcah_SHIFT (4)
1da177e4 LT	108
	109	#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
	110	#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
	111	#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
	112	#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
e5812bf6	113	#define S3C2410_BANKCON_Tcoh_SHIFT (6)
1da177e4 LT	114
	115	#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
	116	#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
	117	#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
	118	#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
	119	#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
	120	#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
	121	#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
	122	#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
e5812bf6	123	#define S3C2410_BANKCON_Tacc_SHIFT (8)
1da177e4 LT	124
	125	#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
	126	#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
	127	#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
	128	#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
e5812bf6	129	#define S3C2410_BANKCON_Tcos_SHIFT (11)
1da177e4 LT	130
	131	#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
	132	#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
	133	#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
	134	#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
e5812bf6	135	#define S3C2410_BANKCON_Tacs_SHIFT (13)
1da177e4 LT	136
	137	#define S3C2410_BANKCON_SRAM (0x0 << 15)
	138	#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
	139	#define S3C2410_BANKCON_SDRAM (0x3 << 15)
	140
	141	/* next bits only for EDO DRAM in 6,7 */
7baced8a MR	142	#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
	143	#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
	144	#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
	145	#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
1da177e4 LT	146
	147	/* CAS pulse width */
	148	#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
	149	#define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3)
	150
	151	/* CAS pre-charge */
	152	#define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2)
	153	#define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2)
	154
	155	/* control column address select */
	156	#define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0)
	157	#define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0)
	158	#define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0)
	159	#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
	160
	161	/* next bits only for SDRAM in 6,7 */
7baced8a MR	162	#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
	163	#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
	164	#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
1da177e4 LT	165
	166	/* control column address select */
	167	#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
	168	#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
	169	#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
	170
	171	#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
	172	#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
	173	#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
	174	#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
	175
	176	/* refresh control */
	177
	178	#define S3C2410_REFRESH_REFEN (1<<23)
	179	#define S3C2410_REFRESH_SELF (1<<22)
	180	#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
	181
	182	#define S3C2410_REFRESH_TRP_MASK (3<<20)
	183	#define S3C2410_REFRESH_TRP_2clk (0<<20)
	184	#define S3C2410_REFRESH_TRP_3clk (1<<20)
	185	#define S3C2410_REFRESH_TRP_4clk (2<<20)
	186
a3342421 LCVR	187	#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20)
	188	#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
	189	#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
	190	#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
	191	#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
	192
1da177e4 LT	193	#define S3C2410_REFRESH_TSRC_MASK (3<<18)
	194	#define S3C2410_REFRESH_TSRC_4clk (0<<18)
	195	#define S3C2410_REFRESH_TSRC_5clk (1<<18)
	196	#define S3C2410_REFRESH_TSRC_6clk (2<<18)
	197	#define S3C2410_REFRESH_TSRC_7clk (3<<18)
	198
	199
	200	/* mode select register(s) */
	201
	202	#define S3C2410_MRSRB_CL1 (0x00 << 4)
	203	#define S3C2410_MRSRB_CL2 (0x02 << 4)
	204	#define S3C2410_MRSRB_CL3 (0x03 << 4)
	205
	206	/* bank size register */
	207	#define S3C2410_BANKSIZE_128M (0x2 << 0)
	208	#define S3C2410_BANKSIZE_64M (0x1 << 0)
	209	#define S3C2410_BANKSIZE_32M (0x0 << 0)
	210	#define S3C2410_BANKSIZE_16M (0x7 << 0)
	211	#define S3C2410_BANKSIZE_8M (0x6 << 0)
	212	#define S3C2410_BANKSIZE_4M (0x5 << 0)
	213	#define S3C2410_BANKSIZE_2M (0x4 << 0)
	214	#define S3C2410_BANKSIZE_MASK (0x7 << 0)
a3342421	215	#define S3C2400_BANKSIZE_MASK (0x4 << 0)
1da177e4 LT	216	#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
	217	#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
	218	#define S3C2410_BANKSIZE_BURST (1<<7)
	219
	220	#endif /* __ASM_ARM_MEMREGS_H */