projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| f30c2269 | 1 | /* linux/include/asm-arm/arch-s3c2410/regs-sdi.h |
| 1da177e4 LT |
2 | * |
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * S3C2410 MMC/SDIO register definitions | |
| 1da177e4 LT |
11 | */ |
| 12 | ||
| 13 | #ifndef __ASM_ARM_REGS_SDI | |
| 14 | #define __ASM_ARM_REGS_SDI "regs-sdi.h" | |
| 15 | ||
| 16 | #define S3C2410_SDICON (0x00) | |
| 17 | #define S3C2410_SDIPRE (0x04) | |
| 18 | #define S3C2410_SDICMDARG (0x08) | |
| 19 | #define S3C2410_SDICMDCON (0x0C) | |
| 20 | #define S3C2410_SDICMDSTAT (0x10) | |
| 21 | #define S3C2410_SDIRSP0 (0x14) | |
| 22 | #define S3C2410_SDIRSP1 (0x18) | |
| 23 | #define S3C2410_SDIRSP2 (0x1C) | |
| 24 | #define S3C2410_SDIRSP3 (0x20) | |
| 25 | #define S3C2410_SDITIMER (0x24) | |
| 26 | #define S3C2410_SDIBSIZE (0x28) | |
| 27 | #define S3C2410_SDIDCON (0x2C) | |
| 28 | #define S3C2410_SDIDCNT (0x30) | |
| 29 | #define S3C2410_SDIDSTA (0x34) | |
| 30 | #define S3C2410_SDIFSTA (0x38) | |
| 31 | #define S3C2410_SDIDATA (0x3C) | |
| 32 | #define S3C2410_SDIIMSK (0x40) | |
| 33 | ||
| 34 | #define S3C2410_SDICON_BYTEORDER (1<<4) | |
| 35 | #define S3C2410_SDICON_SDIOIRQ (1<<3) | |
| 36 | #define S3C2410_SDICON_RWAITEN (1<<2) | |
| 37 | #define S3C2410_SDICON_FIFORESET (1<<1) | |
| 38 | #define S3C2410_SDICON_CLOCKTYPE (1<<0) | |
| 39 | ||
| 40 | #define S3C2410_SDICMDCON_ABORT (1<<12) | |
| 41 | #define S3C2410_SDICMDCON_WITHDATA (1<<11) | |
| 42 | #define S3C2410_SDICMDCON_LONGRSP (1<<10) | |
| 43 | #define S3C2410_SDICMDCON_WAITRSP (1<<9) | |
| 44 | #define S3C2410_SDICMDCON_CMDSTART (1<<8) | |
| 45 | #define S3C2410_SDICMDCON_INDEX (0xff) | |
| 46 | ||
| 47 | #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) | |
| 48 | #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) | |
| 49 | #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) | |
| 50 | #define S3C2410_SDICMDSTAT_RSPFIN (1<<9) | |
| 51 | #define S3C2410_SDICMDSTAT_XFERING (1<<8) | |
| 52 | #define S3C2410_SDICMDSTAT_INDEX (0xff) | |
| 53 | ||
| 54 | #define S3C2410_SDIDCON_IRQPERIOD (1<<21) | |
| 55 | #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) | |
| 56 | #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) | |
| 57 | #define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) | |
| 58 | #define S3C2410_SDIDCON_BLOCKMODE (1<<17) | |
| 59 | #define S3C2410_SDIDCON_WIDEBUS (1<<16) | |
| 60 | #define S3C2410_SDIDCON_DMAEN (1<<15) | |
| 61 | #define S3C2410_SDIDCON_STOP (1<<14) | |
| 62 | #define S3C2410_SDIDCON_DATMODE (3<<12) | |
| 63 | #define S3C2410_SDIDCON_BLKNUM (0x7ff) | |
| 64 | ||
| 65 | /* constants for S3C2410_SDIDCON_DATMODE */ | |
| 66 | #define S3C2410_SDIDCON_XFER_READY (0<<12) | |
| 67 | #define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) | |
| 68 | #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) | |
| 69 | #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) | |
| 70 | ||
| 71 | #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) | |
| 72 | ||
| 73 | #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) | |
| 74 | #define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) | |
| 75 | #define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ | |
| 76 | #define S3C2410_SDIDSTA_CRCFAIL (1<<7) | |
| 77 | #define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) | |
| 78 | #define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) | |
| 79 | #define S3C2410_SDIDSTA_XFERFINISH (1<<4) | |
| 80 | #define S3C2410_SDIDSTA_BUSYFINISH (1<<3) | |
| 81 | #define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ | |
| 82 | #define S3C2410_SDIDSTA_TXDATAON (1<<1) | |
| 83 | #define S3C2410_SDIDSTA_RXDATAON (1<<0) | |
| 84 | ||
| 85 | #define S3C2410_SDIFSTA_TFDET (1<<13) | |
| 86 | #define S3C2410_SDIFSTA_RFDET (1<<12) | |
| 87 | #define S3C2410_SDIFSTA_TXHALF (1<<11) | |
| 88 | #define S3C2410_SDIFSTA_TXEMPTY (1<<10) | |
| 89 | #define S3C2410_SDIFSTA_RFLAST (1<<9) | |
| 90 | #define S3C2410_SDIFSTA_RFFULL (1<<8) | |
| 91 | #define S3C2410_SDIFSTA_RFHALF (1<<7) | |
| 92 | #define S3C2410_SDIFSTA_COUNTMASK (0x7f) | |
| 93 | ||
| 94 | #define S3C2410_SDIIMSK_RESPONSECRC (1<<17) | |
| 95 | #define S3C2410_SDIIMSK_CMDSENT (1<<16) | |
| 96 | #define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) | |
| 97 | #define S3C2410_SDIIMSK_RESPONSEND (1<<14) | |
| 98 | #define S3C2410_SDIIMSK_READWAIT (1<<13) | |
| 99 | #define S3C2410_SDIIMSK_SDIOIRQ (1<<12) | |
| 100 | #define S3C2410_SDIIMSK_FIFOFAIL (1<<11) | |
| 101 | #define S3C2410_SDIIMSK_CRCSTATUS (1<<10) | |
| 102 | #define S3C2410_SDIIMSK_DATACRC (1<<9) | |
| 103 | #define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) | |
| 104 | #define S3C2410_SDIIMSK_DATAFINISH (1<<7) | |
| 105 | #define S3C2410_SDIIMSK_BUSYFINISH (1<<6) | |
| 106 | #define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ | |
| 107 | #define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) | |
| 108 | #define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) | |
| 109 | #define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) | |
| 110 | #define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) | |
| 111 | #define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) | |
| 112 | ||
| 113 | #endif /* __ASM_ARM_REGS_SDI */ |