[mirror_ubuntu-artful-kernel.git] / include / asm-arm / atomic.h

/*
 *  linux/include/asm-arm/atomic.h
 *
 *  Copyright (C) 1996 Russell King.
 *  Copyright (C) 2002 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ASM_ARM_ATOMIC_H
#define __ASM_ARM_ATOMIC_H

#include <linux/config.h>

typedef struct { volatile int counter; } atomic_t;

#define ATOMIC_INIT(i)	{ (i) }

#ifdef __KERNEL__

#define atomic_read(v)	((v)->counter)

#if __LINUX_ARM_ARCH__ >= 6

/*
 * ARMv6 UP and SMP safe atomic ops.  We use load exclusive and
 * store exclusive to ensure that these are atomic.  We may loop
 * to ensure that the update happens.  Writing to 'v->counter'
 * without using the following operations WILL break the atomic
 * nature of these ops.
 */
static inline void atomic_set(atomic_t *v, int i)
{
	unsigned long tmp;

	__asm__ __volatile__("@ atomic_set\n"
"1:	ldrex	%0, [%1]\n"
"	strex	%0, %2, [%1]\n"
"	teq	%0, #0\n"
"	bne	1b"
	: "=&r" (tmp)
	: "r" (&v->counter), "r" (i)
	: "cc");
}

static inline int atomic_add_return(int i, atomic_t *v)
{
	unsigned long tmp;
	int result;

	__asm__ __volatile__("@ atomic_add_return\n"
"1:	ldrex	%0, [%2]\n"
"	add	%0, %0, %3\n"
"	strex	%1, %0, [%2]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp)
	: "r" (&v->counter), "Ir" (i)
	: "cc");

	return result;
}

static inline int atomic_sub_return(int i, atomic_t *v)
{
	unsigned long tmp;
	int result;

	__asm__ __volatile__("@ atomic_sub_return\n"
"1:	ldrex	%0, [%2]\n"
"	sub	%0, %0, %3\n"
"	strex	%1, %0, [%2]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp)
	: "r" (&v->counter), "Ir" (i)
	: "cc");

	return result;
}

static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
{
	u32 oldval, res;

	do {
		__asm__ __volatile__("@ atomic_cmpxchg\n"
		"ldrex	%1, [%2]\n"
		"teq	%1, %3\n"
		"strexeq %0, %4, [%2]\n"
		    : "=&r" (res), "=&r" (oldval)
		    : "r" (&ptr->counter), "Ir" (old), "r" (new)
		    : "cc");
	} while (res);

	return oldval;
}

static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
{
	unsigned long tmp, tmp2;

	__asm__ __volatile__("@ atomic_clear_mask\n"
"1:	ldrex	%0, %2\n"
"	bic	%0, %0, %3\n"
"	strex	%1, %0, %2\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (tmp), "=&r" (tmp2)
	: "r" (addr), "Ir" (mask)
	: "cc");
}

#else /* ARM_ARCH_6 */

#include <asm/system.h>

#ifdef CONFIG_SMP
#error SMP not supported on pre-ARMv6 CPUs
#endif

#define atomic_set(v,i)	(((v)->counter) = (i))

static inline int atomic_add_return(int i, atomic_t *v)
{
	unsigned long flags;
	int val;

	local_irq_save(flags);
	val = v->counter;
	v->counter = val += i;
	local_irq_restore(flags);

	return val;
}

static inline int atomic_sub_return(int i, atomic_t *v)
{
	unsigned long flags;
	int val;

	local_irq_save(flags);
	val = v->counter;
	v->counter = val -= i;
	local_irq_restore(flags);

	return val;
}

static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
	int ret;
	unsigned long flags;

	local_irq_save(flags);
	ret = v->counter;
	if (likely(ret == old))
		v->counter = new;
	local_irq_restore(flags);

	return ret;
}

static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
{
	unsigned long flags;

	local_irq_save(flags);
	*addr &= ~mask;
	local_irq_restore(flags);
}

#endif /* __LINUX_ARM_ARCH__ */

static inline int atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;

	c = atomic_read(v);
	while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
		c = old;
	return c != u;
}
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)

#define atomic_add(i, v)	(void) atomic_add_return(i, v)
#define atomic_inc(v)		(void) atomic_add_return(1, v)
#define atomic_sub(i, v)	(void) atomic_sub_return(i, v)
#define atomic_dec(v)		(void) atomic_sub_return(1, v)

#define atomic_inc_and_test(v)	(atomic_add_return(1, v) == 0)
#define atomic_dec_and_test(v)	(atomic_sub_return(1, v) == 0)
#define atomic_inc_return(v)    (atomic_add_return(1, v))
#define atomic_dec_return(v)    (atomic_sub_return(1, v))
#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)

#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)

/* Atomic operations are already serializing on ARM */
#define smp_mb__before_atomic_dec()	barrier()
#define smp_mb__after_atomic_dec()	barrier()
#define smp_mb__before_atomic_inc()	barrier()
#define smp_mb__after_atomic_inc()	barrier()

#endif
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-arm/atomic.h
	3	*
	4	* Copyright (C) 1996 Russell King.
	5	* Copyright (C) 2002 Deep Blue Solutions Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef __ASM_ARM_ATOMIC_H
	12	#define __ASM_ARM_ATOMIC_H
	13
	14	#include <linux/config.h>
	15
	16	typedef struct { volatile int counter; } atomic_t;
	17
	18	#define ATOMIC_INIT(i) { (i) }
	19
	20	#ifdef __KERNEL__
	21
	22	#define atomic_read(v) ((v)->counter)
	23
	24	#if __LINUX_ARM_ARCH__ >= 6
	25
	26	/*
	27	* ARMv6 UP and SMP safe atomic ops. We use load exclusive and
	28	* store exclusive to ensure that these are atomic. We may loop
	29	* to ensure that the update happens. Writing to 'v->counter'
	30	* without using the following operations WILL break the atomic
	31	* nature of these ops.
	32	*/
	33	static inline void atomic_set(atomic_t *v, int i)
	34	{
	35	unsigned long tmp;
	36
	37	__asm__ __volatile__("@ atomic_set\n"
	38	"1: ldrex %0, [%1]\n"
	39	" strex %0, %2, [%1]\n"
	40	" teq %0, #0\n"
	41	" bne 1b"
	42	: "=&r" (tmp)
	43	: "r" (&v->counter), "r" (i)
	44	: "cc");
	45	}
	46
	47	static inline int atomic_add_return(int i, atomic_t *v)
	48	{
	49	unsigned long tmp;
	50	int result;
	51
	52	__asm__ __volatile__("@ atomic_add_return\n"
	53	"1: ldrex %0, [%2]\n"
	54	" add %0, %0, %3\n"
	55	" strex %1, %0, [%2]\n"
	56	" teq %1, #0\n"
	57	" bne 1b"
	58	: "=&r" (result), "=&r" (tmp)
	59	: "r" (&v->counter), "Ir" (i)
	60	: "cc");
	61
	62	return result;
	63	}
	64
65	static inline int atomic_sub_return(int i, atomic_t *v)
66	{
67	unsigned long tmp;
68	int result;
69
70	__asm__ __volatile__("@ atomic_sub_return\n"
71	"1: ldrex %0, [%2]\n"
72	" sub %0, %0, %3\n"
73	" strex %1, %0, [%2]\n"
74	" teq %1, #0\n"
75	" bne 1b"
76	: "=&r" (result), "=&r" (tmp)
77	: "r" (&v->counter), "Ir" (i)
78	: "cc");
79
80	return result;
81	}
82
4a6dae6d NP	83	static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
	84	{
	85	u32 oldval, res;
	86
	87	do {
	88	__asm__ __volatile__("@ atomic_cmpxchg\n"
	89	"ldrex %1, [%2]\n"
	90	"teq %1, %3\n"
	91	"strexeq %0, %4, [%2]\n"
	92	: "=&r" (res), "=&r" (oldval)
	93	: "r" (&ptr->counter), "Ir" (old), "r" (new)
	94	: "cc");
	95	} while (res);
	96
	97	return oldval;
	98	}
	99
1da177e4 LT	100	static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
	101	{
	102	unsigned long tmp, tmp2;
	103
	104	__asm__ __volatile__("@ atomic_clear_mask\n"
	105	"1: ldrex %0, %2\n"
	106	" bic %0, %0, %3\n"
	107	" strex %1, %0, %2\n"
	108	" teq %1, #0\n"
	109	" bne 1b"
	110	: "=&r" (tmp), "=&r" (tmp2)
	111	: "r" (addr), "Ir" (mask)
	112	: "cc");
	113	}
	114
	115	#else /* ARM_ARCH_6 */
	116
	117	#include <asm/system.h>
	118
	119	#ifdef CONFIG_SMP
	120	#error SMP not supported on pre-ARMv6 CPUs
	121	#endif
	122
	123	#define atomic_set(v,i) (((v)->counter) = (i))
	124
	125	static inline int atomic_add_return(int i, atomic_t *v)
	126	{
	127	unsigned long flags;
	128	int val;
	129
	130	local_irq_save(flags);
	131	val = v->counter;
	132	v->counter = val += i;
	133	local_irq_restore(flags);
	134
	135	return val;
	136	}
	137
	138	static inline int atomic_sub_return(int i, atomic_t *v)
	139	{
	140	unsigned long flags;
	141	int val;
	142
	143	local_irq_save(flags);
	144	val = v->counter;
	145	v->counter = val -= i;
	146	local_irq_restore(flags);
	147
	148	return val;
	149	}
	150
4a6dae6d NP	151	static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
	152	{
	153	int ret;
	154	unsigned long flags;
	155
	156	local_irq_save(flags);
	157	ret = v->counter;
	158	if (likely(ret == old))
	159	v->counter = new;
	160	local_irq_restore(flags);
	161
	162	return ret;
	163	}
	164
1da177e4 LT	165	static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
	166	{
	167	unsigned long flags;
	168
	169	local_irq_save(flags);
	170	*addr &= ~mask;
	171	local_irq_restore(flags);
	172	}
	173
	174	#endif /* __LINUX_ARM_ARCH__ */
	175
8426e1f6 NP	176	static inline int atomic_add_unless(atomic_t *v, int a, int u)
	177	{
	178	int c, old;
	179
	180	c = atomic_read(v);
	181	while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
	182	c = old;
	183	return c != u;
	184	}
	185	#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
	186
1da177e4 LT	187	#define atomic_add(i, v) (void) atomic_add_return(i, v)
	188	#define atomic_inc(v) (void) atomic_add_return(1, v)
	189	#define atomic_sub(i, v) (void) atomic_sub_return(i, v)
	190	#define atomic_dec(v) (void) atomic_sub_return(1, v)
	191
	192	#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
	193	#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
	194	#define atomic_inc_return(v) (atomic_add_return(1, v))
	195	#define atomic_dec_return(v) (atomic_sub_return(1, v))
	196	#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
	197
	198	#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
	199
	200	/* Atomic operations are already serializing on ARM */
	201	#define smp_mb__before_atomic_dec() barrier()
	202	#define smp_mb__after_atomic_dec() barrier()
	203	#define smp_mb__before_atomic_inc() barrier()
	204	#define smp_mb__after_atomic_inc() barrier()
	205
	206	#endif
	207	#endif