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7ae1f7ec LB |
1 | /* |
2 | * include/asm-arm/hardware/iop3xx.h | |
3 | * | |
4 | * Intel IOP32X and IOP33X register definitions | |
5 | * | |
6 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
7 | * Copyright (C) 2002 Rory Bolt | |
8 | * Copyright (C) 2004 Intel Corp. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #ifndef __IOP3XX_H | |
16 | #define __IOP3XX_H | |
17 | ||
72edd84a LB |
18 | /* |
19 | * IOP3XX GPIO handling | |
20 | */ | |
21 | #define GPIO_IN 0 | |
22 | #define GPIO_OUT 1 | |
23 | #define GPIO_LOW 0 | |
24 | #define GPIO_HIGH 1 | |
25 | #define IOP3XX_GPIO_LINE(x) (x) | |
26 | ||
27 | #ifndef __ASSEMBLY__ | |
28 | extern void gpio_line_config(int line, int direction); | |
29 | extern int gpio_line_get(int line); | |
30 | extern void gpio_line_set(int line, int value); | |
31 | #endif | |
32 | ||
33 | ||
7ae1f7ec LB |
34 | /* |
35 | * IOP3XX processor registers | |
36 | */ | |
37 | #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 | |
38 | #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000 | |
39 | #define IOP3XX_PERIPHERAL_SIZE 0x00002000 | |
6df26700 DW |
40 | #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\ |
41 | IOP3XX_PERIPHERAL_SIZE - 1) | |
42 | #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ | |
43 | IOP3XX_PERIPHERAL_SIZE - 1) | |
44 | #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | |
45 | (IOP3XX_PERIPHERAL_PHYS_BASE\ | |
46 | - IOP3XX_PERIPHERAL_VIRT_BASE)) | |
7ae1f7ec LB |
47 | #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) |
48 | ||
0cb015f9 LB |
49 | /* Address Translation Unit */ |
50 | #define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100) | |
51 | #define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102) | |
52 | #define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104) | |
53 | #define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106) | |
54 | #define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108) | |
55 | #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109) | |
56 | #define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c) | |
57 | #define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d) | |
58 | #define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e) | |
59 | #define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f) | |
60 | #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110) | |
61 | #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114) | |
62 | #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118) | |
63 | #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c) | |
64 | #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120) | |
65 | #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124) | |
66 | #define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c) | |
67 | #define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e) | |
68 | #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130) | |
69 | #define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c) | |
70 | #define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d) | |
71 | #define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e) | |
72 | #define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f) | |
73 | #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140) | |
74 | #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144) | |
75 | #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148) | |
76 | #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c) | |
77 | #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150) | |
78 | #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154) | |
79 | #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158) | |
80 | #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c) | |
81 | #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160) | |
82 | #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164) | |
83 | #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168) | |
84 | #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c) | |
85 | #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178) | |
86 | #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180) | |
87 | #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184) | |
88 | #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188) | |
89 | #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c) | |
90 | #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190) | |
91 | #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194) | |
92 | #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198) | |
93 | #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c) | |
94 | #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4) | |
95 | #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac) | |
96 | #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc) | |
97 | #define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0) | |
98 | #define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1) | |
99 | #define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2) | |
100 | #define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4) | |
101 | #define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0) | |
102 | #define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1) | |
103 | #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) | |
104 | #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) | |
105 | #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) | |
106 | ||
475549fa LB |
107 | /* Messaging Unit */ |
108 | #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) | |
109 | #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) | |
110 | #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318) | |
111 | #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c) | |
112 | #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320) | |
113 | #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324) | |
114 | #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328) | |
115 | #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c) | |
116 | #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330) | |
117 | #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334) | |
118 | #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350) | |
119 | #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354) | |
120 | #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360) | |
121 | #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364) | |
122 | #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368) | |
123 | #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c) | |
124 | #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370) | |
125 | #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374) | |
126 | #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378) | |
127 | #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c) | |
128 | #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) | |
129 | ||
130 | /* DMA Controller */ | |
131 | #define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400) | |
132 | #define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404) | |
133 | #define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c) | |
134 | #define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410) | |
135 | #define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414) | |
136 | #define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418) | |
137 | #define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c) | |
138 | #define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420) | |
139 | #define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424) | |
140 | #define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440) | |
141 | #define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444) | |
142 | #define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c) | |
143 | #define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450) | |
144 | #define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454) | |
145 | #define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458) | |
146 | #define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c) | |
147 | #define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460) | |
148 | #define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464) | |
149 | ||
150 | /* Peripheral bus interface */ | |
151 | #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) | |
152 | #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684) | |
153 | #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688) | |
154 | #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c) | |
155 | #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690) | |
156 | #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694) | |
157 | #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698) | |
158 | #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c) | |
159 | #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0) | |
160 | #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4) | |
161 | #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8) | |
162 | #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac) | |
163 | #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0) | |
164 | #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4) | |
165 | #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0) | |
166 | #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0) | |
167 | #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4) | |
168 | ||
169 | /* Peripheral performance monitoring unit */ | |
170 | #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700) | |
171 | #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704) | |
172 | #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708) | |
173 | #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710) | |
174 | /* PERCR0 DOESN'T EXIST - index from 1! */ | |
175 | #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) | |
176 | ||
72edd84a | 177 | /* General Purpose I/O */ |
4ac941d2 DW |
178 | #define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000) |
179 | #define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004) | |
180 | #define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008) | |
72edd84a | 181 | |
48388b2a LB |
182 | /* Timers */ |
183 | #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) | |
184 | #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) | |
185 | #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008) | |
186 | #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c) | |
187 | #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010) | |
188 | #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) | |
189 | #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) | |
190 | #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) | |
191 | #define IOP3XX_TMR_TC 0x01 | |
192 | #define IOP3XX_TMR_EN 0x02 | |
193 | #define IOP3XX_TMR_RELOAD 0x04 | |
194 | #define IOP3XX_TMR_PRIVILEGED 0x09 | |
195 | #define IOP3XX_TMR_RATIO_1_1 0x00 | |
196 | #define IOP3XX_TMR_RATIO_4_1 0x10 | |
197 | #define IOP3XX_TMR_RATIO_8_1 0x20 | |
198 | #define IOP3XX_TMR_RATIO_16_1 0x30 | |
199 | ||
475549fa LB |
200 | /* Application accelerator unit */ |
201 | #define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) | |
202 | #define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804) | |
203 | #define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808) | |
204 | #define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c) | |
205 | #define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810) | |
206 | #define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814) | |
207 | #define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818) | |
208 | #define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c) | |
209 | #define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820) | |
210 | #define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824) | |
211 | #define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828) | |
212 | #define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c) | |
213 | #define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830) | |
214 | #define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834) | |
215 | #define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838) | |
216 | #define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c) | |
217 | #define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840) | |
218 | #define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844) | |
219 | #define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848) | |
220 | #define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c) | |
221 | #define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850) | |
222 | #define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854) | |
223 | #define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858) | |
224 | #define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c) | |
225 | #define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860) | |
226 | #define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864) | |
227 | #define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868) | |
228 | #define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c) | |
229 | #define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870) | |
230 | #define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874) | |
231 | #define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878) | |
232 | #define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c) | |
233 | #define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880) | |
234 | #define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884) | |
235 | #define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888) | |
236 | #define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c) | |
237 | #define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890) | |
238 | #define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894) | |
239 | #define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898) | |
240 | #define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c) | |
241 | #define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0) | |
242 | #define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4) | |
243 | ||
e25d64f1 LB |
244 | /* I2C bus interface unit */ |
245 | #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) | |
246 | #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) | |
247 | #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688) | |
248 | #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c) | |
249 | #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694) | |
250 | #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0) | |
251 | #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4) | |
252 | #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8) | |
253 | #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac) | |
254 | #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4) | |
255 | ||
7ae1f7ec LB |
256 | |
257 | /* | |
258 | * IOP3XX I/O and Mem space regions for PCI autoconfiguration | |
259 | */ | |
260 | #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 | |
261 | #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 | |
0cb015f9 | 262 | #define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0) |
7ae1f7ec LB |
263 | |
264 | #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 | |
265 | #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 | |
266 | #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 | |
0cb015f9 | 267 | #define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR) |
6df26700 DW |
268 | #define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ |
269 | IOP3XX_PCI_IO_WINDOW_SIZE - 1) | |
270 | #define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ | |
271 | IOP3XX_PCI_IO_WINDOW_SIZE - 1) | |
272 | #define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\ | |
273 | IOP3XX_PCI_LOWER_IO_PA) +\ | |
274 | IOP3XX_PCI_LOWER_IO_VA) | |
7ae1f7ec LB |
275 | |
276 | ||
277 | #ifndef __ASSEMBLY__ | |
278 | void iop3xx_map_io(void); | |
48388b2a LB |
279 | void iop3xx_init_time(unsigned long); |
280 | unsigned long iop3xx_gettimeoffset(void); | |
588ef769 | 281 | void iop_init_cp6_handler(void); |
e25d64f1 LB |
282 | |
283 | extern struct platform_device iop3xx_i2c0_device; | |
284 | extern struct platform_device iop3xx_i2c1_device; | |
0b29de4a | 285 | |
7ae1f7ec LB |
286 | #endif |
287 | ||
288 | ||
289 | #endif |