[mirror_ubuntu-hirsute-kernel.git] / include / asm-arm / hardware / iop3xx.h

/*
 * include/asm-arm/hardware/iop3xx.h
 *
 * Intel IOP32X and IOP33X register definitions
 *
 * Author: Rory Bolt <rorybolt@pacbell.net>
 * Copyright (C) 2002 Rory Bolt
 * Copyright (C) 2004 Intel Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __IOP3XX_H
#define __IOP3XX_H

/*
 * IOP3XX GPIO handling
 */
#define GPIO_IN			0
#define GPIO_OUT		1
#define GPIO_LOW		0
#define GPIO_HIGH		1
#define IOP3XX_GPIO_LINE(x)	(x)

#ifndef __ASSEMBLY__
extern void gpio_line_config(int line, int direction);
extern int  gpio_line_get(int line);
extern void gpio_line_set(int line, int value);
#endif


/*
 * IOP3XX processor registers
 */
#define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
#define IOP3XX_PERIPHERAL_VIRT_BASE	0xfeffe000
#define IOP3XX_PERIPHERAL_SIZE		0x00002000
#define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))

/* Address Translation Unit  */
#define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
#define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
#define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
#define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
#define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
#define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
#define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
#define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
#define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
#define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
#define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
#define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
#define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
#define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
#define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
#define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
#define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
#define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
#define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
#define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
#define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
#define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
#define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
#define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
#define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
#define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
#define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
#define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
#define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
#define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
#define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
#define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
#define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
#define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
#define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
#define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
#define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
#define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
#define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
#define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
#define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
#define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
#define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
#define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
#define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
#define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
#define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
#define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
#define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
#define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
#define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
#define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
#define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
#define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
#define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
#define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)

/* General Purpose I/O  */
#define IOP3XX_GPOE		(volatile u32 *)IOP3XX_GPIO_REG(0x0004)
#define IOP3XX_GPID		(volatile u32 *)IOP3XX_GPIO_REG(0x0008)
#define IOP3XX_GPOD		(volatile u32 *)IOP3XX_GPIO_REG(0x000c)

/* Timers  */
#define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
#define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
#define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
#define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
#define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
#define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
#define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
#define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
#define IOP3XX_TMR_TC		0x01
#define IOP3XX_TMR_EN		0x02
#define IOP3XX_TMR_RELOAD	0x04
#define IOP3XX_TMR_PRIVILEGED	0x09
#define IOP3XX_TMR_RATIO_1_1	0x00
#define IOP3XX_TMR_RATIO_4_1	0x10
#define IOP3XX_TMR_RATIO_8_1	0x20
#define IOP3XX_TMR_RATIO_16_1	0x30

/* I2C bus interface unit  */
#define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
#define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
#define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
#define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
#define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
#define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
#define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
#define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
#define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
#define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)


/*
 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
 */
#define IOP3XX_PCI_MEM_WINDOW_SIZE	0x04000000
#define IOP3XX_PCI_LOWER_MEM_PA		0x80000000
#define IOP3XX_PCI_LOWER_MEM_BA		(*IOP3XX_OMWTVR0)

#define IOP3XX_PCI_IO_WINDOW_SIZE	0x00010000
#define IOP3XX_PCI_LOWER_IO_PA		0x90000000
#define IOP3XX_PCI_LOWER_IO_VA		0xfe000000
#define IOP3XX_PCI_LOWER_IO_BA		(*IOP3XX_OIOWTVR)


#ifndef __ASSEMBLY__
void iop3xx_map_io(void);
void iop3xx_init_time(unsigned long);
unsigned long iop3xx_gettimeoffset(void);

extern struct platform_device iop3xx_i2c0_device;
extern struct platform_device iop3xx_i2c1_device;

extern inline void iop3xx_cp6_enable(void)
{
	u32 temp;

	asm volatile (
		"mrc	p15, 0, %0, c15, c1, 0\n\t"
		"orr	%0, %0, #(1 << 6)\n\t"
		"mcr	p15, 0, %0, c15, c1, 0\n\t"
		"mrc	p15, 0, %0, c15, c1, 0\n\t"
		"mov	%0, %0\n\t"
		"sub	pc, pc, #4\n\t"
		: "=r" (temp) );
}

extern inline void iop3xx_cp6_disable(void)
{
	u32 temp;

	asm volatile (
		"mrc	p15, 0, %0, c15, c1, 0\n\t"
		"bic	%0, %0, #(1 << 6)\n\t"
		"mcr	p15, 0, %0, c15, c1, 0\n\t"
		"mrc	p15, 0, %0, c15, c1, 0\n\t"
		"mov	%0, %0\n\t"
		"sub	pc, pc, #4\n\t"
		: "=r" (temp) );
}
#endif


#endif
Commit	Line	Data
7ae1f7ec LB	1	/*
	2	* include/asm-arm/hardware/iop3xx.h
	3	*
	4	* Intel IOP32X and IOP33X register definitions
	5	*
	6	* Author: Rory Bolt <rorybolt@pacbell.net>
	7	* Copyright (C) 2002 Rory Bolt
	8	* Copyright (C) 2004 Intel Corp.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#ifndef __IOP3XX_H
	16	#define __IOP3XX_H
	17
72edd84a LB	18	/*
	19	* IOP3XX GPIO handling
	20	*/
	21	#define GPIO_IN 0
	22	#define GPIO_OUT 1
	23	#define GPIO_LOW 0
	24	#define GPIO_HIGH 1
	25	#define IOP3XX_GPIO_LINE(x) (x)
	26
	27	#ifndef __ASSEMBLY__
	28	extern void gpio_line_config(int line, int direction);
	29	extern int gpio_line_get(int line);
	30	extern void gpio_line_set(int line, int value);
	31	#endif
	32
	33
7ae1f7ec LB	34	/*
	35	* IOP3XX processor registers
	36	*/
	37	#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
	38	#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
	39	#define IOP3XX_PERIPHERAL_SIZE 0x00002000
	40	#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
	41
0cb015f9 LB	42	/* Address Translation Unit */
	43	#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
	44	#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
	45	#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
	46	#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
	47	#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
	48	#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
	49	#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
	50	#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
	51	#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
	52	#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
	53	#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
	54	#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
	55	#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
	56	#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
	57	#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
	58	#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
	59	#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
	60	#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
	61	#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
	62	#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
	63	#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
	64	#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
	65	#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
	66	#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
	67	#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
	68	#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
	69	#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
	70	#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
	71	#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
	72	#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
	73	#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
	74	#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
	75	#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
	76	#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
	77	#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
	78	#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
	79	#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
	80	#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
	81	#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
	82	#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
	83	#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
	84	#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
	85	#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
	86	#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
	87	#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
	88	#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
	89	#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
	90	#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
	91	#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
	92	#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
	93	#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
	94	#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
	95	#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
	96	#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
	97	#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
	98	#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
	99
72edd84a LB	100	/* General Purpose I/O */
	101	#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
	102	#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
	103	#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x000c)
	104
48388b2a LB	105	/* Timers */
	106	#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
	107	#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
	108	#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
	109	#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
	110	#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
	111	#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
	112	#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
	113	#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
	114	#define IOP3XX_TMR_TC 0x01
	115	#define IOP3XX_TMR_EN 0x02
	116	#define IOP3XX_TMR_RELOAD 0x04
	117	#define IOP3XX_TMR_PRIVILEGED 0x09
	118	#define IOP3XX_TMR_RATIO_1_1 0x00
	119	#define IOP3XX_TMR_RATIO_4_1 0x10
	120	#define IOP3XX_TMR_RATIO_8_1 0x20
	121	#define IOP3XX_TMR_RATIO_16_1 0x30
	122
e25d64f1 LB	123	/* I2C bus interface unit */
	124	#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
	125	#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
	126	#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
	127	#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
	128	#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
	129	#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
	130	#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
	131	#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
	132	#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
	133	#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
	134
7ae1f7ec LB	135
	136	/*
	137	* IOP3XX I/O and Mem space regions for PCI autoconfiguration
	138	*/
	139	#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
	140	#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
0cb015f9	141	#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
7ae1f7ec LB	142
	143	#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
	144	#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
	145	#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
0cb015f9	146	#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
7ae1f7ec LB	147
	148
	149	#ifndef __ASSEMBLY__
	150	void iop3xx_map_io(void);
48388b2a LB	151	void iop3xx_init_time(unsigned long);
48388b2a LB	152	unsigned long iop3xx_gettimeoffset(void);
e25d64f1 LB	153
	154	extern struct platform_device iop3xx_i2c0_device;
	155	extern struct platform_device iop3xx_i2c1_device;
0b29de4a LB	156
	157	extern inline void iop3xx_cp6_enable(void)
	158	{
	159	u32 temp;
	160
	161	asm volatile (
	162	"mrc p15, 0, %0, c15, c1, 0\n\t"
	163	"orr %0, %0, #(1 << 6)\n\t"
	164	"mcr p15, 0, %0, c15, c1, 0\n\t"
	165	"mrc p15, 0, %0, c15, c1, 0\n\t"
	166	"mov %0, %0\n\t"
	167	"sub pc, pc, #4\n\t"
	168	: "=r" (temp) );
	169	}
	170
	171	extern inline void iop3xx_cp6_disable(void)
	172	{
	173	u32 temp;
	174
	175	asm volatile (
	176	"mrc p15, 0, %0, c15, c1, 0\n\t"
	177	"bic %0, %0, #(1 << 6)\n\t"
	178	"mcr p15, 0, %0, c15, c1, 0\n\t"
	179	"mrc p15, 0, %0, c15, c1, 0\n\t"
	180	"mov %0, %0\n\t"
	181	"sub pc, pc, #4\n\t"
	182	: "=r" (temp) );
	183	}
7ae1f7ec LB	184	#endif
	185
	186
	187	#endif