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bc8c84c9 MF |
1 | /* |
2 | * File: include/asm-blackfin/mach-bf527/anomaly.h | |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
4 | * | |
4d555630 | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
bc8c84c9 MF |
6 | * Licensed under the GPL-2 or later. |
7 | */ | |
8 | ||
9 | /* This file shoule be up to date with: | |
4d555630 | 10 | * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List |
bc8c84c9 MF |
11 | */ |
12 | ||
13 | #ifndef _MACH_ANOMALY_H_ | |
14 | #define _MACH_ANOMALY_H_ | |
15 | ||
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | |
17 | #define ANOMALY_05000074 (1) | |
bc8c84c9 MF |
18 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
19 | #define ANOMALY_05000122 (1) | |
20 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
21 | #define ANOMALY_05000245 (1) | |
22 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
23 | #define ANOMALY_05000265 (1) | |
bc8c84c9 MF |
24 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
25 | #define ANOMALY_05000328 (1) | |
26 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | |
27 | #define ANOMALY_05000337 (1) | |
4d555630 SZ |
28 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
29 | #define ANOMALY_05000341 (1) | |
30 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ | |
bc8c84c9 | 31 | #define ANOMALY_05000342 (1) |
4d555630 SZ |
32 | /* USB Calibration Value Is Not Initialized */ |
33 | #define ANOMALY_05000346 (1) | |
34 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ | |
bc8c84c9 | 35 | #define ANOMALY_05000347 (1) |
4d555630 SZ |
36 | /* Security Features Are Not Functional */ |
37 | #define ANOMALY_05000348 (__SILICON_REVISION__ < 1) | |
38 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | |
39 | #define ANOMALY_05000355 (1) | |
40 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | |
41 | #define ANOMALY_05000357 (1) | |
42 | /* Incorrect Revision Number in DSPID Register */ | |
43 | #define ANOMALY_05000364 (__SILICON_REVISION__ > 0) | |
44 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | |
45 | #define ANOMALY_05000366 (1) | |
46 | /* New Feature: Higher Default CCLK Rate */ | |
47 | #define ANOMALY_05000368 (1) | |
48 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | |
49 | #define ANOMALY_05000371 (1) | |
50 | /* Authentication Fails To Initiate */ | |
51 | #define ANOMALY_05000376 (__SILICON_REVISION__ > 0) | |
52 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ | |
53 | #define ANOMALY_05000380 (1) | |
54 | /* USB Full-speed Mode not Fully Tested */ | |
55 | #define ANOMALY_05000381 (1) | |
56 | /* New Feature: Boot from OTP Memory */ | |
57 | #define ANOMALY_05000385 (1) | |
58 | /* New Feature: bfrom_SysControl() Routine */ | |
59 | #define ANOMALY_05000386 (1) | |
60 | /* New Feature: Programmable Preboot Settings */ | |
61 | #define ANOMALY_05000387 (1) | |
62 | /* Reset Vector Must Not Be in SDRAM Memory Space */ | |
63 | #define ANOMALY_05000389 (1) | |
64 | /* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ | |
65 | #define ANOMALY_05000392 (1) | |
66 | /* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ | |
67 | #define ANOMALY_05000393 (1) | |
68 | /* New Feature: Log Buffer Functionality */ | |
69 | #define ANOMALY_05000394 (1) | |
70 | /* New Feature: Hook Routine Functionality */ | |
71 | #define ANOMALY_05000395 (1) | |
72 | /* New Feature: Header Indirect Bit */ | |
73 | #define ANOMALY_05000396 (1) | |
74 | /* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ | |
75 | #define ANOMALY_05000397 (1) | |
76 | /* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ | |
77 | #define ANOMALY_05000398 (1) | |
78 | /* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ | |
79 | #define ANOMALY_05000399 (1) | |
80 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ | |
81 | #define ANOMALY_05000401 (1) | |
bc8c84c9 | 82 | |
2b39331a | 83 | /* Anomalies that don't exist on this proc */ |
59003145 MH |
84 | #define ANOMALY_05000125 (0) |
85 | #define ANOMALY_05000158 (0) | |
4d555630 SZ |
86 | #define ANOMALY_05000183 (0) |
87 | #define ANOMALY_05000198 (0) | |
88 | #define ANOMALY_05000230 (0) | |
89 | #define ANOMALY_05000244 (0) | |
90 | #define ANOMALY_05000261 (0) | |
59003145 | 91 | #define ANOMALY_05000263 (0) |
4d555630 SZ |
92 | #define ANOMALY_05000266 (0) |
93 | #define ANOMALY_05000273 (0) | |
59003145 | 94 | #define ANOMALY_05000311 (0) |
4d555630 SZ |
95 | #define ANOMALY_05000312 (0) |
96 | #define ANOMALY_05000323 (0) | |
97 | #define ANOMALY_05000363 (0) | |
98 | ||
bc8c84c9 | 99 | #endif |