[mirror_ubuntu-artful-kernel.git] / include / asm-blackfin / mach-bf527 / bfin_serial_5xx.h

#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>

#define NR_PORTS		2

#define OFFSET_THR              0x00	/* Transmit Holding register            */
#define OFFSET_RBR              0x00	/* Receive Buffer register              */
#define OFFSET_DLL              0x00	/* Divisor Latch (Low-Byte)             */
#define OFFSET_IER              0x04	/* Interrupt Enable Register            */
#define OFFSET_DLH              0x04	/* Divisor Latch (High-Byte)            */
#define OFFSET_IIR              0x08	/* Interrupt Identification Register    */
#define OFFSET_LCR              0x0C	/* Line Control Register                */
#define OFFSET_MCR              0x10	/* Modem Control Register               */
#define OFFSET_LSR              0x14	/* Line Status Register                 */
#define OFFSET_MSR              0x18	/* Modem Status Register                */
#define OFFSET_SCR              0x1C	/* SCR Scratch Register                 */
#define OFFSET_GCTL             0x24	/* Global Control Register              */

#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart)	bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
#define UART_GET_DLH(uart)	bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))

#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)

#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS

# ifndef CONFIG_UART0_CTS_PIN
#  define CONFIG_UART0_CTS_PIN -1
# endif

# ifndef CONFIG_UART0_RTS_PIN
#  define CONFIG_UART0_RTS_PIN -1
# endif

# ifndef CONFIG_UART1_CTS_PIN
#  define CONFIG_UART1_CTS_PIN -1
# endif

# ifndef CONFIG_UART1_RTS_PIN
#  define CONFIG_UART1_RTS_PIN -1
# endif
#endif
/*
 * The pin configuration is different from schematic
 */
struct bfin_serial_port {
	struct uart_port port;
	unsigned int old_status;
#ifdef CONFIG_SERIAL_BFIN_DMA
	int tx_done;
	int tx_count;
	struct circ_buf rx_dma_buf;
	struct timer_list rx_dma_timer;
	int rx_dma_nrows;
	unsigned int tx_dma_channel;
	unsigned int rx_dma_channel;
	struct work_struct tx_dma_workqueue;
#else
	struct work_struct cts_workqueue;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
	int cts_pin;
	int rts_pin;
#endif
};

struct bfin_serial_port bfin_serial_ports[NR_PORTS];
struct bfin_serial_res {
	unsigned long uart_base_addr;
	int uart_irq;
#ifdef CONFIG_SERIAL_BFIN_DMA
	unsigned int uart_tx_dma_channel;
	unsigned int uart_rx_dma_channel;
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
	int uart_cts_pin;
	int uart_rts_pin;
#endif
};

struct bfin_serial_res bfin_serial_resource[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
	{
	 0xFFC00400,
	 IRQ_UART0_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
	 CH_UART0_TX,
	 CH_UART0_RX,
#endif
#ifdef CONFIG_BFIN_UART0_CTSRTS
	 CONFIG_UART0_CTS_PIN,
	 CONFIG_UART0_RTS_PIN,
#endif
	 },
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
	{
	 0xFFC02000,
	 IRQ_UART1_RX,
#ifdef CONFIG_SERIAL_BFIN_DMA
	 CH_UART1_TX,
	 CH_UART1_RX,
#endif
#ifdef CONFIG_BFIN_UART1_CTSRTS
	 CONFIG_UART1_CTS_PIN,
	 CONFIG_UART1_RTS_PIN,
#endif
	 },
#endif
};

int nr_ports = ARRAY_SIZE(bfin_serial_resource);

#define DRIVER_NAME "bfin-uart"

static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{

#ifdef CONFIG_SERIAL_BFIN_UART0
	peripheral_request(P_UART0_TX, DRIVER_NAME);
	peripheral_request(P_UART0_RX, DRIVER_NAME);
#endif

#ifdef CONFIG_SERIAL_BFIN_UART1
	peripheral_request(P_UART1_TX, DRIVER_NAME);
	peripheral_request(P_UART1_RX, DRIVER_NAME);
#endif

#ifdef CONFIG_SERIAL_BFIN_CTSRTS
	if (uart->cts_pin >= 0) {
		gpio_request(uart->cts_pin, DRIVER_NAME);
		gpio_direction_input(uart->cts_pin);
	}

	if (uart->rts_pin >= 0) {
		gpio_request(uart->rts_pin, DRIVER_NAME);
		gpio_direction_output(uart->rts_pin, 0);
	}
#endif
}
Commit	Line	Data
59003145 MH	1	#include <linux/serial.h>
	2	#include <asm/dma.h>
	3	#include <asm/portmux.h>
	4
	5	#define NR_PORTS 2
	6
	7	#define OFFSET_THR 0x00 /* Transmit Holding register */
	8	#define OFFSET_RBR 0x00 /* Receive Buffer register */
	9	#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
	10	#define OFFSET_IER 0x04 /* Interrupt Enable Register */
	11	#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
	12	#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
	13	#define OFFSET_LCR 0x0C /* Line Control Register */
	14	#define OFFSET_MCR 0x10 /* Modem Control Register */
	15	#define OFFSET_LSR 0x14 /* Line Status Register */
	16	#define OFFSET_MSR 0x18 /* Modem Status Register */
	17	#define OFFSET_SCR 0x1C /* SCR Scratch Register */
	18	#define OFFSET_GCTL 0x24 /* Global Control Register */
	19
	20	#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
	21	#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
	22	#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
	23	#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
	24	#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
	25	#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
	26	#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
	27	#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
	28
	29	#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
	30	#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
	31	#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
	32	#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
	33	#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
	34	#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
	35
	36	#if defined(CONFIG_BFIN_UART0_CTSRTS) \|\| defined(CONFIG_BFIN_UART1_CTSRTS)
	37	# define CONFIG_SERIAL_BFIN_CTSRTS
	38
	39	# ifndef CONFIG_UART0_CTS_PIN
	40	# define CONFIG_UART0_CTS_PIN -1
	41	# endif
	42
	43	# ifndef CONFIG_UART0_RTS_PIN
	44	# define CONFIG_UART0_RTS_PIN -1
	45	# endif
	46
	47	# ifndef CONFIG_UART1_CTS_PIN
	48	# define CONFIG_UART1_CTS_PIN -1
	49	# endif
	50
	51	# ifndef CONFIG_UART1_RTS_PIN
	52	# define CONFIG_UART1_RTS_PIN -1
	53	# endif
	54	#endif
	55	/*
	56	* The pin configuration is different from schematic
	57	*/
	58	struct bfin_serial_port {
	59	struct uart_port port;
	60	unsigned int old_status;
	61	#ifdef CONFIG_SERIAL_BFIN_DMA
	62	int tx_done;
	63	int tx_count;
	64	struct circ_buf rx_dma_buf;
65	struct timer_list rx_dma_timer;
66	int rx_dma_nrows;
67	unsigned int tx_dma_channel;
68	unsigned int rx_dma_channel;
69	struct work_struct tx_dma_workqueue;
70	#else
71	struct work_struct cts_workqueue;
72	#endif
73	#ifdef CONFIG_SERIAL_BFIN_CTSRTS
74	int cts_pin;
75	int rts_pin;
76	#endif
77	};
78
79	struct bfin_serial_port bfin_serial_ports[NR_PORTS];
80	struct bfin_serial_res {
81	unsigned long uart_base_addr;
82	int uart_irq;
83	#ifdef CONFIG_SERIAL_BFIN_DMA
84	unsigned int uart_tx_dma_channel;
85	unsigned int uart_rx_dma_channel;
86	#endif
87	#ifdef CONFIG_SERIAL_BFIN_CTSRTS
88	int uart_cts_pin;
89	int uart_rts_pin;
90	#endif
91	};
92
93	struct bfin_serial_res bfin_serial_resource[] = {
94	#ifdef CONFIG_SERIAL_BFIN_UART0
95	{
96	0xFFC00400,
97	IRQ_UART0_RX,
98	#ifdef CONFIG_SERIAL_BFIN_DMA
99	CH_UART0_TX,
100	CH_UART0_RX,
101	#endif
102	#ifdef CONFIG_BFIN_UART0_CTSRTS
103	CONFIG_UART0_CTS_PIN,
104	CONFIG_UART0_RTS_PIN,
105	#endif
106	},
107	#endif
108	#ifdef CONFIG_SERIAL_BFIN_UART1
109	{
110	0xFFC02000,
111	IRQ_UART1_RX,
112	#ifdef CONFIG_SERIAL_BFIN_DMA
113	CH_UART1_TX,
114	CH_UART1_RX,
115	#endif
116	#ifdef CONFIG_BFIN_UART1_CTSRTS
117	CONFIG_UART1_CTS_PIN,
118	CONFIG_UART1_RTS_PIN,
119	#endif
120	},
121	#endif
122	};
123
124	int nr_ports = ARRAY_SIZE(bfin_serial_resource);
125
126	#define DRIVER_NAME "bfin-uart"
127
128	static void bfin_serial_hw_init(struct bfin_serial_port *uart)
129	{
130
131	#ifdef CONFIG_SERIAL_BFIN_UART0
132	peripheral_request(P_UART0_TX, DRIVER_NAME);
133	peripheral_request(P_UART0_RX, DRIVER_NAME);
134	#endif
135
136	#ifdef CONFIG_SERIAL_BFIN_UART1
137	peripheral_request(P_UART1_TX, DRIVER_NAME);
138	peripheral_request(P_UART1_RX, DRIVER_NAME);
139	#endif
140
141	#ifdef CONFIG_SERIAL_BFIN_CTSRTS
142	if (uart->cts_pin >= 0) {
143	gpio_request(uart->cts_pin, DRIVER_NAME);
144	gpio_direction_input(uart->cts_pin);
145	}
146
147	if (uart->rts_pin >= 0) {
148	gpio_request(uart->rts_pin, DRIVER_NAME);
acbcd263	149	gpio_direction_output(uart->rts_pin, 0);
59003145 MH	150	}
	151	#endif
	152	}