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1394f032 | 1 | /* |
287050fe MF |
2 | * File: include/asm-blackfin/mach-bf533/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
1394f032 | 4 | * |
287050fe MF |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | |
1394f032 BW |
7 | */ |
8 | ||
9 | /* This file shoule be up to date with: | |
1aafd909 MF |
10 | * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List |
11 | * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List | |
12 | * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List | |
1394f032 BW |
13 | */ |
14 | ||
15 | #ifndef _MACH_ANOMALY_H_ | |
16 | #define _MACH_ANOMALY_H_ | |
17 | ||
18 | /* We do not support 0.1 or 0.2 silicon - sorry */ | |
1aafd909 MF |
19 | #if __SILICON_REVISION__ < 3 |
20 | # error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 | |
1394f032 BW |
21 | #endif |
22 | ||
1aafd909 MF |
23 | #if defined(__ADSPBF531__) |
24 | # define ANOMALY_BF531 1 | |
25 | #else | |
26 | # define ANOMALY_BF531 0 | |
27 | #endif | |
28 | #if defined(__ADSPBF532__) | |
29 | # define ANOMALY_BF532 1 | |
30 | #else | |
31 | # define ANOMALY_BF532 0 | |
32 | #endif | |
33 | #if defined(__ADSPBF533__) | |
34 | # define ANOMALY_BF533 1 | |
35 | #else | |
36 | # define ANOMALY_BF533 0 | |
37 | #endif | |
1394f032 | 38 | |
1aafd909 MF |
39 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ |
40 | #define ANOMALY_05000074 (1) | |
41 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | |
42 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | |
43 | /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ | |
44 | #define ANOMALY_05000105 (1) | |
45 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
46 | #define ANOMALY_05000119 (1) | |
47 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
48 | #define ANOMALY_05000122 (1) | |
49 | /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ | |
50 | #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) | |
51 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | |
52 | #define ANOMALY_05000166 (1) | |
53 | /* Turning Serial Ports on with External Frame Syncs */ | |
54 | #define ANOMALY_05000167 (1) | |
55 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | |
56 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) | |
57 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | |
58 | #define ANOMALY_05000180 (1) | |
59 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ | |
60 | #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) | |
61 | /* False Protection Exceptions */ | |
62 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) | |
63 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | |
64 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) | |
65 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ | |
66 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) | |
67 | /* Failing MMR Accesses When Stalled by Preceding Memory Read */ | |
68 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) | |
69 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | |
70 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | |
71 | /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ | |
72 | #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) | |
73 | /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ | |
74 | #define ANOMALY_05000201 (__SILICON_REVISION__ < 4) | |
75 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ | |
76 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | |
77 | /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ | |
78 | #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) | |
79 | /* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ | |
80 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) | |
81 | /* Recovery from "Brown-Out" Condition */ | |
82 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) | |
83 | /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ | |
84 | #define ANOMALY_05000208 (1) | |
85 | /* Speed Path in Computational Unit Affects Certain Instructions */ | |
86 | #define ANOMALY_05000209 (__SILICON_REVISION__ < 4) | |
87 | /* UART TX Interrupt Masked Erroneously */ | |
88 | #define ANOMALY_05000215 (__SILICON_REVISION__ < 5) | |
89 | /* NMI Event at Boot Time Results in Unpredictable State */ | |
90 | #define ANOMALY_05000219 (1) | |
91 | /* Incorrect Pulse-Width of UART Start Bit */ | |
92 | #define ANOMALY_05000225 (__SILICON_REVISION__ < 5) | |
93 | /* Scratchpad Memory Bank Reads May Return Incorrect Data */ | |
94 | #define ANOMALY_05000227 (__SILICON_REVISION__ < 5) | |
95 | /* SPI Slave Boot Mode Modifies Registers from Reset Value */ | |
96 | #define ANOMALY_05000229 (1) | |
97 | /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ | |
98 | #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) | |
99 | /* UART STB Bit Incorrectly Affects Receiver Setting */ | |
100 | #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) | |
101 | /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ | |
102 | #define ANOMALY_05000233 (__SILICON_REVISION__ < 4) | |
103 | /* Incorrect Revision Number in DSPID Register */ | |
104 | #define ANOMALY_05000234 (__SILICON_REVISION__ == 4) | |
105 | /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ | |
106 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 4) | |
107 | /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ | |
108 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | |
109 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
110 | #define ANOMALY_05000245 (1) | |
111 | /* Data CPLBs Should Prevent Spurious Hardware Errors */ | |
112 | #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) | |
113 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | |
114 | #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) | |
115 | /* Maximum External Clock Speed for Timers */ | |
116 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 5) | |
117 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | |
118 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 4) | |
119 | /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ | |
120 | #define ANOMALY_05000255 (__SILICON_REVISION__ < 5) | |
121 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ | |
122 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 5) | |
123 | /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ | |
124 | #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) | |
125 | /* ICPLB_STATUS MMR Register May Be Corrupted */ | |
126 | #define ANOMALY_05000260 (__SILICON_REVISION__ < 5) | |
127 | /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ | |
128 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 5) | |
129 | /* Stores To Data Cache May Be Lost */ | |
130 | #define ANOMALY_05000262 (__SILICON_REVISION__ < 5) | |
131 | /* Hardware Loop Corrupted When Taking an ICPLB Exception */ | |
132 | #define ANOMALY_05000263 (__SILICON_REVISION__ < 5) | |
133 | /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ | |
134 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) | |
135 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | |
136 | #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) | |
137 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ | |
138 | #define ANOMALY_05000269 (__SILICON_REVISION__ < 5) | |
139 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | |
140 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 5) | |
141 | /* Spontaneous Reset of Internal Voltage Regulator */ | |
142 | #define ANOMALY_05000271 (__SILICON_REVISION__ < 4) | |
143 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
144 | #define ANOMALY_05000272 (1) | |
145 | /* Writes to Synchronous SDRAM Memory May Be Lost */ | |
146 | #define ANOMALY_05000273 (1) | |
147 | /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ | |
148 | #define ANOMALY_05000276 (1) | |
149 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ | |
150 | #define ANOMALY_05000277 (1) | |
151 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | |
152 | #define ANOMALY_05000278 (1) | |
153 | /* False Hardware Error Exception When ISR Context Is Not Restored */ | |
154 | #define ANOMALY_05000281 (1) | |
155 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | |
156 | #define ANOMALY_05000282 (1) | |
157 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | |
158 | #define ANOMALY_05000283 (1) | |
159 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | |
160 | #define ANOMALY_05000288 (1) | |
161 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | |
162 | #define ANOMALY_05000301 (1) | |
163 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | |
164 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) | |
165 | /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | |
166 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | |
167 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ | |
168 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) | |
169 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
170 | #define ANOMALY_05000310 (1) | |
171 | /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ | |
172 | #define ANOMALY_05000311 (1) | |
173 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
174 | #define ANOMALY_05000312 (1) | |
175 | /* PPI Is Level-Sensitive on First Transfer */ | |
176 | #define ANOMALY_05000313 (1) | |
177 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | |
178 | #define ANOMALY_05000315 (1) | |
179 | /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ | |
180 | #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) | |
1394f032 | 181 | |
1aafd909 MF |
182 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are |
183 | * here to show running on older silicon just isn't feasible. | |
184 | */ | |
1394f032 | 185 | |
1aafd909 MF |
186 | /* Watchpoints (Hardware Breakpoints) are not supported */ |
187 | #define ANOMALY_05000067 (__SILICON_REVISION__ < 3) | |
188 | /* Reserved bits in SYSCFG register not set at power on */ | |
189 | #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) | |
190 | /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ | |
191 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | |
192 | /* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ | |
193 | #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) | |
194 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | |
195 | #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) | |
196 | /* Erroneous exception when enabling cache */ | |
197 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) | |
198 | /* SPI clock polarity and phase bits incorrect during booting */ | |
199 | #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) | |
200 | /* DMEM_CONTROL is not set on Reset */ | |
201 | #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) | |
202 | /* SPI boot will not complete if there is a zero fill block in the loader file */ | |
203 | #define ANOMALY_05000138 (__SILICON_REVISION__ < 3) | |
204 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ | |
205 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | |
206 | /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ | |
207 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) | |
208 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | |
209 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | |
210 | /* A read from external memory may return a wrong value with data cache enabled */ | |
211 | #define ANOMALY_05000143 (__SILICON_REVISION__ < 3) | |
212 | /* DMA and TESTSET conflict when both are accessing external memory */ | |
213 | #define ANOMALY_05000144 (__SILICON_REVISION__ < 3) | |
214 | /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ | |
215 | #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) | |
216 | /* MDMA may lose the first few words of a descriptor chain */ | |
217 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | |
218 | /* The source MDMA descriptor may stop with a DMA Error */ | |
219 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) | |
220 | /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ | |
221 | #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) | |
222 | /* Frame Delay in SPORT Multichannel Mode */ | |
223 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) | |
224 | /* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ | |
225 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) | |
226 | /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ | |
227 | #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) | |
228 | /* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ | |
229 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) | |
230 | /* SPORT transmit data is not gated by external frame sync in certain conditions */ | |
231 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | |
232 | /* SDRAM auto-refresh and subsequent Power Ups */ | |
233 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) | |
234 | /* DATA CPLB page miss can result in lost write-through cache data writes */ | |
235 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) | |
236 | /* DMA vs Core accesses to external memory */ | |
237 | #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) | |
238 | /* Cache Fill Buffer Data lost */ | |
239 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) | |
240 | /* Overlapping Sequencer and Memory Stalls */ | |
241 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) | |
242 | /* Multiplication of (-1) by (-1) followed by an accumulator saturation */ | |
243 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) | |
244 | /* Disabling the PPI resets the PPI configuration registers */ | |
245 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) | |
246 | /* PPI TX Mode with 2 External Frame Syncs */ | |
247 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) | |
248 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ | |
249 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) | |
250 | /* In PPI Transmit Modes with External Frame Syncs POLC */ | |
251 | #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) | |
252 | /* Internal Voltage Regulator may not start up */ | |
253 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) | |
4bf3f3cb | 254 | |
1aafd909 MF |
255 | /* Anomalies that don't exist on this proc */ |
256 | #define ANOMALY_05000266 (0) | |
2b39331a | 257 | #define ANOMALY_05000323 (0) |
4bf3f3cb | 258 | |
1394f032 | 259 | #endif |