projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 58d08319 JN |
1 | #ifndef __marb_bar_defs_h |
| 2 | #define __marb_bar_defs_h | |
| 3 | ||
| 4 | /* | |
| 5 | * This file is autogenerated from | |
| 6 | * file: marb_bar.r | |
| 7 | * | |
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r | |
| 9 | * Any changes here will be lost. | |
| 10 | * | |
| 11 | * -*- buffer-read-only: t -*- | |
| 12 | */ | |
| 13 | /* Main access macros */ | |
| 14 | #ifndef REG_RD | |
| 15 | #define REG_RD( scope, inst, reg ) \ | |
| 16 | REG_READ( reg_##scope##_##reg, \ | |
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 18 | #endif | |
| 19 | ||
| 20 | #ifndef REG_WR | |
| 21 | #define REG_WR( scope, inst, reg, val ) \ | |
| 22 | REG_WRITE( reg_##scope##_##reg, \ | |
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
| 24 | #endif | |
| 25 | ||
| 26 | #ifndef REG_RD_VECT | |
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
| 28 | REG_READ( reg_##scope##_##reg, \ | |
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 30 | (index) * STRIDE_##scope##_##reg ) | |
| 31 | #endif | |
| 32 | ||
| 33 | #ifndef REG_WR_VECT | |
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
| 35 | REG_WRITE( reg_##scope##_##reg, \ | |
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | |
| 38 | #endif | |
| 39 | ||
| 40 | #ifndef REG_RD_INT | |
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | |
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 43 | #endif | |
| 44 | ||
| 45 | #ifndef REG_WR_INT | |
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
| 48 | #endif | |
| 49 | ||
| 50 | #ifndef REG_RD_INT_VECT | |
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 53 | (index) * STRIDE_##scope##_##reg ) | |
| 54 | #endif | |
| 55 | ||
| 56 | #ifndef REG_WR_INT_VECT | |
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | |
| 60 | #endif | |
| 61 | ||
| 62 | #ifndef REG_TYPE_CONV | |
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
| 65 | #endif | |
| 66 | ||
| 67 | #ifndef reg_page_size | |
| 68 | #define reg_page_size 8192 | |
| 69 | #endif | |
| 70 | ||
| 71 | #ifndef REG_ADDR | |
| 72 | #define REG_ADDR( scope, inst, reg ) \ | |
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 74 | #endif | |
| 75 | ||
| 76 | #ifndef REG_ADDR_VECT | |
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 79 | (index) * STRIDE_##scope##_##reg ) | |
| 80 | #endif | |
| 81 | ||
| 82 | /* C-code for register scope marb_bar */ | |
| 83 | ||
| 84 | #define STRIDE_marb_bar_rw_ddr2_slots 4 | |
| 85 | /* Register rw_ddr2_slots, scope marb_bar, type rw */ | |
| 86 | typedef struct { | |
| 87 | unsigned int owner : 4; | |
| 88 | unsigned int dummy1 : 28; | |
| 89 | } reg_marb_bar_rw_ddr2_slots; | |
| 90 | #define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 | |
| 91 | #define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 | |
| 92 | ||
| 93 | /* Register rw_h264_rd_burst, scope marb_bar, type rw */ | |
| 94 | typedef struct { | |
| 95 | unsigned int ddr2_bsize : 2; | |
| 96 | unsigned int dummy1 : 30; | |
| 97 | } reg_marb_bar_rw_h264_rd_burst; | |
| 98 | #define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 | |
| 99 | #define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 | |
| 100 | ||
| 101 | /* Register rw_h264_wr_burst, scope marb_bar, type rw */ | |
| 102 | typedef struct { | |
| 103 | unsigned int ddr2_bsize : 2; | |
| 104 | unsigned int dummy1 : 30; | |
| 105 | } reg_marb_bar_rw_h264_wr_burst; | |
| 106 | #define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 | |
| 107 | #define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 | |
| 108 | ||
| 109 | /* Register rw_ccd_burst, scope marb_bar, type rw */ | |
| 110 | typedef struct { | |
| 111 | unsigned int ddr2_bsize : 2; | |
| 112 | unsigned int dummy1 : 30; | |
| 113 | } reg_marb_bar_rw_ccd_burst; | |
| 114 | #define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 | |
| 115 | #define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 | |
| 116 | ||
| 117 | /* Register rw_vin_wr_burst, scope marb_bar, type rw */ | |
| 118 | typedef struct { | |
| 119 | unsigned int ddr2_bsize : 2; | |
| 120 | unsigned int dummy1 : 30; | |
| 121 | } reg_marb_bar_rw_vin_wr_burst; | |
| 122 | #define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 | |
| 123 | #define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 | |
| 124 | ||
| 125 | /* Register rw_vin_rd_burst, scope marb_bar, type rw */ | |
| 126 | typedef struct { | |
| 127 | unsigned int ddr2_bsize : 2; | |
| 128 | unsigned int dummy1 : 30; | |
| 129 | } reg_marb_bar_rw_vin_rd_burst; | |
| 130 | #define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 | |
| 131 | #define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 | |
| 132 | ||
| 133 | /* Register rw_sclr_rd_burst, scope marb_bar, type rw */ | |
| 134 | typedef struct { | |
| 135 | unsigned int ddr2_bsize : 2; | |
| 136 | unsigned int dummy1 : 30; | |
| 137 | } reg_marb_bar_rw_sclr_rd_burst; | |
| 138 | #define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 | |
| 139 | #define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 | |
| 140 | ||
| 141 | /* Register rw_vout_burst, scope marb_bar, type rw */ | |
| 142 | typedef struct { | |
| 143 | unsigned int ddr2_bsize : 2; | |
| 144 | unsigned int dummy1 : 30; | |
| 145 | } reg_marb_bar_rw_vout_burst; | |
| 146 | #define REG_RD_ADDR_marb_bar_rw_vout_burst 280 | |
| 147 | #define REG_WR_ADDR_marb_bar_rw_vout_burst 280 | |
| 148 | ||
| 149 | /* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ | |
| 150 | typedef struct { | |
| 151 | unsigned int ddr2_bsize : 2; | |
| 152 | unsigned int dummy1 : 30; | |
| 153 | } reg_marb_bar_rw_sclr_fifo_burst; | |
| 154 | #define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 | |
| 155 | #define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 | |
| 156 | ||
| 157 | /* Register rw_l2cache_burst, scope marb_bar, type rw */ | |
| 158 | typedef struct { | |
| 159 | unsigned int ddr2_bsize : 2; | |
| 160 | unsigned int dummy1 : 30; | |
| 161 | } reg_marb_bar_rw_l2cache_burst; | |
| 162 | #define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 | |
| 163 | #define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 | |
| 164 | ||
| 165 | /* Register rw_intr_mask, scope marb_bar, type rw */ | |
| 166 | typedef struct { | |
| 167 | unsigned int bp0 : 1; | |
| 168 | unsigned int bp1 : 1; | |
| 169 | unsigned int bp2 : 1; | |
| 170 | unsigned int bp3 : 1; | |
| 171 | unsigned int dummy1 : 28; | |
| 172 | } reg_marb_bar_rw_intr_mask; | |
| 173 | #define REG_RD_ADDR_marb_bar_rw_intr_mask 292 | |
| 174 | #define REG_WR_ADDR_marb_bar_rw_intr_mask 292 | |
| 175 | ||
| 176 | /* Register rw_ack_intr, scope marb_bar, type rw */ | |
| 177 | typedef struct { | |
| 178 | unsigned int bp0 : 1; | |
| 179 | unsigned int bp1 : 1; | |
| 180 | unsigned int bp2 : 1; | |
| 181 | unsigned int bp3 : 1; | |
| 182 | unsigned int dummy1 : 28; | |
| 183 | } reg_marb_bar_rw_ack_intr; | |
| 184 | #define REG_RD_ADDR_marb_bar_rw_ack_intr 296 | |
| 185 | #define REG_WR_ADDR_marb_bar_rw_ack_intr 296 | |
| 186 | ||
| 187 | /* Register r_intr, scope marb_bar, type r */ | |
| 188 | typedef struct { | |
| 189 | unsigned int bp0 : 1; | |
| 190 | unsigned int bp1 : 1; | |
| 191 | unsigned int bp2 : 1; | |
| 192 | unsigned int bp3 : 1; | |
| 193 | unsigned int dummy1 : 28; | |
| 194 | } reg_marb_bar_r_intr; | |
| 195 | #define REG_RD_ADDR_marb_bar_r_intr 300 | |
| 196 | ||
| 197 | /* Register r_masked_intr, scope marb_bar, type r */ | |
| 198 | typedef struct { | |
| 199 | unsigned int bp0 : 1; | |
| 200 | unsigned int bp1 : 1; | |
| 201 | unsigned int bp2 : 1; | |
| 202 | unsigned int bp3 : 1; | |
| 203 | unsigned int dummy1 : 28; | |
| 204 | } reg_marb_bar_r_masked_intr; | |
| 205 | #define REG_RD_ADDR_marb_bar_r_masked_intr 304 | |
| 206 | ||
| 207 | /* Register rw_stop_mask, scope marb_bar, type rw */ | |
| 208 | typedef struct { | |
| 209 | unsigned int h264_rd : 1; | |
| 210 | unsigned int h264_wr : 1; | |
| 211 | unsigned int ccd : 1; | |
| 212 | unsigned int vin_wr : 1; | |
| 213 | unsigned int vin_rd : 1; | |
| 214 | unsigned int sclr_rd : 1; | |
| 215 | unsigned int vout : 1; | |
| 216 | unsigned int sclr_fifo : 1; | |
| 217 | unsigned int l2cache : 1; | |
| 218 | unsigned int dummy1 : 23; | |
| 219 | } reg_marb_bar_rw_stop_mask; | |
| 220 | #define REG_RD_ADDR_marb_bar_rw_stop_mask 308 | |
| 221 | #define REG_WR_ADDR_marb_bar_rw_stop_mask 308 | |
| 222 | ||
| 223 | /* Register r_stopped, scope marb_bar, type r */ | |
| 224 | typedef struct { | |
| 225 | unsigned int h264_rd : 1; | |
| 226 | unsigned int h264_wr : 1; | |
| 227 | unsigned int ccd : 1; | |
| 228 | unsigned int vin_wr : 1; | |
| 229 | unsigned int vin_rd : 1; | |
| 230 | unsigned int sclr_rd : 1; | |
| 231 | unsigned int vout : 1; | |
| 232 | unsigned int sclr_fifo : 1; | |
| 233 | unsigned int l2cache : 1; | |
| 234 | unsigned int dummy1 : 23; | |
| 235 | } reg_marb_bar_r_stopped; | |
| 236 | #define REG_RD_ADDR_marb_bar_r_stopped 312 | |
| 237 | ||
| 238 | /* Register rw_no_snoop, scope marb_bar, type rw */ | |
| 239 | typedef struct { | |
| 240 | unsigned int h264_rd : 1; | |
| 241 | unsigned int h264_wr : 1; | |
| 242 | unsigned int ccd : 1; | |
| 243 | unsigned int vin_wr : 1; | |
| 244 | unsigned int vin_rd : 1; | |
| 245 | unsigned int sclr_rd : 1; | |
| 246 | unsigned int vout : 1; | |
| 247 | unsigned int sclr_fifo : 1; | |
| 248 | unsigned int l2cache : 1; | |
| 249 | unsigned int dummy1 : 23; | |
| 250 | } reg_marb_bar_rw_no_snoop; | |
| 251 | #define REG_RD_ADDR_marb_bar_rw_no_snoop 576 | |
| 252 | #define REG_WR_ADDR_marb_bar_rw_no_snoop 576 | |
| 253 | ||
| 254 | ||
| 255 | /* Constants */ | |
| 256 | enum { | |
| 257 | regk_marb_bar_ccd = 0x00000002, | |
| 258 | regk_marb_bar_h264_rd = 0x00000000, | |
| 259 | regk_marb_bar_h264_wr = 0x00000001, | |
| 260 | regk_marb_bar_l2cache = 0x00000008, | |
| 261 | regk_marb_bar_no = 0x00000000, | |
| 262 | regk_marb_bar_r_stopped_default = 0x00000000, | |
| 263 | regk_marb_bar_rw_ccd_burst_default = 0x00000000, | |
| 264 | regk_marb_bar_rw_ddr2_slots_default = 0x00000000, | |
| 265 | regk_marb_bar_rw_ddr2_slots_size = 0x00000040, | |
| 266 | regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, | |
| 267 | regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, | |
| 268 | regk_marb_bar_rw_intr_mask_default = 0x00000000, | |
| 269 | regk_marb_bar_rw_l2cache_burst_default = 0x00000000, | |
| 270 | regk_marb_bar_rw_no_snoop_default = 0x00000000, | |
| 271 | regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, | |
| 272 | regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, | |
| 273 | regk_marb_bar_rw_stop_mask_default = 0x00000000, | |
| 274 | regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, | |
| 275 | regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, | |
| 276 | regk_marb_bar_rw_vout_burst_default = 0x00000000, | |
| 277 | regk_marb_bar_sclr_fifo = 0x00000007, | |
| 278 | regk_marb_bar_sclr_rd = 0x00000005, | |
| 279 | regk_marb_bar_vin_rd = 0x00000004, | |
| 280 | regk_marb_bar_vin_wr = 0x00000003, | |
| 281 | regk_marb_bar_vout = 0x00000006, | |
| 282 | regk_marb_bar_yes = 0x00000001 | |
| 283 | }; | |
| 284 | #endif /* __marb_bar_defs_h */ | |
| 285 | #ifndef __marb_bar_bp_defs_h | |
| 286 | #define __marb_bar_bp_defs_h | |
| 287 | ||
| 288 | /* | |
| 289 | * This file is autogenerated from | |
| 290 | * file: marb_bar.r | |
| 291 | * | |
| 292 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r | |
| 293 | * Any changes here will be lost. | |
| 294 | * | |
| 295 | * -*- buffer-read-only: t -*- | |
| 296 | */ | |
| 297 | /* Main access macros */ | |
| 298 | #ifndef REG_RD | |
| 299 | #define REG_RD( scope, inst, reg ) \ | |
| 300 | REG_READ( reg_##scope##_##reg, \ | |
| 301 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 302 | #endif | |
| 303 | ||
| 304 | #ifndef REG_WR | |
| 305 | #define REG_WR( scope, inst, reg, val ) \ | |
| 306 | REG_WRITE( reg_##scope##_##reg, \ | |
| 307 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
| 308 | #endif | |
| 309 | ||
| 310 | #ifndef REG_RD_VECT | |
| 311 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
| 312 | REG_READ( reg_##scope##_##reg, \ | |
| 313 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 314 | (index) * STRIDE_##scope##_##reg ) | |
| 315 | #endif | |
| 316 | ||
| 317 | #ifndef REG_WR_VECT | |
| 318 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
| 319 | REG_WRITE( reg_##scope##_##reg, \ | |
| 320 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
| 321 | (index) * STRIDE_##scope##_##reg, (val) ) | |
| 322 | #endif | |
| 323 | ||
| 324 | #ifndef REG_RD_INT | |
| 325 | #define REG_RD_INT( scope, inst, reg ) \ | |
| 326 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 327 | #endif | |
| 328 | ||
| 329 | #ifndef REG_WR_INT | |
| 330 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
| 331 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
| 332 | #endif | |
| 333 | ||
| 334 | #ifndef REG_RD_INT_VECT | |
| 335 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
| 336 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 337 | (index) * STRIDE_##scope##_##reg ) | |
| 338 | #endif | |
| 339 | ||
| 340 | #ifndef REG_WR_INT_VECT | |
| 341 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
| 342 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
| 343 | (index) * STRIDE_##scope##_##reg, (val) ) | |
| 344 | #endif | |
| 345 | ||
| 346 | #ifndef REG_TYPE_CONV | |
| 347 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
| 348 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
| 349 | #endif | |
| 350 | ||
| 351 | #ifndef reg_page_size | |
| 352 | #define reg_page_size 8192 | |
| 353 | #endif | |
| 354 | ||
| 355 | #ifndef REG_ADDR | |
| 356 | #define REG_ADDR( scope, inst, reg ) \ | |
| 357 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 358 | #endif | |
| 359 | ||
| 360 | #ifndef REG_ADDR_VECT | |
| 361 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
| 362 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 363 | (index) * STRIDE_##scope##_##reg ) | |
| 364 | #endif | |
| 365 | ||
| 366 | /* C-code for register scope marb_bar_bp */ | |
| 367 | ||
| 368 | /* Register rw_first_addr, scope marb_bar_bp, type rw */ | |
| 369 | typedef unsigned int reg_marb_bar_bp_rw_first_addr; | |
| 370 | #define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 | |
| 371 | #define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 | |
| 372 | ||
| 373 | /* Register rw_last_addr, scope marb_bar_bp, type rw */ | |
| 374 | typedef unsigned int reg_marb_bar_bp_rw_last_addr; | |
| 375 | #define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 | |
| 376 | #define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 | |
| 377 | ||
| 378 | /* Register rw_op, scope marb_bar_bp, type rw */ | |
| 379 | typedef struct { | |
| 380 | unsigned int rd : 1; | |
| 381 | unsigned int wr : 1; | |
| 382 | unsigned int rd_excl : 1; | |
| 383 | unsigned int pri_wr : 1; | |
| 384 | unsigned int us_rd : 1; | |
| 385 | unsigned int us_wr : 1; | |
| 386 | unsigned int us_rd_excl : 1; | |
| 387 | unsigned int us_pri_wr : 1; | |
| 388 | unsigned int dummy1 : 24; | |
| 389 | } reg_marb_bar_bp_rw_op; | |
| 390 | #define REG_RD_ADDR_marb_bar_bp_rw_op 8 | |
| 391 | #define REG_WR_ADDR_marb_bar_bp_rw_op 8 | |
| 392 | ||
| 393 | /* Register rw_clients, scope marb_bar_bp, type rw */ | |
| 394 | typedef struct { | |
| 395 | unsigned int h264_rd : 1; | |
| 396 | unsigned int h264_wr : 1; | |
| 397 | unsigned int ccd : 1; | |
| 398 | unsigned int vin_wr : 1; | |
| 399 | unsigned int vin_rd : 1; | |
| 400 | unsigned int sclr_rd : 1; | |
| 401 | unsigned int vout : 1; | |
| 402 | unsigned int sclr_fifo : 1; | |
| 403 | unsigned int l2cache : 1; | |
| 404 | unsigned int dummy1 : 23; | |
| 405 | } reg_marb_bar_bp_rw_clients; | |
| 406 | #define REG_RD_ADDR_marb_bar_bp_rw_clients 12 | |
| 407 | #define REG_WR_ADDR_marb_bar_bp_rw_clients 12 | |
| 408 | ||
| 409 | /* Register rw_options, scope marb_bar_bp, type rw */ | |
| 410 | typedef struct { | |
| 411 | unsigned int wrap : 1; | |
| 412 | unsigned int dummy1 : 31; | |
| 413 | } reg_marb_bar_bp_rw_options; | |
| 414 | #define REG_RD_ADDR_marb_bar_bp_rw_options 16 | |
| 415 | #define REG_WR_ADDR_marb_bar_bp_rw_options 16 | |
| 416 | ||
| 417 | /* Register r_brk_addr, scope marb_bar_bp, type r */ | |
| 418 | typedef unsigned int reg_marb_bar_bp_r_brk_addr; | |
| 419 | #define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 | |
| 420 | ||
| 421 | /* Register r_brk_op, scope marb_bar_bp, type r */ | |
| 422 | typedef struct { | |
| 423 | unsigned int rd : 1; | |
| 424 | unsigned int wr : 1; | |
| 425 | unsigned int rd_excl : 1; | |
| 426 | unsigned int pri_wr : 1; | |
| 427 | unsigned int us_rd : 1; | |
| 428 | unsigned int us_wr : 1; | |
| 429 | unsigned int us_rd_excl : 1; | |
| 430 | unsigned int us_pri_wr : 1; | |
| 431 | unsigned int dummy1 : 24; | |
| 432 | } reg_marb_bar_bp_r_brk_op; | |
| 433 | #define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 | |
| 434 | ||
| 435 | /* Register r_brk_clients, scope marb_bar_bp, type r */ | |
| 436 | typedef struct { | |
| 437 | unsigned int h264_rd : 1; | |
| 438 | unsigned int h264_wr : 1; | |
| 439 | unsigned int ccd : 1; | |
| 440 | unsigned int vin_wr : 1; | |
| 441 | unsigned int vin_rd : 1; | |
| 442 | unsigned int sclr_rd : 1; | |
| 443 | unsigned int vout : 1; | |
| 444 | unsigned int sclr_fifo : 1; | |
| 445 | unsigned int l2cache : 1; | |
| 446 | unsigned int dummy1 : 23; | |
| 447 | } reg_marb_bar_bp_r_brk_clients; | |
| 448 | #define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 | |
| 449 | ||
| 450 | /* Register r_brk_first_client, scope marb_bar_bp, type r */ | |
| 451 | typedef struct { | |
| 452 | unsigned int h264_rd : 1; | |
| 453 | unsigned int h264_wr : 1; | |
| 454 | unsigned int ccd : 1; | |
| 455 | unsigned int vin_wr : 1; | |
| 456 | unsigned int vin_rd : 1; | |
| 457 | unsigned int sclr_rd : 1; | |
| 458 | unsigned int vout : 1; | |
| 459 | unsigned int sclr_fifo : 1; | |
| 460 | unsigned int l2cache : 1; | |
| 461 | unsigned int dummy1 : 23; | |
| 462 | } reg_marb_bar_bp_r_brk_first_client; | |
| 463 | #define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 | |
| 464 | ||
| 465 | /* Register r_brk_size, scope marb_bar_bp, type r */ | |
| 466 | typedef unsigned int reg_marb_bar_bp_r_brk_size; | |
| 467 | #define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 | |
| 468 | ||
| 469 | /* Register rw_ack, scope marb_bar_bp, type rw */ | |
| 470 | typedef unsigned int reg_marb_bar_bp_rw_ack; | |
| 471 | #define REG_RD_ADDR_marb_bar_bp_rw_ack 40 | |
| 472 | #define REG_WR_ADDR_marb_bar_bp_rw_ack 40 | |
| 473 | ||
| 474 | ||
| 475 | /* Constants */ | |
| 476 | enum { | |
| 477 | regk_marb_bar_bp_no = 0x00000000, | |
| 478 | regk_marb_bar_bp_rw_op_default = 0x00000000, | |
| 479 | regk_marb_bar_bp_rw_options_default = 0x00000000, | |
| 480 | regk_marb_bar_bp_yes = 0x00000001 | |
| 481 | }; | |
| 482 | #endif /* __marb_bar_bp_defs_h */ |