[mirror_ubuntu-artful-kernel.git] / include / asm-cris / etraxgpio.h

/*
 * The following devices are accessable using this driver using
 * GPIO_MAJOR (120) and a couple of minor numbers.
 *
 * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
 * /dev/gpioa  minor 0, 8 bit GPIO, each bit can change direction
 * /dev/gpiob  minor 1, 8 bit GPIO, each bit can change direction
 * /dev/leds   minor 2, Access to leds depending on kernelconfig
 * /dev/gpiog  minor 3
 *       g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
 *       g1-g7 and g25-g31 is both input and outputs but on different pins
 *       Also note that some bits change pins depending on what interfaces
 *       are enabled.
 *
 * For ETRAX FS (CONFIG_ETRAXFS):
 * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
 * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
 * /dev/gpioc  minor 3, 18 bit GPIO, each bit can change direction
 * /dev/gpiod  minor 4, 18 bit GPIO, each bit can change direction
 * /dev/gpioe  minor 5, 18 bit GPIO, each bit can change direction
 * /dev/leds   minor 2, Access to leds depending on kernelconfig
 *
 * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
 * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
 * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
 * /dev/gpioc  minor 3, 18 bit GPIO, each bit can change direction
 * /dev/gpiod  minor 4, 18 bit GPIO, each bit can change direction
 * /dev/leds   minor 2, Access to leds depending on kernelconfig
 * /dev/pwm0   minor 16, PWM channel 0 on PA30
 * /dev/pwm1   minor 17, PWM channel 1 on PA31
 * /dev/pwm2   minor 18, PWM channel 2 on PB26
 *
 */
#ifndef _ASM_ETRAXGPIO_H
#define _ASM_ETRAXGPIO_H

/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
#ifdef CONFIG_ETRAX_ARCH_V10
#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_G 3
#define GPIO_MINOR_LAST 3
#endif

#ifdef CONFIG_ETRAXFS
#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_C 3
#define GPIO_MINOR_D 4
#define GPIO_MINOR_E 5
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#define GPIO_MINOR_V 6
#define GPIO_MINOR_LAST 6
#else
#define GPIO_MINOR_LAST 5
#endif
#endif

#ifdef CONFIG_CRIS_MACH_ARTPEC3
#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_C 3
#define GPIO_MINOR_D 4
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#define GPIO_MINOR_V 6
#define GPIO_MINOR_LAST 6
#else
#define GPIO_MINOR_LAST 4
#endif
#define GPIO_MINOR_PWM0 16
#define GPIO_MINOR_PWM1 17
#define GPIO_MINOR_PWM2 18
#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
#endif

/* supported ioctl _IOC_NR's */

#define IO_READBITS  0x1  /* read and return current port bits (obsolete) */
#define IO_SETBITS   0x2  /* set the bits marked by 1 in the argument */
#define IO_CLRBITS   0x3  /* clear the bits marked by 1 in the argument */

/* the alarm is waited for by select() */

#define IO_HIGHALARM 0x4  /* set alarm on high for bits marked by 1 */
#define IO_LOWALARM  0x5  /* set alarm on low for bits marked by 1 */
#define IO_CLRALARM  0x6  /* clear alarm for bits marked by 1 */

/* LED ioctl */
#define IO_LEDACTIVE_SET 0x7 /* set active led
                              * 0=off, 1=green, 2=red, 3=yellow */

/* GPIO direction ioctl's */
#define IO_READDIR    0x8  /* Read direction 0=input 1=output  (obsolete) */
#define IO_SETINPUT   0x9  /* Set direction for bits set, 0=unchanged 1=input,
                              returns mask with current inputs (obsolete) */
#define IO_SETOUTPUT  0xA  /* Set direction for bits set, 0=unchanged 1=output,
                              returns mask with current outputs (obsolete)*/

/* LED ioctl extended */
#define IO_LED_SETBIT 0xB
#define IO_LED_CLRBIT 0xC

/* SHUTDOWN ioctl */
#define IO_SHUTDOWN   0xD
#define IO_GET_PWR_BT 0xE

/* Bit toggling in driver settings */
/* bit set in low byte0 is CLK mask (0x00FF),
   bit set in byte1 is DATA mask    (0xFF00)
   msb, data_mask[7:0] , clk_mask[7:0]
 */
#define IO_CFG_WRITE_MODE 0xF
#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
	( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )

/* The following 4 ioctl's take a pointer as argument and handles
 * 32 bit ports (port G) properly.
 * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
 */
#define IO_READ_INBITS   0x10 /* *arg is result of reading the input pins */
#define IO_READ_OUTBITS  0x11 /* *arg is result of reading the output shadow */
#define IO_SETGET_INPUT  0x12 /* bits set in *arg is set to input,
                               * *arg updated with current input pins.
                               */
#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
                               * *arg updated with current output pins.
                               */

/* The following ioctl's are applicable to the PWM channels only */

#define IO_PWM_SET_MODE     0x20

enum io_pwm_mode {
	PWM_OFF = 0,		/* disabled, deallocated */
	PWM_STANDARD = 1,	/* 390 kHz, duty cycle 0..255/256 */
	PWM_FAST = 2,		/* variable freq, w/ 10ns active pulse len */
	PWM_VARFREQ = 3		/* individually configurable high/low periods */
};

struct io_pwm_set_mode {
	enum io_pwm_mode mode;
};

/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
 * from 10ns (value = 0) to 81920ns (value = 8191)
 * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
 * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
 * cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
 */
#define IO_PWM_SET_PERIOD   0x21

struct io_pwm_set_period {
	int lo;		/* 0..8191 */
	int hi;		/* 0..8191 */
};

/* Only for modes PWM_STANDARD and PWM_FAST.
 * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
 * 0 (value = 0) to 255/256 (value = 255).
 * For PWM_FAST, set duty cycle of PWM output signal from
 * 0% (value = 0) to 100% (value = 255). Output signal in this mode
 * is a 10ns pulse surrounded by a high or low level depending on duty
 * cycle (except for 0% and 100% which result in a constant output).
 * Resulting output frequency varies from 50 MHz at 50% duty cycle,
 * down to 390 kHz at min/max duty cycle.
 */
#define IO_PWM_SET_DUTY     0x22

struct io_pwm_set_duty {
	int duty;		/* 0..255 */
};

#endif
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* The following devices are accessable using this driver using
46aac058 JN	3	* GPIO_MAJOR (120) and a couple of minor numbers.
	4	*
	5	* For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
1da177e4 LT	6	* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
	7	* /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
	8	* /dev/leds minor 2, Access to leds depending on kernelconfig
	9	* /dev/gpiog minor 3
46aac058 JN	10	* g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
	11	* g1-g7 and g25-g31 is both input and outputs but on different pins
	12	* Also note that some bits change pins depending on what interfaces
	13	* are enabled.
1da177e4	14	*
46aac058 JN	15	* For ETRAX FS (CONFIG_ETRAXFS):
	16	* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
	17	* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
	18	* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
	19	* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
	20	* /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
	21	* /dev/leds minor 2, Access to leds depending on kernelconfig
1da177e4	22	*
46aac058	23	* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
1da177e4 LT	24	* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
1da177e4 LT	25	* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
46aac058 JN	26	* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
	27	* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
	28	* /dev/leds minor 2, Access to leds depending on kernelconfig
	29	* /dev/pwm0 minor 16, PWM channel 0 on PA30
	30	* /dev/pwm1 minor 17, PWM channel 1 on PA31
	31	* /dev/pwm2 minor 18, PWM channel 2 on PB26
1da177e4 LT	32	*
	33	*/
	34	#ifndef _ASM_ETRAXGPIO_H
	35	#define _ASM_ETRAXGPIO_H
	36
1da177e4 LT	37	/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
	38	#ifdef CONFIG_ETRAX_ARCH_V10
	39	#define ETRAXGPIO_IOCTYPE 43
	40	#define GPIO_MINOR_A 0
	41	#define GPIO_MINOR_B 1
	42	#define GPIO_MINOR_LEDS 2
	43	#define GPIO_MINOR_G 3
	44	#define GPIO_MINOR_LAST 3
	45	#endif
46aac058 JN	46
46aac058 JN	47	#ifdef CONFIG_ETRAXFS
1da177e4 LT	48	#define ETRAXGPIO_IOCTYPE 43
	49	#define GPIO_MINOR_A 0
	50	#define GPIO_MINOR_B 1
cb09f540 MS	51	#define GPIO_MINOR_LEDS 2
	52	#define GPIO_MINOR_C 3
	53	#define GPIO_MINOR_D 4
	54	#define GPIO_MINOR_E 5
46aac058 JN	55	#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
	56	#define GPIO_MINOR_V 6
	57	#define GPIO_MINOR_LAST 6
	58	#else
1da177e4 LT	59	#define GPIO_MINOR_LAST 5
1da177e4 LT	60	#endif
46aac058 JN	61	#endif
	62
	63	#ifdef CONFIG_CRIS_MACH_ARTPEC3
	64	#define ETRAXGPIO_IOCTYPE 43
	65	#define GPIO_MINOR_A 0
	66	#define GPIO_MINOR_B 1
	67	#define GPIO_MINOR_LEDS 2
	68	#define GPIO_MINOR_C 3
	69	#define GPIO_MINOR_D 4
	70	#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
	71	#define GPIO_MINOR_V 6
	72	#define GPIO_MINOR_LAST 6
	73	#else
	74	#define GPIO_MINOR_LAST 4
	75	#endif
	76	#define GPIO_MINOR_PWM0 16
	77	#define GPIO_MINOR_PWM1 17
	78	#define GPIO_MINOR_PWM2 18
	79	#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
	80	#endif
1da177e4 LT	81
	82	/* supported ioctl _IOC_NR's */
	83
	84	#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
	85	#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */
	86	#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */
	87
	88	/* the alarm is waited for by select() */
	89
	90	#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */
	91	#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */
	92	#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */
	93
	94	/* LED ioctl */
	95	#define IO_LEDACTIVE_SET 0x7 /* set active led
	96	* 0=off, 1=green, 2=red, 3=yellow */
	97
	98	/* GPIO direction ioctl's */
	99	#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */
46aac058	100	#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
1da177e4 LT	101	returns mask with current inputs (obsolete) */
	102	#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output,
	103	returns mask with current outputs (obsolete)*/
	104
	105	/* LED ioctl extended */
	106	#define IO_LED_SETBIT 0xB
	107	#define IO_LED_CLRBIT 0xC
	108
	109	/* SHUTDOWN ioctl */
	110	#define IO_SHUTDOWN 0xD
	111	#define IO_GET_PWR_BT 0xE
	112
	113	/* Bit toggling in driver settings */
46aac058 JN	114	/* bit set in low byte0 is CLK mask (0x00FF),
46aac058 JN	115	bit set in byte1 is DATA mask (0xFF00)
1da177e4 LT	116	msb, data_mask[7:0] , clk_mask[7:0]
1da177e4 LT	117	*/
46aac058	118	#define IO_CFG_WRITE_MODE 0xF
1da177e4	119	#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
46aac058	120	( (((msb)&1) << 16) \| (((data_mask) &0xFF) << 8) \| ((clk_mask) & 0xFF) )
1da177e4 LT	121
	122	/* The following 4 ioctl's take a pointer as argument and handles
	123	* 32 bit ports (port G) properly.
	124	* These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
	125	*/
	126	#define IO_READ_INBITS 0x10 /* arg is result of reading the input pins /
	127	#define IO_READ_OUTBITS 0x11 /* arg is result of reading the output shadow /
	128	#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input,
	129	* *arg updated with current input pins.
	130	*/
	131	#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
	132	* *arg updated with current output pins.
	133	*/
	134
46aac058 JN	135	/* The following ioctl's are applicable to the PWM channels only */
	136
	137	#define IO_PWM_SET_MODE 0x20
	138
	139	enum io_pwm_mode {
	140	PWM_OFF = 0, /* disabled, deallocated */
	141	PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
	142	PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
	143	PWM_VARFREQ = 3 /* individually configurable high/low periods */
	144	};
	145
	146	struct io_pwm_set_mode {
	147	enum io_pwm_mode mode;
	148	};
	149
	150	/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
	151	* from 10ns (value = 0) to 81920ns (value = 8191)
	152	* (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
	153	* 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
	154	* cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
	155	*/
	156	#define IO_PWM_SET_PERIOD 0x21
	157
	158	struct io_pwm_set_period {
	159	int lo; /* 0..8191 */
	160	int hi; /* 0..8191 */
	161	};
	162
	163	/* Only for modes PWM_STANDARD and PWM_FAST.
	164	* For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
	165	* 0 (value = 0) to 255/256 (value = 255).
	166	* For PWM_FAST, set duty cycle of PWM output signal from
	167	* 0% (value = 0) to 100% (value = 255). Output signal in this mode
	168	* is a 10ns pulse surrounded by a high or low level depending on duty
	169	* cycle (except for 0% and 100% which result in a constant output).
	170	* Resulting output frequency varies from 50 MHz at 50% duty cycle,
	171	* down to 390 kHz at min/max duty cycle.
	172	*/
	173	#define IO_PWM_SET_DUTY 0x22
1da177e4	174
46aac058 JN	175	struct io_pwm_set_duty {
	176	int duty; /* 0..255 */
	177	};
1da177e4 LT	178
1da177e4 LT	179	#endif