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Commit | Line | Data |
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3f7e212d AB |
1 | /* Generic I/O port emulation, based on MN10300 code |
2 | * | |
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public Licence | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the Licence, or (at your option) any later version. | |
10 | */ | |
11 | #ifndef __ASM_GENERIC_IO_H | |
12 | #define __ASM_GENERIC_IO_H | |
13 | ||
14 | #include <asm/page.h> /* I/O is all done through memory accesses */ | |
9216efaf | 15 | #include <linux/string.h> /* for memset() and memcpy() */ |
3f7e212d AB |
16 | #include <linux/types.h> |
17 | ||
18 | #ifdef CONFIG_GENERIC_IOMAP | |
19 | #include <asm-generic/iomap.h> | |
20 | #endif | |
21 | ||
66eab4df MT |
22 | #include <asm-generic/pci_iomap.h> |
23 | ||
35dbc0e0 | 24 | #ifndef mmiowb |
3f7e212d | 25 | #define mmiowb() do {} while (0) |
35dbc0e0 | 26 | #endif |
3f7e212d | 27 | |
3f7e212d | 28 | /* |
9216efaf TR |
29 | * __raw_{read,write}{b,w,l,q}() access memory in native endianness. |
30 | * | |
31 | * On some architectures memory mapped IO needs to be accessed differently. | |
32 | * On the simple architectures, we just read/write the memory location | |
33 | * directly. | |
3f7e212d | 34 | */ |
9216efaf | 35 | |
35dbc0e0 | 36 | #ifndef __raw_readb |
9216efaf | 37 | #define __raw_readb __raw_readb |
3f7e212d AB |
38 | static inline u8 __raw_readb(const volatile void __iomem *addr) |
39 | { | |
9216efaf | 40 | return *(const volatile u8 __force *)addr; |
3f7e212d | 41 | } |
35dbc0e0 | 42 | #endif |
3f7e212d | 43 | |
35dbc0e0 | 44 | #ifndef __raw_readw |
9216efaf | 45 | #define __raw_readw __raw_readw |
3f7e212d AB |
46 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
47 | { | |
9216efaf | 48 | return *(const volatile u16 __force *)addr; |
3f7e212d | 49 | } |
35dbc0e0 | 50 | #endif |
3f7e212d | 51 | |
35dbc0e0 | 52 | #ifndef __raw_readl |
9216efaf | 53 | #define __raw_readl __raw_readl |
3f7e212d AB |
54 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
55 | { | |
9216efaf | 56 | return *(const volatile u32 __force *)addr; |
3f7e212d | 57 | } |
35dbc0e0 | 58 | #endif |
3f7e212d | 59 | |
9216efaf TR |
60 | #ifdef CONFIG_64BIT |
61 | #ifndef __raw_readq | |
62 | #define __raw_readq __raw_readq | |
63 | static inline u64 __raw_readq(const volatile void __iomem *addr) | |
7292e7e0 | 64 | { |
9216efaf | 65 | return *(const volatile u64 __force *)addr; |
7292e7e0 | 66 | } |
9216efaf TR |
67 | #endif |
68 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 69 | |
35dbc0e0 | 70 | #ifndef __raw_writeb |
9216efaf TR |
71 | #define __raw_writeb __raw_writeb |
72 | static inline void __raw_writeb(u8 value, volatile void __iomem *addr) | |
3f7e212d | 73 | { |
9216efaf | 74 | *(volatile u8 __force *)addr = value; |
3f7e212d | 75 | } |
35dbc0e0 | 76 | #endif |
3f7e212d | 77 | |
35dbc0e0 | 78 | #ifndef __raw_writew |
9216efaf TR |
79 | #define __raw_writew __raw_writew |
80 | static inline void __raw_writew(u16 value, volatile void __iomem *addr) | |
3f7e212d | 81 | { |
9216efaf | 82 | *(volatile u16 __force *)addr = value; |
3f7e212d | 83 | } |
35dbc0e0 | 84 | #endif |
3f7e212d | 85 | |
35dbc0e0 | 86 | #ifndef __raw_writel |
9216efaf TR |
87 | #define __raw_writel __raw_writel |
88 | static inline void __raw_writel(u32 value, volatile void __iomem *addr) | |
3f7e212d | 89 | { |
9216efaf | 90 | *(volatile u32 __force *)addr = value; |
3f7e212d | 91 | } |
35dbc0e0 | 92 | #endif |
3f7e212d | 93 | |
3f7e212d | 94 | #ifdef CONFIG_64BIT |
9216efaf TR |
95 | #ifndef __raw_writeq |
96 | #define __raw_writeq __raw_writeq | |
97 | static inline void __raw_writeq(u64 value, volatile void __iomem *addr) | |
3f7e212d | 98 | { |
9216efaf | 99 | *(volatile u64 __force *)addr = value; |
3f7e212d | 100 | } |
cd248341 | 101 | #endif |
9216efaf | 102 | #endif /* CONFIG_64BIT */ |
cd248341 | 103 | |
9216efaf TR |
104 | /* |
105 | * {read,write}{b,w,l,q}() access little endian memory and return result in | |
106 | * native endianness. | |
107 | */ | |
3f7e212d | 108 | |
9216efaf TR |
109 | #ifndef readb |
110 | #define readb readb | |
111 | static inline u8 readb(const volatile void __iomem *addr) | |
3f7e212d | 112 | { |
9216efaf | 113 | return __raw_readb(addr); |
3f7e212d | 114 | } |
3f7e212d AB |
115 | #endif |
116 | ||
9216efaf TR |
117 | #ifndef readw |
118 | #define readw readw | |
119 | static inline u16 readw(const volatile void __iomem *addr) | |
120 | { | |
121 | return __le16_to_cpu(__raw_readw(addr)); | |
122 | } | |
7dc59bdd G |
123 | #endif |
124 | ||
9216efaf TR |
125 | #ifndef readl |
126 | #define readl readl | |
127 | static inline u32 readl(const volatile void __iomem *addr) | |
3f7e212d | 128 | { |
9216efaf | 129 | return __le32_to_cpu(__raw_readl(addr)); |
3f7e212d | 130 | } |
9216efaf | 131 | #endif |
3f7e212d | 132 | |
9216efaf TR |
133 | #ifdef CONFIG_64BIT |
134 | #ifndef readq | |
135 | #define readq readq | |
136 | static inline u64 readq(const volatile void __iomem *addr) | |
3f7e212d | 137 | { |
9216efaf | 138 | return __le64_to_cpu(__raw_readq(addr)); |
3f7e212d | 139 | } |
9216efaf TR |
140 | #endif |
141 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 142 | |
9216efaf TR |
143 | #ifndef writeb |
144 | #define writeb writeb | |
145 | static inline void writeb(u8 value, volatile void __iomem *addr) | |
3f7e212d | 146 | { |
9216efaf | 147 | __raw_writeb(value, addr); |
3f7e212d | 148 | } |
9216efaf | 149 | #endif |
3f7e212d | 150 | |
9216efaf TR |
151 | #ifndef writew |
152 | #define writew writew | |
153 | static inline void writew(u16 value, volatile void __iomem *addr) | |
3f7e212d | 154 | { |
9216efaf | 155 | __raw_writew(cpu_to_le16(value), addr); |
3f7e212d | 156 | } |
9216efaf | 157 | #endif |
3f7e212d | 158 | |
9216efaf TR |
159 | #ifndef writel |
160 | #define writel writel | |
161 | static inline void writel(u32 value, volatile void __iomem *addr) | |
3f7e212d | 162 | { |
9216efaf | 163 | __raw_writel(__cpu_to_le32(value), addr); |
3f7e212d | 164 | } |
9216efaf | 165 | #endif |
3f7e212d | 166 | |
9216efaf TR |
167 | #ifdef CONFIG_64BIT |
168 | #ifndef writeq | |
169 | #define writeq writeq | |
170 | static inline void writeq(u64 value, volatile void __iomem *addr) | |
3f7e212d | 171 | { |
9216efaf | 172 | __raw_writeq(__cpu_to_le64(value), addr); |
3f7e212d | 173 | } |
9216efaf TR |
174 | #endif |
175 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 176 | |
1c8d2969 AB |
177 | /* |
178 | * {read,write}{b,w,l,q}_relaxed() are like the regular version, but | |
179 | * are not guaranteed to provide ordering against spinlocks or memory | |
180 | * accesses. | |
181 | */ | |
182 | #ifndef readb_relaxed | |
183 | #define readb_relaxed readb | |
184 | #endif | |
185 | ||
186 | #ifndef readw_relaxed | |
187 | #define readw_relaxed readw | |
188 | #endif | |
189 | ||
190 | #ifndef readl_relaxed | |
191 | #define readl_relaxed readl | |
192 | #endif | |
193 | ||
e511267b | 194 | #if defined(readq) && !defined(readq_relaxed) |
1c8d2969 AB |
195 | #define readq_relaxed readq |
196 | #endif | |
197 | ||
9439eb3a WD |
198 | #ifndef writeb_relaxed |
199 | #define writeb_relaxed writeb | |
200 | #endif | |
201 | ||
9439eb3a WD |
202 | #ifndef writew_relaxed |
203 | #define writew_relaxed writew | |
204 | #endif | |
205 | ||
9439eb3a WD |
206 | #ifndef writel_relaxed |
207 | #define writel_relaxed writel | |
208 | #endif | |
3f7e212d | 209 | |
e511267b | 210 | #if defined(writeq) && !defined(writeq_relaxed) |
1c8d2969 AB |
211 | #define writeq_relaxed writeq |
212 | #endif | |
213 | ||
9ab3a7a0 TR |
214 | /* |
215 | * {read,write}s{b,w,l,q}() repeatedly access the same memory address in | |
216 | * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). | |
217 | */ | |
218 | #ifndef readsb | |
219 | #define readsb readsb | |
220 | static inline void readsb(const volatile void __iomem *addr, void *buffer, | |
221 | unsigned int count) | |
3f7e212d AB |
222 | { |
223 | if (count) { | |
224 | u8 *buf = buffer; | |
9ab3a7a0 | 225 | |
3f7e212d | 226 | do { |
9ab3a7a0 | 227 | u8 x = __raw_readb(addr); |
3f7e212d AB |
228 | *buf++ = x; |
229 | } while (--count); | |
230 | } | |
231 | } | |
35dbc0e0 | 232 | #endif |
3f7e212d | 233 | |
9ab3a7a0 TR |
234 | #ifndef readsw |
235 | #define readsw readsw | |
236 | static inline void readsw(const volatile void __iomem *addr, void *buffer, | |
237 | unsigned int count) | |
3f7e212d AB |
238 | { |
239 | if (count) { | |
240 | u16 *buf = buffer; | |
9ab3a7a0 | 241 | |
3f7e212d | 242 | do { |
9ab3a7a0 | 243 | u16 x = __raw_readw(addr); |
3f7e212d AB |
244 | *buf++ = x; |
245 | } while (--count); | |
246 | } | |
247 | } | |
35dbc0e0 | 248 | #endif |
3f7e212d | 249 | |
9ab3a7a0 TR |
250 | #ifndef readsl |
251 | #define readsl readsl | |
252 | static inline void readsl(const volatile void __iomem *addr, void *buffer, | |
253 | unsigned int count) | |
3f7e212d AB |
254 | { |
255 | if (count) { | |
256 | u32 *buf = buffer; | |
9ab3a7a0 | 257 | |
3f7e212d | 258 | do { |
9ab3a7a0 | 259 | u32 x = __raw_readl(addr); |
3f7e212d AB |
260 | *buf++ = x; |
261 | } while (--count); | |
262 | } | |
263 | } | |
35dbc0e0 | 264 | #endif |
3f7e212d | 265 | |
9ab3a7a0 TR |
266 | #ifdef CONFIG_64BIT |
267 | #ifndef readsq | |
268 | #define readsq readsq | |
269 | static inline void readsq(const volatile void __iomem *addr, void *buffer, | |
270 | unsigned int count) | |
271 | { | |
272 | if (count) { | |
273 | u64 *buf = buffer; | |
274 | ||
275 | do { | |
276 | u64 x = __raw_readq(addr); | |
277 | *buf++ = x; | |
278 | } while (--count); | |
279 | } | |
280 | } | |
281 | #endif | |
282 | #endif /* CONFIG_64BIT */ | |
283 | ||
284 | #ifndef writesb | |
285 | #define writesb writesb | |
286 | static inline void writesb(volatile void __iomem *addr, const void *buffer, | |
287 | unsigned int count) | |
3f7e212d AB |
288 | { |
289 | if (count) { | |
290 | const u8 *buf = buffer; | |
9ab3a7a0 | 291 | |
3f7e212d | 292 | do { |
9ab3a7a0 | 293 | __raw_writeb(*buf++, addr); |
3f7e212d AB |
294 | } while (--count); |
295 | } | |
296 | } | |
35dbc0e0 | 297 | #endif |
3f7e212d | 298 | |
9ab3a7a0 TR |
299 | #ifndef writesw |
300 | #define writesw writesw | |
301 | static inline void writesw(volatile void __iomem *addr, const void *buffer, | |
302 | unsigned int count) | |
3f7e212d AB |
303 | { |
304 | if (count) { | |
305 | const u16 *buf = buffer; | |
9ab3a7a0 | 306 | |
3f7e212d | 307 | do { |
9ab3a7a0 | 308 | __raw_writew(*buf++, addr); |
3f7e212d AB |
309 | } while (--count); |
310 | } | |
311 | } | |
35dbc0e0 | 312 | #endif |
3f7e212d | 313 | |
9ab3a7a0 TR |
314 | #ifndef writesl |
315 | #define writesl writesl | |
316 | static inline void writesl(volatile void __iomem *addr, const void *buffer, | |
317 | unsigned int count) | |
3f7e212d AB |
318 | { |
319 | if (count) { | |
320 | const u32 *buf = buffer; | |
9ab3a7a0 | 321 | |
3f7e212d | 322 | do { |
9ab3a7a0 | 323 | __raw_writel(*buf++, addr); |
3f7e212d AB |
324 | } while (--count); |
325 | } | |
326 | } | |
35dbc0e0 | 327 | #endif |
3f7e212d | 328 | |
9ab3a7a0 TR |
329 | #ifdef CONFIG_64BIT |
330 | #ifndef writesq | |
331 | #define writesq writesq | |
332 | static inline void writesq(volatile void __iomem *addr, const void *buffer, | |
333 | unsigned int count) | |
334 | { | |
335 | if (count) { | |
336 | const u64 *buf = buffer; | |
337 | ||
338 | do { | |
339 | __raw_writeq(*buf++, addr); | |
340 | } while (--count); | |
341 | } | |
342 | } | |
343 | #endif | |
344 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 345 | |
9216efaf TR |
346 | #ifndef PCI_IOBASE |
347 | #define PCI_IOBASE ((void __iomem *)0) | |
348 | #endif | |
349 | ||
7dc59bdd G |
350 | #ifndef IO_SPACE_LIMIT |
351 | #define IO_SPACE_LIMIT 0xffff | |
352 | #endif | |
3f7e212d | 353 | |
90a4bbef | 354 | #include <linux/libio.h> |
355 | ||
9216efaf TR |
356 | /* |
357 | * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be | |
358 | * implemented on hardware that needs an additional delay for I/O accesses to | |
359 | * take effect. | |
360 | */ | |
361 | ||
362 | #ifndef inb | |
90a4bbef | 363 | #ifdef CONFIG_LIBIO |
364 | #define inb libio_inb | |
365 | #else | |
9216efaf TR |
366 | #define inb inb |
367 | static inline u8 inb(unsigned long addr) | |
368 | { | |
369 | return readb(PCI_IOBASE + addr); | |
370 | } | |
90a4bbef | 371 | #endif /* CONFIG_LIBIO */ |
9216efaf TR |
372 | #endif |
373 | ||
374 | #ifndef inw | |
90a4bbef | 375 | #ifdef CONFIG_LIBIO |
376 | #define inw libio_inw | |
377 | #else | |
9216efaf TR |
378 | #define inw inw |
379 | static inline u16 inw(unsigned long addr) | |
380 | { | |
381 | return readw(PCI_IOBASE + addr); | |
382 | } | |
90a4bbef | 383 | #endif /* CONFIG_LIBIO */ |
9216efaf TR |
384 | #endif |
385 | ||
386 | #ifndef inl | |
90a4bbef | 387 | #ifdef CONFIG_LIBIO |
388 | #define inl libio_inl | |
389 | #else | |
9216efaf TR |
390 | #define inl inl |
391 | static inline u32 inl(unsigned long addr) | |
392 | { | |
393 | return readl(PCI_IOBASE + addr); | |
394 | } | |
90a4bbef | 395 | #endif /* CONFIG_LIBIO */ |
9216efaf TR |
396 | #endif |
397 | ||
398 | #ifndef outb | |
90a4bbef | 399 | #ifdef CONFIG_LIBIO |
400 | #define outb libio_outb | |
401 | #else | |
9216efaf TR |
402 | #define outb outb |
403 | static inline void outb(u8 value, unsigned long addr) | |
404 | { | |
405 | writeb(value, PCI_IOBASE + addr); | |
406 | } | |
90a4bbef | 407 | #endif /* CONFIG_LIBIO */ |
9216efaf TR |
408 | #endif |
409 | ||
410 | #ifndef outw | |
90a4bbef | 411 | #ifdef CONFIG_LIBIO |
412 | #define outw libio_outw | |
413 | #else | |
9216efaf TR |
414 | #define outw outw |
415 | static inline void outw(u16 value, unsigned long addr) | |
416 | { | |
417 | writew(value, PCI_IOBASE + addr); | |
418 | } | |
90a4bbef | 419 | #endif /* CONFIG_LIBIO */ |
9216efaf TR |
420 | #endif |
421 | ||
422 | #ifndef outl | |
90a4bbef | 423 | #ifdef CONFIG_LIBIO |
424 | #define outl libio_outl | |
425 | #else | |
9216efaf TR |
426 | #define outl outl |
427 | static inline void outl(u32 value, unsigned long addr) | |
428 | { | |
429 | writel(value, PCI_IOBASE + addr); | |
430 | } | |
90a4bbef | 431 | #endif /* CONFIG_LIBIO */ |
9216efaf TR |
432 | #endif |
433 | ||
434 | #ifndef inb_p | |
435 | #define inb_p inb_p | |
436 | static inline u8 inb_p(unsigned long addr) | |
437 | { | |
438 | return inb(addr); | |
439 | } | |
440 | #endif | |
441 | ||
442 | #ifndef inw_p | |
443 | #define inw_p inw_p | |
444 | static inline u16 inw_p(unsigned long addr) | |
445 | { | |
446 | return inw(addr); | |
447 | } | |
448 | #endif | |
449 | ||
450 | #ifndef inl_p | |
451 | #define inl_p inl_p | |
452 | static inline u32 inl_p(unsigned long addr) | |
453 | { | |
454 | return inl(addr); | |
455 | } | |
456 | #endif | |
457 | ||
458 | #ifndef outb_p | |
459 | #define outb_p outb_p | |
460 | static inline void outb_p(u8 value, unsigned long addr) | |
461 | { | |
462 | outb(value, addr); | |
463 | } | |
464 | #endif | |
465 | ||
466 | #ifndef outw_p | |
467 | #define outw_p outw_p | |
468 | static inline void outw_p(u16 value, unsigned long addr) | |
469 | { | |
470 | outw(value, addr); | |
471 | } | |
472 | #endif | |
473 | ||
474 | #ifndef outl_p | |
475 | #define outl_p outl_p | |
476 | static inline void outl_p(u32 value, unsigned long addr) | |
477 | { | |
478 | outl(value, addr); | |
479 | } | |
480 | #endif | |
481 | ||
9ab3a7a0 TR |
482 | /* |
483 | * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a | |
484 | * single I/O port multiple times. | |
485 | */ | |
486 | ||
487 | #ifndef insb | |
90a4bbef | 488 | #ifdef CONFIG_LIBIO |
489 | #define insb libio_insb | |
490 | #else | |
9ab3a7a0 TR |
491 | #define insb insb |
492 | static inline void insb(unsigned long addr, void *buffer, unsigned int count) | |
493 | { | |
494 | readsb(PCI_IOBASE + addr, buffer, count); | |
495 | } | |
90a4bbef | 496 | #endif /* CONFIG_LIBIO */ |
9ab3a7a0 TR |
497 | #endif |
498 | ||
499 | #ifndef insw | |
90a4bbef | 500 | #ifdef CONFIG_LIBIO |
501 | #define insw libio_insw | |
502 | #else | |
9ab3a7a0 TR |
503 | #define insw insw |
504 | static inline void insw(unsigned long addr, void *buffer, unsigned int count) | |
505 | { | |
506 | readsw(PCI_IOBASE + addr, buffer, count); | |
507 | } | |
90a4bbef | 508 | #endif /* CONFIG_LIBIO */ |
9ab3a7a0 TR |
509 | #endif |
510 | ||
511 | #ifndef insl | |
90a4bbef | 512 | #ifdef CONFIG_LIBIO |
513 | #define insl libio_insl | |
514 | #else | |
9ab3a7a0 TR |
515 | #define insl insl |
516 | static inline void insl(unsigned long addr, void *buffer, unsigned int count) | |
517 | { | |
518 | readsl(PCI_IOBASE + addr, buffer, count); | |
519 | } | |
90a4bbef | 520 | #endif /* CONFIG_LIBIO */ |
9ab3a7a0 TR |
521 | #endif |
522 | ||
523 | #ifndef outsb | |
90a4bbef | 524 | #ifdef CONFIG_LIBIO |
525 | #define outsb libio_outsb | |
526 | #else | |
9ab3a7a0 TR |
527 | #define outsb outsb |
528 | static inline void outsb(unsigned long addr, const void *buffer, | |
529 | unsigned int count) | |
530 | { | |
531 | writesb(PCI_IOBASE + addr, buffer, count); | |
532 | } | |
90a4bbef | 533 | #endif /* CONFIG_LIBIO */ |
9ab3a7a0 TR |
534 | #endif |
535 | ||
536 | #ifndef outsw | |
90a4bbef | 537 | #ifdef CONFIG_LIBIO |
538 | #define outsw libio_outsw | |
539 | #else | |
9ab3a7a0 TR |
540 | #define outsw outsw |
541 | static inline void outsw(unsigned long addr, const void *buffer, | |
542 | unsigned int count) | |
543 | { | |
544 | writesw(PCI_IOBASE + addr, buffer, count); | |
545 | } | |
90a4bbef | 546 | #endif /* CONFIG_LIBIO */ |
9ab3a7a0 TR |
547 | #endif |
548 | ||
549 | #ifndef outsl | |
90a4bbef | 550 | #ifdef CONFIG_LIBIO |
551 | #define outsl libio_outsl | |
552 | #else | |
9ab3a7a0 TR |
553 | #define outsl outsl |
554 | static inline void outsl(unsigned long addr, const void *buffer, | |
555 | unsigned int count) | |
556 | { | |
557 | writesl(PCI_IOBASE + addr, buffer, count); | |
558 | } | |
90a4bbef | 559 | #endif /* CONFIG_LIBIO */ |
9ab3a7a0 TR |
560 | #endif |
561 | ||
562 | #ifndef insb_p | |
563 | #define insb_p insb_p | |
564 | static inline void insb_p(unsigned long addr, void *buffer, unsigned int count) | |
565 | { | |
566 | insb(addr, buffer, count); | |
567 | } | |
568 | #endif | |
569 | ||
570 | #ifndef insw_p | |
571 | #define insw_p insw_p | |
572 | static inline void insw_p(unsigned long addr, void *buffer, unsigned int count) | |
573 | { | |
574 | insw(addr, buffer, count); | |
575 | } | |
576 | #endif | |
577 | ||
578 | #ifndef insl_p | |
579 | #define insl_p insl_p | |
580 | static inline void insl_p(unsigned long addr, void *buffer, unsigned int count) | |
581 | { | |
582 | insl(addr, buffer, count); | |
583 | } | |
584 | #endif | |
585 | ||
586 | #ifndef outsb_p | |
587 | #define outsb_p outsb_p | |
588 | static inline void outsb_p(unsigned long addr, const void *buffer, | |
589 | unsigned int count) | |
590 | { | |
591 | outsb(addr, buffer, count); | |
592 | } | |
593 | #endif | |
594 | ||
595 | #ifndef outsw_p | |
596 | #define outsw_p outsw_p | |
597 | static inline void outsw_p(unsigned long addr, const void *buffer, | |
598 | unsigned int count) | |
599 | { | |
600 | outsw(addr, buffer, count); | |
601 | } | |
602 | #endif | |
603 | ||
604 | #ifndef outsl_p | |
605 | #define outsl_p outsl_p | |
606 | static inline void outsl_p(unsigned long addr, const void *buffer, | |
607 | unsigned int count) | |
608 | { | |
609 | outsl(addr, buffer, count); | |
610 | } | |
611 | #endif | |
612 | ||
9216efaf TR |
613 | #ifndef CONFIG_GENERIC_IOMAP |
614 | #ifndef ioread8 | |
615 | #define ioread8 ioread8 | |
616 | static inline u8 ioread8(const volatile void __iomem *addr) | |
617 | { | |
618 | return readb(addr); | |
619 | } | |
620 | #endif | |
621 | ||
622 | #ifndef ioread16 | |
623 | #define ioread16 ioread16 | |
624 | static inline u16 ioread16(const volatile void __iomem *addr) | |
625 | { | |
626 | return readw(addr); | |
627 | } | |
628 | #endif | |
629 | ||
630 | #ifndef ioread32 | |
631 | #define ioread32 ioread32 | |
632 | static inline u32 ioread32(const volatile void __iomem *addr) | |
633 | { | |
634 | return readl(addr); | |
635 | } | |
636 | #endif | |
637 | ||
9e44fb18 HG |
638 | #ifdef CONFIG_64BIT |
639 | #ifndef ioread64 | |
640 | #define ioread64 ioread64 | |
641 | static inline u64 ioread64(const volatile void __iomem *addr) | |
642 | { | |
643 | return readq(addr); | |
644 | } | |
645 | #endif | |
646 | #endif /* CONFIG_64BIT */ | |
647 | ||
9216efaf TR |
648 | #ifndef iowrite8 |
649 | #define iowrite8 iowrite8 | |
650 | static inline void iowrite8(u8 value, volatile void __iomem *addr) | |
651 | { | |
652 | writeb(value, addr); | |
653 | } | |
654 | #endif | |
655 | ||
656 | #ifndef iowrite16 | |
657 | #define iowrite16 iowrite16 | |
658 | static inline void iowrite16(u16 value, volatile void __iomem *addr) | |
659 | { | |
660 | writew(value, addr); | |
661 | } | |
662 | #endif | |
663 | ||
664 | #ifndef iowrite32 | |
665 | #define iowrite32 iowrite32 | |
666 | static inline void iowrite32(u32 value, volatile void __iomem *addr) | |
667 | { | |
668 | writel(value, addr); | |
669 | } | |
670 | #endif | |
671 | ||
9e44fb18 HG |
672 | #ifdef CONFIG_64BIT |
673 | #ifndef iowrite64 | |
674 | #define iowrite64 iowrite64 | |
675 | static inline void iowrite64(u64 value, volatile void __iomem *addr) | |
676 | { | |
677 | writeq(value, addr); | |
678 | } | |
679 | #endif | |
680 | #endif /* CONFIG_64BIT */ | |
681 | ||
9216efaf TR |
682 | #ifndef ioread16be |
683 | #define ioread16be ioread16be | |
684 | static inline u16 ioread16be(const volatile void __iomem *addr) | |
685 | { | |
7a1aedba | 686 | return swab16(readw(addr)); |
9216efaf TR |
687 | } |
688 | #endif | |
689 | ||
690 | #ifndef ioread32be | |
691 | #define ioread32be ioread32be | |
692 | static inline u32 ioread32be(const volatile void __iomem *addr) | |
693 | { | |
7a1aedba | 694 | return swab32(readl(addr)); |
9216efaf TR |
695 | } |
696 | #endif | |
697 | ||
9e44fb18 HG |
698 | #ifdef CONFIG_64BIT |
699 | #ifndef ioread64be | |
700 | #define ioread64be ioread64be | |
701 | static inline u64 ioread64be(const volatile void __iomem *addr) | |
702 | { | |
703 | return swab64(readq(addr)); | |
704 | } | |
705 | #endif | |
706 | #endif /* CONFIG_64BIT */ | |
707 | ||
9216efaf TR |
708 | #ifndef iowrite16be |
709 | #define iowrite16be iowrite16be | |
710 | static inline void iowrite16be(u16 value, void volatile __iomem *addr) | |
711 | { | |
7a1aedba | 712 | writew(swab16(value), addr); |
9216efaf TR |
713 | } |
714 | #endif | |
715 | ||
716 | #ifndef iowrite32be | |
717 | #define iowrite32be iowrite32be | |
718 | static inline void iowrite32be(u32 value, volatile void __iomem *addr) | |
719 | { | |
7a1aedba | 720 | writel(swab32(value), addr); |
9216efaf TR |
721 | } |
722 | #endif | |
9ab3a7a0 | 723 | |
9e44fb18 HG |
724 | #ifdef CONFIG_64BIT |
725 | #ifndef iowrite64be | |
726 | #define iowrite64be iowrite64be | |
727 | static inline void iowrite64be(u64 value, volatile void __iomem *addr) | |
728 | { | |
729 | writeq(swab64(value), addr); | |
730 | } | |
731 | #endif | |
732 | #endif /* CONFIG_64BIT */ | |
733 | ||
9ab3a7a0 TR |
734 | #ifndef ioread8_rep |
735 | #define ioread8_rep ioread8_rep | |
736 | static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer, | |
737 | unsigned int count) | |
738 | { | |
739 | readsb(addr, buffer, count); | |
740 | } | |
741 | #endif | |
742 | ||
743 | #ifndef ioread16_rep | |
744 | #define ioread16_rep ioread16_rep | |
745 | static inline void ioread16_rep(const volatile void __iomem *addr, | |
746 | void *buffer, unsigned int count) | |
747 | { | |
748 | readsw(addr, buffer, count); | |
749 | } | |
750 | #endif | |
751 | ||
752 | #ifndef ioread32_rep | |
753 | #define ioread32_rep ioread32_rep | |
754 | static inline void ioread32_rep(const volatile void __iomem *addr, | |
755 | void *buffer, unsigned int count) | |
756 | { | |
757 | readsl(addr, buffer, count); | |
758 | } | |
759 | #endif | |
760 | ||
9e44fb18 HG |
761 | #ifdef CONFIG_64BIT |
762 | #ifndef ioread64_rep | |
763 | #define ioread64_rep ioread64_rep | |
764 | static inline void ioread64_rep(const volatile void __iomem *addr, | |
765 | void *buffer, unsigned int count) | |
766 | { | |
767 | readsq(addr, buffer, count); | |
768 | } | |
769 | #endif | |
770 | #endif /* CONFIG_64BIT */ | |
771 | ||
9ab3a7a0 TR |
772 | #ifndef iowrite8_rep |
773 | #define iowrite8_rep iowrite8_rep | |
774 | static inline void iowrite8_rep(volatile void __iomem *addr, | |
775 | const void *buffer, | |
776 | unsigned int count) | |
777 | { | |
778 | writesb(addr, buffer, count); | |
779 | } | |
780 | #endif | |
781 | ||
782 | #ifndef iowrite16_rep | |
783 | #define iowrite16_rep iowrite16_rep | |
784 | static inline void iowrite16_rep(volatile void __iomem *addr, | |
785 | const void *buffer, | |
786 | unsigned int count) | |
787 | { | |
788 | writesw(addr, buffer, count); | |
789 | } | |
790 | #endif | |
791 | ||
792 | #ifndef iowrite32_rep | |
793 | #define iowrite32_rep iowrite32_rep | |
794 | static inline void iowrite32_rep(volatile void __iomem *addr, | |
795 | const void *buffer, | |
796 | unsigned int count) | |
797 | { | |
798 | writesl(addr, buffer, count); | |
799 | } | |
800 | #endif | |
9e44fb18 HG |
801 | |
802 | #ifdef CONFIG_64BIT | |
803 | #ifndef iowrite64_rep | |
804 | #define iowrite64_rep iowrite64_rep | |
805 | static inline void iowrite64_rep(volatile void __iomem *addr, | |
806 | const void *buffer, | |
807 | unsigned int count) | |
808 | { | |
809 | writesq(addr, buffer, count); | |
810 | } | |
811 | #endif | |
812 | #endif /* CONFIG_64BIT */ | |
9216efaf TR |
813 | #endif /* CONFIG_GENERIC_IOMAP */ |
814 | ||
3f7e212d AB |
815 | #ifdef __KERNEL__ |
816 | ||
817 | #include <linux/vmalloc.h> | |
9216efaf | 818 | #define __io_virt(x) ((void __force *)(x)) |
3f7e212d AB |
819 | |
820 | #ifndef CONFIG_GENERIC_IOMAP | |
3f7e212d | 821 | struct pci_dev; |
cd248341 JG |
822 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); |
823 | ||
824 | #ifndef pci_iounmap | |
9216efaf | 825 | #define pci_iounmap pci_iounmap |
3f7e212d AB |
826 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) |
827 | { | |
828 | } | |
cd248341 | 829 | #endif |
3f7e212d AB |
830 | #endif /* CONFIG_GENERIC_IOMAP */ |
831 | ||
832 | /* | |
833 | * Change virtual addresses to physical addresses and vv. | |
834 | * These are pretty trivial | |
835 | */ | |
cd248341 | 836 | #ifndef virt_to_phys |
9216efaf | 837 | #define virt_to_phys virt_to_phys |
3f7e212d AB |
838 | static inline unsigned long virt_to_phys(volatile void *address) |
839 | { | |
840 | return __pa((unsigned long)address); | |
841 | } | |
9216efaf | 842 | #endif |
3f7e212d | 843 | |
9216efaf TR |
844 | #ifndef phys_to_virt |
845 | #define phys_to_virt phys_to_virt | |
3f7e212d AB |
846 | static inline void *phys_to_virt(unsigned long address) |
847 | { | |
848 | return __va(address); | |
849 | } | |
cd248341 | 850 | #endif |
3f7e212d | 851 | |
8c7ea50c LR |
852 | /** |
853 | * DOC: ioremap() and ioremap_*() variants | |
854 | * | |
855 | * If you have an IOMMU your architecture is expected to have both ioremap() | |
856 | * and iounmap() implemented otherwise the asm-generic helpers will provide a | |
857 | * direct mapping. | |
858 | * | |
859 | * There are ioremap_*() call variants, if you have no IOMMU we naturally will | |
860 | * default to direct mapping for all of them, you can override these defaults. | |
861 | * If you have an IOMMU you are highly encouraged to provide your own | |
862 | * ioremap variant implementation as there currently is no safe architecture | |
863 | * agnostic default. To avoid possible improper behaviour default asm-generic | |
864 | * ioremap_*() variants all return NULL when an IOMMU is available. If you've | |
865 | * defined your own ioremap_*() variant you must then declare your own | |
866 | * ioremap_*() variant as defined to itself to avoid the default NULL return. | |
867 | */ | |
868 | ||
869 | #ifdef CONFIG_MMU | |
870 | ||
871 | #ifndef ioremap_uc | |
872 | #define ioremap_uc ioremap_uc | |
873 | static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size) | |
874 | { | |
875 | return NULL; | |
876 | } | |
877 | #endif | |
878 | ||
879 | #else /* !CONFIG_MMU */ | |
880 | ||
3f7e212d AB |
881 | /* |
882 | * Change "struct page" to physical address. | |
f1ecc698 JB |
883 | * |
884 | * This implementation is for the no-MMU case only... if you have an MMU | |
885 | * you'll need to provide your own definitions. | |
3f7e212d | 886 | */ |
9216efaf | 887 | |
9216efaf TR |
888 | #ifndef ioremap |
889 | #define ioremap ioremap | |
890 | static inline void __iomem *ioremap(phys_addr_t offset, size_t size) | |
3f7e212d | 891 | { |
9216efaf | 892 | return (void __iomem *)(unsigned long)offset; |
3f7e212d | 893 | } |
9216efaf | 894 | #endif |
3f7e212d | 895 | |
9216efaf TR |
896 | #ifndef __ioremap |
897 | #define __ioremap __ioremap | |
898 | static inline void __iomem *__ioremap(phys_addr_t offset, size_t size, | |
899 | unsigned long flags) | |
900 | { | |
901 | return ioremap(offset, size); | |
902 | } | |
903 | #endif | |
3f7e212d AB |
904 | |
905 | #ifndef ioremap_nocache | |
9216efaf TR |
906 | #define ioremap_nocache ioremap_nocache |
907 | static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size) | |
908 | { | |
909 | return ioremap(offset, size); | |
910 | } | |
3f7e212d AB |
911 | #endif |
912 | ||
e4b6be33 LR |
913 | #ifndef ioremap_uc |
914 | #define ioremap_uc ioremap_uc | |
915 | static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size) | |
916 | { | |
917 | return ioremap_nocache(offset, size); | |
918 | } | |
919 | #endif | |
920 | ||
3f7e212d | 921 | #ifndef ioremap_wc |
9216efaf TR |
922 | #define ioremap_wc ioremap_wc |
923 | static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size) | |
924 | { | |
925 | return ioremap_nocache(offset, size); | |
926 | } | |
3f7e212d AB |
927 | #endif |
928 | ||
d838270e TK |
929 | #ifndef ioremap_wt |
930 | #define ioremap_wt ioremap_wt | |
931 | static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size) | |
932 | { | |
933 | return ioremap_nocache(offset, size); | |
934 | } | |
935 | #endif | |
936 | ||
9216efaf TR |
937 | #ifndef iounmap |
938 | #define iounmap iounmap | |
d838270e | 939 | |
e66d3c49 | 940 | static inline void iounmap(void __iomem *addr) |
3f7e212d AB |
941 | { |
942 | } | |
9216efaf | 943 | #endif |
f1ecc698 | 944 | #endif /* CONFIG_MMU */ |
3f7e212d | 945 | |
ce816fa8 | 946 | #ifdef CONFIG_HAS_IOPORT_MAP |
3f7e212d | 947 | #ifndef CONFIG_GENERIC_IOMAP |
9216efaf TR |
948 | #ifndef ioport_map |
949 | #define ioport_map ioport_map | |
3f7e212d AB |
950 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) |
951 | { | |
112eeaa7 | 952 | return PCI_IOBASE + (port & IO_SPACE_LIMIT); |
3f7e212d | 953 | } |
9216efaf | 954 | #endif |
3f7e212d | 955 | |
9216efaf TR |
956 | #ifndef ioport_unmap |
957 | #define ioport_unmap ioport_unmap | |
3f7e212d AB |
958 | static inline void ioport_unmap(void __iomem *p) |
959 | { | |
960 | } | |
9216efaf | 961 | #endif |
3f7e212d AB |
962 | #else /* CONFIG_GENERIC_IOMAP */ |
963 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
964 | extern void ioport_unmap(void __iomem *p); | |
965 | #endif /* CONFIG_GENERIC_IOMAP */ | |
ce816fa8 | 966 | #endif /* CONFIG_HAS_IOPORT_MAP */ |
3f7e212d | 967 | |
576ebd74 | 968 | #ifndef xlate_dev_kmem_ptr |
9216efaf TR |
969 | #define xlate_dev_kmem_ptr xlate_dev_kmem_ptr |
970 | static inline void *xlate_dev_kmem_ptr(void *addr) | |
971 | { | |
972 | return addr; | |
973 | } | |
576ebd74 | 974 | #endif |
9216efaf | 975 | |
576ebd74 | 976 | #ifndef xlate_dev_mem_ptr |
9216efaf TR |
977 | #define xlate_dev_mem_ptr xlate_dev_mem_ptr |
978 | static inline void *xlate_dev_mem_ptr(phys_addr_t addr) | |
979 | { | |
980 | return __va(addr); | |
981 | } | |
982 | #endif | |
983 | ||
984 | #ifndef unxlate_dev_mem_ptr | |
985 | #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr | |
986 | static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr) | |
987 | { | |
988 | } | |
576ebd74 | 989 | #endif |
3f7e212d | 990 | |
c93d0312 | 991 | #ifdef CONFIG_VIRT_TO_BUS |
3f7e212d | 992 | #ifndef virt_to_bus |
9216efaf | 993 | static inline unsigned long virt_to_bus(void *address) |
3f7e212d | 994 | { |
9216efaf | 995 | return (unsigned long)address; |
3f7e212d AB |
996 | } |
997 | ||
998 | static inline void *bus_to_virt(unsigned long address) | |
999 | { | |
9216efaf | 1000 | return (void *)address; |
3f7e212d AB |
1001 | } |
1002 | #endif | |
c93d0312 | 1003 | #endif |
3f7e212d | 1004 | |
cd248341 | 1005 | #ifndef memset_io |
9216efaf TR |
1006 | #define memset_io memset_io |
1007 | static inline void memset_io(volatile void __iomem *addr, int value, | |
1008 | size_t size) | |
1009 | { | |
1010 | memset(__io_virt(addr), value, size); | |
1011 | } | |
cd248341 JG |
1012 | #endif |
1013 | ||
1014 | #ifndef memcpy_fromio | |
9216efaf TR |
1015 | #define memcpy_fromio memcpy_fromio |
1016 | static inline void memcpy_fromio(void *buffer, | |
1017 | const volatile void __iomem *addr, | |
1018 | size_t size) | |
1019 | { | |
1020 | memcpy(buffer, __io_virt(addr), size); | |
1021 | } | |
cd248341 | 1022 | #endif |
9216efaf | 1023 | |
cd248341 | 1024 | #ifndef memcpy_toio |
9216efaf TR |
1025 | #define memcpy_toio memcpy_toio |
1026 | static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer, | |
1027 | size_t size) | |
1028 | { | |
1029 | memcpy(__io_virt(addr), buffer, size); | |
1030 | } | |
cd248341 | 1031 | #endif |
3f7e212d AB |
1032 | |
1033 | #endif /* __KERNEL__ */ | |
1034 | ||
1035 | #endif /* __ASM_GENERIC_IO_H */ |