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3f7e212d AB |
1 | /* Generic I/O port emulation, based on MN10300 code |
2 | * | |
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public Licence | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the Licence, or (at your option) any later version. | |
10 | */ | |
11 | #ifndef __ASM_GENERIC_IO_H | |
12 | #define __ASM_GENERIC_IO_H | |
13 | ||
14 | #include <asm/page.h> /* I/O is all done through memory accesses */ | |
15 | #include <asm/cacheflush.h> | |
16 | #include <linux/types.h> | |
17 | ||
18 | #ifdef CONFIG_GENERIC_IOMAP | |
19 | #include <asm-generic/iomap.h> | |
20 | #endif | |
21 | ||
35dbc0e0 | 22 | #ifndef mmiowb |
3f7e212d | 23 | #define mmiowb() do {} while (0) |
35dbc0e0 | 24 | #endif |
3f7e212d AB |
25 | |
26 | /*****************************************************************************/ | |
27 | /* | |
28 | * readX/writeX() are used to access memory mapped devices. On some | |
29 | * architectures the memory mapped IO stuff needs to be accessed | |
30 | * differently. On the simple architectures, we just read/write the | |
31 | * memory location directly. | |
32 | */ | |
35dbc0e0 | 33 | #ifndef __raw_readb |
3f7e212d AB |
34 | static inline u8 __raw_readb(const volatile void __iomem *addr) |
35 | { | |
36 | return *(const volatile u8 __force *) addr; | |
37 | } | |
35dbc0e0 | 38 | #endif |
3f7e212d | 39 | |
35dbc0e0 | 40 | #ifndef __raw_readw |
3f7e212d AB |
41 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
42 | { | |
43 | return *(const volatile u16 __force *) addr; | |
44 | } | |
35dbc0e0 | 45 | #endif |
3f7e212d | 46 | |
35dbc0e0 | 47 | #ifndef __raw_readl |
3f7e212d AB |
48 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
49 | { | |
50 | return *(const volatile u32 __force *) addr; | |
51 | } | |
35dbc0e0 | 52 | #endif |
3f7e212d AB |
53 | |
54 | #define readb __raw_readb | |
55 | #define readw(addr) __le16_to_cpu(__raw_readw(addr)) | |
56 | #define readl(addr) __le32_to_cpu(__raw_readl(addr)) | |
57 | ||
35dbc0e0 | 58 | #ifndef __raw_writeb |
3f7e212d AB |
59 | static inline void __raw_writeb(u8 b, volatile void __iomem *addr) |
60 | { | |
61 | *(volatile u8 __force *) addr = b; | |
62 | } | |
35dbc0e0 | 63 | #endif |
3f7e212d | 64 | |
35dbc0e0 | 65 | #ifndef __raw_writew |
3f7e212d AB |
66 | static inline void __raw_writew(u16 b, volatile void __iomem *addr) |
67 | { | |
68 | *(volatile u16 __force *) addr = b; | |
69 | } | |
35dbc0e0 | 70 | #endif |
3f7e212d | 71 | |
35dbc0e0 | 72 | #ifndef __raw_writel |
3f7e212d AB |
73 | static inline void __raw_writel(u32 b, volatile void __iomem *addr) |
74 | { | |
75 | *(volatile u32 __force *) addr = b; | |
76 | } | |
35dbc0e0 | 77 | #endif |
3f7e212d AB |
78 | |
79 | #define writeb __raw_writeb | |
80 | #define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr) | |
81 | #define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr) | |
82 | ||
83 | #ifdef CONFIG_64BIT | |
84 | static inline u64 __raw_readq(const volatile void __iomem *addr) | |
85 | { | |
86 | return *(const volatile u64 __force *) addr; | |
87 | } | |
88 | #define readq(addr) __le64_to_cpu(__raw_readq(addr)) | |
89 | ||
90 | static inline void __raw_writeq(u64 b, volatile void __iomem *addr) | |
91 | { | |
92 | *(volatile u64 __force *) addr = b; | |
93 | } | |
94 | #define writeq(b,addr) __raw_writeq(__cpu_to_le64(b),addr) | |
95 | #endif | |
96 | ||
7dc59bdd G |
97 | #ifndef PCI_IOBASE |
98 | #define PCI_IOBASE ((void __iomem *) 0) | |
99 | #endif | |
100 | ||
3f7e212d AB |
101 | /*****************************************************************************/ |
102 | /* | |
103 | * traditional input/output functions | |
104 | */ | |
105 | ||
106 | static inline u8 inb(unsigned long addr) | |
107 | { | |
7dc59bdd | 108 | return readb(addr + PCI_IOBASE); |
3f7e212d AB |
109 | } |
110 | ||
111 | static inline u16 inw(unsigned long addr) | |
112 | { | |
7dc59bdd | 113 | return readw(addr + PCI_IOBASE); |
3f7e212d AB |
114 | } |
115 | ||
116 | static inline u32 inl(unsigned long addr) | |
117 | { | |
7dc59bdd | 118 | return readl(addr + PCI_IOBASE); |
3f7e212d AB |
119 | } |
120 | ||
121 | static inline void outb(u8 b, unsigned long addr) | |
122 | { | |
7dc59bdd | 123 | writeb(b, addr + PCI_IOBASE); |
3f7e212d AB |
124 | } |
125 | ||
126 | static inline void outw(u16 b, unsigned long addr) | |
127 | { | |
7dc59bdd | 128 | writew(b, addr + PCI_IOBASE); |
3f7e212d AB |
129 | } |
130 | ||
131 | static inline void outl(u32 b, unsigned long addr) | |
132 | { | |
7dc59bdd | 133 | writel(b, addr + PCI_IOBASE); |
3f7e212d AB |
134 | } |
135 | ||
136 | #define inb_p(addr) inb(addr) | |
137 | #define inw_p(addr) inw(addr) | |
138 | #define inl_p(addr) inl(addr) | |
139 | #define outb_p(x, addr) outb((x), (addr)) | |
140 | #define outw_p(x, addr) outw((x), (addr)) | |
141 | #define outl_p(x, addr) outl((x), (addr)) | |
142 | ||
35dbc0e0 | 143 | #ifndef insb |
3f7e212d AB |
144 | static inline void insb(unsigned long addr, void *buffer, int count) |
145 | { | |
146 | if (count) { | |
147 | u8 *buf = buffer; | |
148 | do { | |
149 | u8 x = inb(addr); | |
150 | *buf++ = x; | |
151 | } while (--count); | |
152 | } | |
153 | } | |
35dbc0e0 | 154 | #endif |
3f7e212d | 155 | |
35dbc0e0 | 156 | #ifndef insw |
3f7e212d AB |
157 | static inline void insw(unsigned long addr, void *buffer, int count) |
158 | { | |
159 | if (count) { | |
160 | u16 *buf = buffer; | |
161 | do { | |
162 | u16 x = inw(addr); | |
163 | *buf++ = x; | |
164 | } while (--count); | |
165 | } | |
166 | } | |
35dbc0e0 | 167 | #endif |
3f7e212d | 168 | |
35dbc0e0 | 169 | #ifndef insl |
3f7e212d AB |
170 | static inline void insl(unsigned long addr, void *buffer, int count) |
171 | { | |
172 | if (count) { | |
173 | u32 *buf = buffer; | |
174 | do { | |
175 | u32 x = inl(addr); | |
176 | *buf++ = x; | |
177 | } while (--count); | |
178 | } | |
179 | } | |
35dbc0e0 | 180 | #endif |
3f7e212d | 181 | |
35dbc0e0 | 182 | #ifndef outsb |
3f7e212d AB |
183 | static inline void outsb(unsigned long addr, const void *buffer, int count) |
184 | { | |
185 | if (count) { | |
186 | const u8 *buf = buffer; | |
187 | do { | |
188 | outb(*buf++, addr); | |
189 | } while (--count); | |
190 | } | |
191 | } | |
35dbc0e0 | 192 | #endif |
3f7e212d | 193 | |
35dbc0e0 | 194 | #ifndef outsw |
3f7e212d AB |
195 | static inline void outsw(unsigned long addr, const void *buffer, int count) |
196 | { | |
197 | if (count) { | |
198 | const u16 *buf = buffer; | |
199 | do { | |
200 | outw(*buf++, addr); | |
201 | } while (--count); | |
202 | } | |
203 | } | |
35dbc0e0 | 204 | #endif |
3f7e212d | 205 | |
35dbc0e0 | 206 | #ifndef outsl |
3f7e212d AB |
207 | static inline void outsl(unsigned long addr, const void *buffer, int count) |
208 | { | |
209 | if (count) { | |
210 | const u32 *buf = buffer; | |
211 | do { | |
212 | outl(*buf++, addr); | |
213 | } while (--count); | |
214 | } | |
215 | } | |
35dbc0e0 | 216 | #endif |
3f7e212d | 217 | |
efb2d31c MF |
218 | static inline void readsl(const void __iomem *addr, void *buf, int len) |
219 | { | |
7dc59bdd | 220 | insl(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
221 | } |
222 | ||
223 | static inline void readsw(const void __iomem *addr, void *buf, int len) | |
224 | { | |
7dc59bdd | 225 | insw(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
226 | } |
227 | ||
228 | static inline void readsb(const void __iomem *addr, void *buf, int len) | |
229 | { | |
7dc59bdd | 230 | insb(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
231 | } |
232 | ||
233 | static inline void writesl(const void __iomem *addr, const void *buf, int len) | |
234 | { | |
7dc59bdd | 235 | outsl(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
236 | } |
237 | ||
238 | static inline void writesw(const void __iomem *addr, const void *buf, int len) | |
239 | { | |
7dc59bdd | 240 | outsw(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
241 | } |
242 | ||
243 | static inline void writesb(const void __iomem *addr, const void *buf, int len) | |
244 | { | |
7dc59bdd | 245 | outsb(addr - PCI_IOBASE, buf, len); |
efb2d31c MF |
246 | } |
247 | ||
3f7e212d AB |
248 | #ifndef CONFIG_GENERIC_IOMAP |
249 | #define ioread8(addr) readb(addr) | |
250 | #define ioread16(addr) readw(addr) | |
7387be33 | 251 | #define ioread16be(addr) be16_to_cpu(ioread16(addr)) |
3f7e212d | 252 | #define ioread32(addr) readl(addr) |
7387be33 | 253 | #define ioread32be(addr) be32_to_cpu(ioread32(addr)) |
3f7e212d AB |
254 | |
255 | #define iowrite8(v, addr) writeb((v), (addr)) | |
256 | #define iowrite16(v, addr) writew((v), (addr)) | |
7387be33 | 257 | #define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr)) |
3f7e212d | 258 | #define iowrite32(v, addr) writel((v), (addr)) |
7387be33 | 259 | #define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr)) |
3f7e212d AB |
260 | |
261 | #define ioread8_rep(p, dst, count) \ | |
262 | insb((unsigned long) (p), (dst), (count)) | |
263 | #define ioread16_rep(p, dst, count) \ | |
264 | insw((unsigned long) (p), (dst), (count)) | |
265 | #define ioread32_rep(p, dst, count) \ | |
266 | insl((unsigned long) (p), (dst), (count)) | |
267 | ||
268 | #define iowrite8_rep(p, src, count) \ | |
269 | outsb((unsigned long) (p), (src), (count)) | |
270 | #define iowrite16_rep(p, src, count) \ | |
271 | outsw((unsigned long) (p), (src), (count)) | |
272 | #define iowrite32_rep(p, src, count) \ | |
273 | outsl((unsigned long) (p), (src), (count)) | |
274 | #endif /* CONFIG_GENERIC_IOMAP */ | |
275 | ||
7dc59bdd G |
276 | #ifndef IO_SPACE_LIMIT |
277 | #define IO_SPACE_LIMIT 0xffff | |
278 | #endif | |
3f7e212d AB |
279 | |
280 | #ifdef __KERNEL__ | |
281 | ||
282 | #include <linux/vmalloc.h> | |
283 | #define __io_virt(x) ((void __force *) (x)) | |
284 | ||
285 | #ifndef CONFIG_GENERIC_IOMAP | |
286 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | |
287 | struct pci_dev; | |
288 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); | |
289 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) | |
290 | { | |
291 | } | |
292 | #endif /* CONFIG_GENERIC_IOMAP */ | |
293 | ||
294 | /* | |
295 | * Change virtual addresses to physical addresses and vv. | |
296 | * These are pretty trivial | |
297 | */ | |
298 | static inline unsigned long virt_to_phys(volatile void *address) | |
299 | { | |
300 | return __pa((unsigned long)address); | |
301 | } | |
302 | ||
303 | static inline void *phys_to_virt(unsigned long address) | |
304 | { | |
305 | return __va(address); | |
306 | } | |
307 | ||
308 | /* | |
309 | * Change "struct page" to physical address. | |
f1ecc698 JB |
310 | * |
311 | * This implementation is for the no-MMU case only... if you have an MMU | |
312 | * you'll need to provide your own definitions. | |
3f7e212d | 313 | */ |
f1ecc698 | 314 | #ifndef CONFIG_MMU |
3f7e212d AB |
315 | static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) |
316 | { | |
317 | return (void __iomem*) (unsigned long)offset; | |
318 | } | |
319 | ||
320 | #define __ioremap(offset, size, flags) ioremap(offset, size) | |
321 | ||
322 | #ifndef ioremap_nocache | |
323 | #define ioremap_nocache ioremap | |
324 | #endif | |
325 | ||
326 | #ifndef ioremap_wc | |
327 | #define ioremap_wc ioremap_nocache | |
328 | #endif | |
329 | ||
330 | static inline void iounmap(void *addr) | |
331 | { | |
332 | } | |
f1ecc698 | 333 | #endif /* CONFIG_MMU */ |
3f7e212d | 334 | |
82ed223c | 335 | #ifdef CONFIG_HAS_IOPORT |
3f7e212d AB |
336 | #ifndef CONFIG_GENERIC_IOMAP |
337 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) | |
338 | { | |
339 | return (void __iomem *) port; | |
340 | } | |
341 | ||
342 | static inline void ioport_unmap(void __iomem *p) | |
343 | { | |
344 | } | |
345 | #else /* CONFIG_GENERIC_IOMAP */ | |
346 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
347 | extern void ioport_unmap(void __iomem *p); | |
348 | #endif /* CONFIG_GENERIC_IOMAP */ | |
82ed223c | 349 | #endif /* CONFIG_HAS_IOPORT */ |
3f7e212d AB |
350 | |
351 | #define xlate_dev_kmem_ptr(p) p | |
f1ecc698 | 352 | #define xlate_dev_mem_ptr(p) __va(p) |
3f7e212d AB |
353 | |
354 | #ifndef virt_to_bus | |
355 | static inline unsigned long virt_to_bus(volatile void *address) | |
356 | { | |
357 | return ((unsigned long) address); | |
358 | } | |
359 | ||
360 | static inline void *bus_to_virt(unsigned long address) | |
361 | { | |
362 | return (void *) address; | |
363 | } | |
364 | #endif | |
365 | ||
366 | #define memset_io(a, b, c) memset(__io_virt(a), (b), (c)) | |
367 | #define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c)) | |
368 | #define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c)) | |
369 | ||
370 | #endif /* __KERNEL__ */ | |
371 | ||
372 | #endif /* __ASM_GENERIC_IO_H */ |