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1da177e4 LT |
1 | #ifndef _ASM_GENERIC_PGTABLE_H |
2 | #define _ASM_GENERIC_PGTABLE_H | |
3 | ||
f25748e3 DW |
4 | #include <linux/pfn.h> |
5 | ||
673eae82 | 6 | #ifndef __ASSEMBLY__ |
9535239f | 7 | #ifdef CONFIG_MMU |
673eae82 | 8 | |
fbd71844 | 9 | #include <linux/mm_types.h> |
187f1882 | 10 | #include <linux/bug.h> |
e61ce6ad | 11 | #include <linux/errno.h> |
fbd71844 | 12 | |
235a8f02 KS |
13 | #if 4 - defined(__PAGETABLE_PUD_FOLDED) - defined(__PAGETABLE_PMD_FOLDED) != \ |
14 | CONFIG_PGTABLE_LEVELS | |
15 | #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{PUD,PMD}_FOLDED | |
16 | #endif | |
17 | ||
6ee8630e HD |
18 | /* |
19 | * On almost all architectures and configurations, 0 can be used as the | |
20 | * upper ceiling to free_pgtables(): on many architectures it has the same | |
21 | * effect as using TASK_SIZE. However, there is one configuration which | |
22 | * must impose a more careful limit, to avoid freeing kernel pgtables. | |
23 | */ | |
24 | #ifndef USER_PGTABLES_CEILING | |
25 | #define USER_PGTABLES_CEILING 0UL | |
26 | #endif | |
27 | ||
1da177e4 | 28 | #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
e2cda322 AA |
29 | extern int ptep_set_access_flags(struct vm_area_struct *vma, |
30 | unsigned long address, pte_t *ptep, | |
31 | pte_t entry, int dirty); | |
32 | #endif | |
33 | ||
34 | #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS | |
bd5e88ad | 35 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
e2cda322 AA |
36 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, |
37 | unsigned long address, pmd_t *pmdp, | |
38 | pmd_t entry, int dirty); | |
bd5e88ad VG |
39 | #else |
40 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
41 | unsigned long address, pmd_t *pmdp, | |
42 | pmd_t entry, int dirty) | |
43 | { | |
44 | BUILD_BUG(); | |
45 | return 0; | |
46 | } | |
47 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1da177e4 LT |
48 | #endif |
49 | ||
50 | #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
e2cda322 AA |
51 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
52 | unsigned long address, | |
53 | pte_t *ptep) | |
54 | { | |
55 | pte_t pte = *ptep; | |
56 | int r = 1; | |
57 | if (!pte_young(pte)) | |
58 | r = 0; | |
59 | else | |
60 | set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); | |
61 | return r; | |
62 | } | |
63 | #endif | |
64 | ||
65 | #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
66 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
67 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
68 | unsigned long address, | |
69 | pmd_t *pmdp) | |
70 | { | |
71 | pmd_t pmd = *pmdp; | |
72 | int r = 1; | |
73 | if (!pmd_young(pmd)) | |
74 | r = 0; | |
75 | else | |
76 | set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); | |
77 | return r; | |
78 | } | |
bd5e88ad | 79 | #else |
e2cda322 AA |
80 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, |
81 | unsigned long address, | |
82 | pmd_t *pmdp) | |
83 | { | |
bd5e88ad | 84 | BUILD_BUG(); |
e2cda322 AA |
85 | return 0; |
86 | } | |
87 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1da177e4 LT |
88 | #endif |
89 | ||
90 | #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
e2cda322 AA |
91 | int ptep_clear_flush_young(struct vm_area_struct *vma, |
92 | unsigned long address, pte_t *ptep); | |
93 | #endif | |
94 | ||
95 | #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
bd5e88ad VG |
96 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
97 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
98 | unsigned long address, pmd_t *pmdp); | |
99 | #else | |
100 | /* | |
101 | * Despite relevant to THP only, this API is called from generic rmap code | |
102 | * under PageTransHuge(), hence needs a dummy implementation for !THP | |
103 | */ | |
104 | static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
105 | unsigned long address, pmd_t *pmdp) | |
106 | { | |
107 | BUILD_BUG(); | |
108 | return 0; | |
109 | } | |
110 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1da177e4 LT |
111 | #endif |
112 | ||
1da177e4 | 113 | #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR |
e2cda322 AA |
114 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
115 | unsigned long address, | |
116 | pte_t *ptep) | |
117 | { | |
118 | pte_t pte = *ptep; | |
119 | pte_clear(mm, address, ptep); | |
120 | return pte; | |
121 | } | |
122 | #endif | |
123 | ||
8809aa2d | 124 | #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
e2cda322 | 125 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
8809aa2d AK |
126 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
127 | unsigned long address, | |
128 | pmd_t *pmdp) | |
e2cda322 AA |
129 | { |
130 | pmd_t pmd = *pmdp; | |
2d28a227 | 131 | pmd_clear(pmdp); |
e2cda322 | 132 | return pmd; |
49b24d6b | 133 | } |
e2cda322 | 134 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1da177e4 LT |
135 | #endif |
136 | ||
8809aa2d | 137 | #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
fcbe08d6 | 138 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
8809aa2d | 139 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, |
fcbe08d6 MS |
140 | unsigned long address, pmd_t *pmdp, |
141 | int full) | |
142 | { | |
8809aa2d | 143 | return pmdp_huge_get_and_clear(mm, address, pmdp); |
fcbe08d6 MS |
144 | } |
145 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
146 | #endif | |
147 | ||
a600388d | 148 | #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
e2cda322 AA |
149 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, |
150 | unsigned long address, pte_t *ptep, | |
151 | int full) | |
152 | { | |
153 | pte_t pte; | |
154 | pte = ptep_get_and_clear(mm, address, ptep); | |
155 | return pte; | |
156 | } | |
a600388d ZA |
157 | #endif |
158 | ||
9888a1ca ZA |
159 | /* |
160 | * Some architectures may be able to avoid expensive synchronization | |
161 | * primitives when modifications are made to PTE's which are already | |
162 | * not present, or in the process of an address space destruction. | |
163 | */ | |
164 | #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL | |
e2cda322 AA |
165 | static inline void pte_clear_not_present_full(struct mm_struct *mm, |
166 | unsigned long address, | |
167 | pte_t *ptep, | |
168 | int full) | |
169 | { | |
170 | pte_clear(mm, address, ptep); | |
171 | } | |
a600388d ZA |
172 | #endif |
173 | ||
1da177e4 | 174 | #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH |
e2cda322 AA |
175 | extern pte_t ptep_clear_flush(struct vm_area_struct *vma, |
176 | unsigned long address, | |
177 | pte_t *ptep); | |
178 | #endif | |
179 | ||
8809aa2d AK |
180 | #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
181 | extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
e2cda322 AA |
182 | unsigned long address, |
183 | pmd_t *pmdp); | |
1da177e4 LT |
184 | #endif |
185 | ||
186 | #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT | |
8c65b4a6 | 187 | struct mm_struct; |
1da177e4 LT |
188 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) |
189 | { | |
190 | pte_t old_pte = *ptep; | |
191 | set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); | |
192 | } | |
193 | #endif | |
194 | ||
d511ead1 AK |
195 | #ifndef pte_savedwrite |
196 | #define pte_savedwrite pte_write | |
197 | #endif | |
198 | ||
199 | #ifndef pte_mk_savedwrite | |
200 | #define pte_mk_savedwrite pte_mkwrite | |
201 | #endif | |
202 | ||
737f3a90 AK |
203 | #ifndef pte_clear_savedwrite |
204 | #define pte_clear_savedwrite pte_wrprotect | |
205 | #endif | |
206 | ||
d511ead1 AK |
207 | #ifndef pmd_savedwrite |
208 | #define pmd_savedwrite pmd_write | |
209 | #endif | |
210 | ||
211 | #ifndef pmd_mk_savedwrite | |
212 | #define pmd_mk_savedwrite pmd_mkwrite | |
213 | #endif | |
214 | ||
737f3a90 AK |
215 | #ifndef pmd_clear_savedwrite |
216 | #define pmd_clear_savedwrite pmd_wrprotect | |
217 | #endif | |
218 | ||
e2cda322 AA |
219 | #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT |
220 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
221 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
222 | unsigned long address, pmd_t *pmdp) | |
223 | { | |
224 | pmd_t old_pmd = *pmdp; | |
225 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); | |
226 | } | |
bd5e88ad | 227 | #else |
e2cda322 AA |
228 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, |
229 | unsigned long address, pmd_t *pmdp) | |
230 | { | |
bd5e88ad | 231 | BUILD_BUG(); |
e2cda322 AA |
232 | } |
233 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
234 | #endif | |
235 | ||
15a25b2e AK |
236 | #ifndef pmdp_collapse_flush |
237 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
f28b6ff8 AK |
238 | extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
239 | unsigned long address, pmd_t *pmdp); | |
15a25b2e AK |
240 | #else |
241 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, | |
242 | unsigned long address, | |
243 | pmd_t *pmdp) | |
244 | { | |
245 | BUILD_BUG(); | |
246 | return *pmdp; | |
247 | } | |
248 | #define pmdp_collapse_flush pmdp_collapse_flush | |
249 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
250 | #endif | |
251 | ||
e3ebcf64 | 252 | #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT |
6b0b50b0 AK |
253 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
254 | pgtable_t pgtable); | |
e3ebcf64 GS |
255 | #endif |
256 | ||
257 | #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 258 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
e3ebcf64 GS |
259 | #endif |
260 | ||
46dcde73 GS |
261 | #ifndef __HAVE_ARCH_PMDP_INVALIDATE |
262 | extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, | |
263 | pmd_t *pmdp); | |
264 | #endif | |
265 | ||
c777e2a8 AK |
266 | #ifndef __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE |
267 | static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, | |
268 | unsigned long address, pmd_t *pmdp) | |
269 | { | |
270 | ||
271 | } | |
272 | #endif | |
273 | ||
1da177e4 | 274 | #ifndef __HAVE_ARCH_PTE_SAME |
e2cda322 AA |
275 | static inline int pte_same(pte_t pte_a, pte_t pte_b) |
276 | { | |
277 | return pte_val(pte_a) == pte_val(pte_b); | |
278 | } | |
279 | #endif | |
280 | ||
45961722 KW |
281 | #ifndef __HAVE_ARCH_PTE_UNUSED |
282 | /* | |
283 | * Some architectures provide facilities to virtualization guests | |
284 | * so that they can flag allocated pages as unused. This allows the | |
285 | * host to transparently reclaim unused pages. This function returns | |
286 | * whether the pte's page is unused. | |
287 | */ | |
288 | static inline int pte_unused(pte_t pte) | |
289 | { | |
290 | return 0; | |
291 | } | |
292 | #endif | |
293 | ||
e2cda322 AA |
294 | #ifndef __HAVE_ARCH_PMD_SAME |
295 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
296 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
297 | { | |
298 | return pmd_val(pmd_a) == pmd_val(pmd_b); | |
299 | } | |
300 | #else /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
301 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
302 | { | |
bd5e88ad | 303 | BUILD_BUG(); |
e2cda322 AA |
304 | return 0; |
305 | } | |
306 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1da177e4 LT |
307 | #endif |
308 | ||
1da177e4 LT |
309 | #ifndef __HAVE_ARCH_PGD_OFFSET_GATE |
310 | #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) | |
311 | #endif | |
312 | ||
0b0968a3 | 313 | #ifndef __HAVE_ARCH_MOVE_PTE |
8b1f3124 | 314 | #define move_pte(pte, prot, old_addr, new_addr) (pte) |
8b1f3124 NP |
315 | #endif |
316 | ||
2c3cf556 | 317 | #ifndef pte_accessible |
20841405 | 318 | # define pte_accessible(mm, pte) ((void)(pte), 1) |
2c3cf556 RR |
319 | #endif |
320 | ||
61c77326 SL |
321 | #ifndef flush_tlb_fix_spurious_fault |
322 | #define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address) | |
323 | #endif | |
324 | ||
0634a632 PM |
325 | #ifndef pgprot_noncached |
326 | #define pgprot_noncached(prot) (prot) | |
327 | #endif | |
328 | ||
2520bd31 | 329 | #ifndef pgprot_writecombine |
330 | #define pgprot_writecombine pgprot_noncached | |
331 | #endif | |
332 | ||
d1b4bfbf TK |
333 | #ifndef pgprot_writethrough |
334 | #define pgprot_writethrough pgprot_noncached | |
335 | #endif | |
336 | ||
8b921acf LD |
337 | #ifndef pgprot_device |
338 | #define pgprot_device pgprot_noncached | |
339 | #endif | |
340 | ||
64e45507 PF |
341 | #ifndef pgprot_modify |
342 | #define pgprot_modify pgprot_modify | |
343 | static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) | |
344 | { | |
345 | if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) | |
346 | newprot = pgprot_noncached(newprot); | |
347 | if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) | |
348 | newprot = pgprot_writecombine(newprot); | |
349 | if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) | |
350 | newprot = pgprot_device(newprot); | |
351 | return newprot; | |
352 | } | |
353 | #endif | |
354 | ||
1da177e4 | 355 | /* |
8f6c99c1 HD |
356 | * When walking page tables, get the address of the next boundary, |
357 | * or the end address of the range if that comes earlier. Although no | |
358 | * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. | |
1da177e4 LT |
359 | */ |
360 | ||
1da177e4 LT |
361 | #define pgd_addr_end(addr, end) \ |
362 | ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ | |
363 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
364 | }) | |
1da177e4 LT |
365 | |
366 | #ifndef pud_addr_end | |
367 | #define pud_addr_end(addr, end) \ | |
368 | ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ | |
369 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
370 | }) | |
371 | #endif | |
372 | ||
373 | #ifndef pmd_addr_end | |
374 | #define pmd_addr_end(addr, end) \ | |
375 | ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ | |
376 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
377 | }) | |
378 | #endif | |
379 | ||
1da177e4 LT |
380 | /* |
381 | * When walking page tables, we usually want to skip any p?d_none entries; | |
382 | * and any p?d_bad entries - reporting the error before resetting to none. | |
383 | * Do the tests inline, but report and clear the bad entry in mm/memory.c. | |
384 | */ | |
385 | void pgd_clear_bad(pgd_t *); | |
386 | void pud_clear_bad(pud_t *); | |
387 | void pmd_clear_bad(pmd_t *); | |
388 | ||
389 | static inline int pgd_none_or_clear_bad(pgd_t *pgd) | |
390 | { | |
391 | if (pgd_none(*pgd)) | |
392 | return 1; | |
393 | if (unlikely(pgd_bad(*pgd))) { | |
394 | pgd_clear_bad(pgd); | |
395 | return 1; | |
396 | } | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static inline int pud_none_or_clear_bad(pud_t *pud) | |
401 | { | |
402 | if (pud_none(*pud)) | |
403 | return 1; | |
404 | if (unlikely(pud_bad(*pud))) { | |
405 | pud_clear_bad(pud); | |
406 | return 1; | |
407 | } | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static inline int pmd_none_or_clear_bad(pmd_t *pmd) | |
412 | { | |
413 | if (pmd_none(*pmd)) | |
414 | return 1; | |
415 | if (unlikely(pmd_bad(*pmd))) { | |
416 | pmd_clear_bad(pmd); | |
417 | return 1; | |
418 | } | |
419 | return 0; | |
420 | } | |
9535239f | 421 | |
1ea0704e JF |
422 | static inline pte_t __ptep_modify_prot_start(struct mm_struct *mm, |
423 | unsigned long addr, | |
424 | pte_t *ptep) | |
425 | { | |
426 | /* | |
427 | * Get the current pte state, but zero it out to make it | |
428 | * non-present, preventing the hardware from asynchronously | |
429 | * updating it. | |
430 | */ | |
431 | return ptep_get_and_clear(mm, addr, ptep); | |
432 | } | |
433 | ||
434 | static inline void __ptep_modify_prot_commit(struct mm_struct *mm, | |
435 | unsigned long addr, | |
436 | pte_t *ptep, pte_t pte) | |
437 | { | |
438 | /* | |
439 | * The pte is non-present, so there's no hardware state to | |
440 | * preserve. | |
441 | */ | |
442 | set_pte_at(mm, addr, ptep, pte); | |
443 | } | |
444 | ||
445 | #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
446 | /* | |
447 | * Start a pte protection read-modify-write transaction, which | |
448 | * protects against asynchronous hardware modifications to the pte. | |
449 | * The intention is not to prevent the hardware from making pte | |
450 | * updates, but to prevent any updates it may make from being lost. | |
451 | * | |
452 | * This does not protect against other software modifications of the | |
453 | * pte; the appropriate pte lock must be held over the transation. | |
454 | * | |
455 | * Note that this interface is intended to be batchable, meaning that | |
456 | * ptep_modify_prot_commit may not actually update the pte, but merely | |
457 | * queue the update to be done at some later time. The update must be | |
458 | * actually committed before the pte lock is released, however. | |
459 | */ | |
460 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, | |
461 | unsigned long addr, | |
462 | pte_t *ptep) | |
463 | { | |
464 | return __ptep_modify_prot_start(mm, addr, ptep); | |
465 | } | |
466 | ||
467 | /* | |
468 | * Commit an update to a pte, leaving any hardware-controlled bits in | |
469 | * the PTE unmodified. | |
470 | */ | |
471 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, | |
472 | unsigned long addr, | |
473 | pte_t *ptep, pte_t pte) | |
474 | { | |
475 | __ptep_modify_prot_commit(mm, addr, ptep, pte); | |
476 | } | |
477 | #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ | |
fe1a6875 | 478 | #endif /* CONFIG_MMU */ |
1ea0704e | 479 | |
9535239f GU |
480 | /* |
481 | * A facility to provide lazy MMU batching. This allows PTE updates and | |
482 | * page invalidations to be delayed until a call to leave lazy MMU mode | |
483 | * is issued. Some architectures may benefit from doing this, and it is | |
484 | * beneficial for both shadow and direct mode hypervisors, which may batch | |
485 | * the PTE updates which happen during this window. Note that using this | |
486 | * interface requires that read hazards be removed from the code. A read | |
487 | * hazard could result in the direct mode hypervisor case, since the actual | |
488 | * write to the page tables may not yet have taken place, so reads though | |
489 | * a raw PTE pointer after it has been modified are not guaranteed to be | |
490 | * up to date. This mode can only be entered and left under the protection of | |
491 | * the page table locks for all page tables which may be modified. In the UP | |
492 | * case, this is required so that preemption is disabled, and in the SMP case, | |
493 | * it must synchronize the delayed page table writes properly on other CPUs. | |
494 | */ | |
495 | #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
496 | #define arch_enter_lazy_mmu_mode() do {} while (0) | |
497 | #define arch_leave_lazy_mmu_mode() do {} while (0) | |
498 | #define arch_flush_lazy_mmu_mode() do {} while (0) | |
499 | #endif | |
500 | ||
501 | /* | |
7fd7d83d JF |
502 | * A facility to provide batching of the reload of page tables and |
503 | * other process state with the actual context switch code for | |
504 | * paravirtualized guests. By convention, only one of the batched | |
505 | * update (lazy) modes (CPU, MMU) should be active at any given time, | |
506 | * entry should never be nested, and entry and exits should always be | |
507 | * paired. This is for sanity of maintaining and reasoning about the | |
508 | * kernel code. In this case, the exit (end of the context switch) is | |
509 | * in architecture-specific code, and so doesn't need a generic | |
510 | * definition. | |
9535239f | 511 | */ |
7fd7d83d | 512 | #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 513 | #define arch_start_context_switch(prev) do {} while (0) |
9535239f GU |
514 | #endif |
515 | ||
0f8975ec PE |
516 | #ifndef CONFIG_HAVE_ARCH_SOFT_DIRTY |
517 | static inline int pte_soft_dirty(pte_t pte) | |
518 | { | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static inline int pmd_soft_dirty(pmd_t pmd) | |
523 | { | |
524 | return 0; | |
525 | } | |
526 | ||
527 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
528 | { | |
529 | return pte; | |
530 | } | |
531 | ||
532 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
533 | { | |
534 | return pmd; | |
535 | } | |
179ef71c | 536 | |
a7b76174 MS |
537 | static inline pte_t pte_clear_soft_dirty(pte_t pte) |
538 | { | |
539 | return pte; | |
540 | } | |
541 | ||
542 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
543 | { | |
544 | return pmd; | |
545 | } | |
546 | ||
179ef71c CG |
547 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) |
548 | { | |
549 | return pte; | |
550 | } | |
551 | ||
552 | static inline int pte_swp_soft_dirty(pte_t pte) | |
553 | { | |
554 | return 0; | |
555 | } | |
556 | ||
557 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) | |
558 | { | |
559 | return pte; | |
560 | } | |
0f8975ec PE |
561 | #endif |
562 | ||
34801ba9 | 563 | #ifndef __HAVE_PFNMAP_TRACKING |
564 | /* | |
5180da41 SS |
565 | * Interfaces that can be used by architecture code to keep track of |
566 | * memory type of pfn mappings specified by the remap_pfn_range, | |
567 | * vm_insert_pfn. | |
568 | */ | |
569 | ||
570 | /* | |
571 | * track_pfn_remap is called when a _new_ pfn mapping is being established | |
572 | * by remap_pfn_range() for physical range indicated by pfn and size. | |
34801ba9 | 573 | */ |
5180da41 | 574 | static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, |
b3b9c293 KK |
575 | unsigned long pfn, unsigned long addr, |
576 | unsigned long size) | |
34801ba9 | 577 | { |
578 | return 0; | |
579 | } | |
580 | ||
581 | /* | |
5180da41 SS |
582 | * track_pfn_insert is called when a _new_ single pfn is established |
583 | * by vm_insert_pfn(). | |
584 | */ | |
308a047c BP |
585 | static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, |
586 | pfn_t pfn) | |
5180da41 | 587 | { |
5180da41 SS |
588 | } |
589 | ||
590 | /* | |
591 | * track_pfn_copy is called when vma that is covering the pfnmap gets | |
34801ba9 | 592 | * copied through copy_page_range(). |
593 | */ | |
5180da41 | 594 | static inline int track_pfn_copy(struct vm_area_struct *vma) |
34801ba9 | 595 | { |
596 | return 0; | |
597 | } | |
598 | ||
599 | /* | |
d9fe4fab | 600 | * untrack_pfn is called while unmapping a pfnmap for a region. |
34801ba9 | 601 | * untrack can be called for a specific region indicated by pfn and size or |
5180da41 | 602 | * can be for the entire vma (in which case pfn, size are zero). |
34801ba9 | 603 | */ |
5180da41 SS |
604 | static inline void untrack_pfn(struct vm_area_struct *vma, |
605 | unsigned long pfn, unsigned long size) | |
34801ba9 | 606 | { |
607 | } | |
d9fe4fab TK |
608 | |
609 | /* | |
610 | * untrack_pfn_moved is called while mremapping a pfnmap for a new region. | |
611 | */ | |
612 | static inline void untrack_pfn_moved(struct vm_area_struct *vma) | |
613 | { | |
614 | } | |
34801ba9 | 615 | #else |
5180da41 | 616 | extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, |
b3b9c293 KK |
617 | unsigned long pfn, unsigned long addr, |
618 | unsigned long size); | |
308a047c BP |
619 | extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, |
620 | pfn_t pfn); | |
5180da41 SS |
621 | extern int track_pfn_copy(struct vm_area_struct *vma); |
622 | extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, | |
623 | unsigned long size); | |
d9fe4fab | 624 | extern void untrack_pfn_moved(struct vm_area_struct *vma); |
34801ba9 | 625 | #endif |
626 | ||
816422ad KS |
627 | #ifdef __HAVE_COLOR_ZERO_PAGE |
628 | static inline int is_zero_pfn(unsigned long pfn) | |
629 | { | |
630 | extern unsigned long zero_pfn; | |
631 | unsigned long offset_from_zero_pfn = pfn - zero_pfn; | |
632 | return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); | |
633 | } | |
634 | ||
2f91ec8c KS |
635 | #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) |
636 | ||
816422ad KS |
637 | #else |
638 | static inline int is_zero_pfn(unsigned long pfn) | |
639 | { | |
640 | extern unsigned long zero_pfn; | |
641 | return pfn == zero_pfn; | |
642 | } | |
643 | ||
644 | static inline unsigned long my_zero_pfn(unsigned long addr) | |
645 | { | |
646 | extern unsigned long zero_pfn; | |
647 | return zero_pfn; | |
648 | } | |
649 | #endif | |
650 | ||
1a5a9906 AA |
651 | #ifdef CONFIG_MMU |
652 | ||
5f6e8da7 AA |
653 | #ifndef CONFIG_TRANSPARENT_HUGEPAGE |
654 | static inline int pmd_trans_huge(pmd_t pmd) | |
655 | { | |
656 | return 0; | |
657 | } | |
e2cda322 AA |
658 | #ifndef __HAVE_ARCH_PMD_WRITE |
659 | static inline int pmd_write(pmd_t pmd) | |
660 | { | |
661 | BUG(); | |
662 | return 0; | |
663 | } | |
664 | #endif /* __HAVE_ARCH_PMD_WRITE */ | |
1a5a9906 AA |
665 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
666 | ||
26c19178 AA |
667 | #ifndef pmd_read_atomic |
668 | static inline pmd_t pmd_read_atomic(pmd_t *pmdp) | |
669 | { | |
670 | /* | |
671 | * Depend on compiler for an atomic pmd read. NOTE: this is | |
672 | * only going to work, if the pmdval_t isn't larger than | |
673 | * an unsigned long. | |
674 | */ | |
675 | return *pmdp; | |
676 | } | |
677 | #endif | |
678 | ||
953c66c2 AK |
679 | #ifndef arch_needs_pgtable_deposit |
680 | #define arch_needs_pgtable_deposit() (false) | |
681 | #endif | |
1a5a9906 AA |
682 | /* |
683 | * This function is meant to be used by sites walking pagetables with | |
684 | * the mmap_sem hold in read mode to protect against MADV_DONTNEED and | |
685 | * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd | |
686 | * into a null pmd and the transhuge page fault can convert a null pmd | |
687 | * into an hugepmd or into a regular pmd (if the hugepage allocation | |
688 | * fails). While holding the mmap_sem in read mode the pmd becomes | |
689 | * stable and stops changing under us only if it's not null and not a | |
690 | * transhuge pmd. When those races occurs and this function makes a | |
691 | * difference vs the standard pmd_none_or_clear_bad, the result is | |
692 | * undefined so behaving like if the pmd was none is safe (because it | |
693 | * can return none anyway). The compiler level barrier() is critically | |
694 | * important to compute the two checks atomically on the same pmdval. | |
26c19178 AA |
695 | * |
696 | * For 32bit kernels with a 64bit large pmd_t this automatically takes | |
697 | * care of reading the pmd atomically to avoid SMP race conditions | |
698 | * against pmd_populate() when the mmap_sem is hold for reading by the | |
699 | * caller (a special atomic read not done by "gcc" as in the generic | |
700 | * version above, is also needed when THP is disabled because the page | |
701 | * fault can populate the pmd from under us). | |
1a5a9906 AA |
702 | */ |
703 | static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd) | |
704 | { | |
26c19178 | 705 | pmd_t pmdval = pmd_read_atomic(pmd); |
1a5a9906 AA |
706 | /* |
707 | * The barrier will stabilize the pmdval in a register or on | |
708 | * the stack so that it will stop changing under the code. | |
e4eed03f AA |
709 | * |
710 | * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE, | |
711 | * pmd_read_atomic is allowed to return a not atomic pmdval | |
712 | * (for example pointing to an hugepage that has never been | |
713 | * mapped in the pmd). The below checks will only care about | |
714 | * the low part of the pmd with 32bit PAE x86 anyway, with the | |
715 | * exception of pmd_none(). So the important thing is that if | |
716 | * the low part of the pmd is found null, the high part will | |
717 | * be also null or the pmd_none() check below would be | |
718 | * confused. | |
1a5a9906 AA |
719 | */ |
720 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
721 | barrier(); | |
722 | #endif | |
ee53664b | 723 | if (pmd_none(pmdval) || pmd_trans_huge(pmdval)) |
1a5a9906 AA |
724 | return 1; |
725 | if (unlikely(pmd_bad(pmdval))) { | |
ee53664b | 726 | pmd_clear_bad(pmd); |
1a5a9906 AA |
727 | return 1; |
728 | } | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* | |
733 | * This is a noop if Transparent Hugepage Support is not built into | |
734 | * the kernel. Otherwise it is equivalent to | |
735 | * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in | |
736 | * places that already verified the pmd is not none and they want to | |
737 | * walk ptes while holding the mmap sem in read mode (write mode don't | |
738 | * need this). If THP is not enabled, the pmd can't go away under the | |
739 | * code even if MADV_DONTNEED runs, but if THP is enabled we need to | |
740 | * run a pmd_trans_unstable before walking the ptes after | |
741 | * split_huge_page_pmd returns (because it may have run when the pmd | |
742 | * become null, but then a page fault can map in a THP and not a | |
743 | * regular page). | |
744 | */ | |
745 | static inline int pmd_trans_unstable(pmd_t *pmd) | |
746 | { | |
747 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
748 | return pmd_none_or_trans_huge_or_clear_bad(pmd); | |
749 | #else | |
750 | return 0; | |
5f6e8da7 | 751 | #endif |
1a5a9906 AA |
752 | } |
753 | ||
e7bb4b6d MG |
754 | #ifndef CONFIG_NUMA_BALANCING |
755 | /* | |
756 | * Technically a PTE can be PROTNONE even when not doing NUMA balancing but | |
757 | * the only case the kernel cares is for NUMA balancing and is only ever set | |
758 | * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked | |
759 | * _PAGE_PROTNONE so by by default, implement the helper as "always no". It | |
760 | * is the responsibility of the caller to distinguish between PROT_NONE | |
761 | * protections and NUMA hinting fault protections. | |
762 | */ | |
763 | static inline int pte_protnone(pte_t pte) | |
764 | { | |
765 | return 0; | |
766 | } | |
767 | ||
768 | static inline int pmd_protnone(pmd_t pmd) | |
769 | { | |
770 | return 0; | |
771 | } | |
772 | #endif /* CONFIG_NUMA_BALANCING */ | |
773 | ||
1a5a9906 | 774 | #endif /* CONFIG_MMU */ |
5f6e8da7 | 775 | |
e61ce6ad TK |
776 | #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP |
777 | int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); | |
778 | int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); | |
b9820d8f TK |
779 | int pud_clear_huge(pud_t *pud); |
780 | int pmd_clear_huge(pmd_t *pmd); | |
e61ce6ad TK |
781 | #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ |
782 | static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) | |
783 | { | |
784 | return 0; | |
785 | } | |
786 | static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) | |
787 | { | |
788 | return 0; | |
789 | } | |
b9820d8f TK |
790 | static inline int pud_clear_huge(pud_t *pud) |
791 | { | |
792 | return 0; | |
793 | } | |
794 | static inline int pmd_clear_huge(pmd_t *pmd) | |
795 | { | |
796 | return 0; | |
797 | } | |
e61ce6ad TK |
798 | #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ |
799 | ||
458aa76d AK |
800 | #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE |
801 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
802 | /* | |
803 | * ARCHes with special requirements for evicting THP backing TLB entries can | |
804 | * implement this. Otherwise also, it can help optimize normal TLB flush in | |
805 | * THP regime. stock flush_tlb_range() typically has optimization to nuke the | |
806 | * entire TLB TLB if flush span is greater than a threshold, which will | |
807 | * likely be true for a single huge page. Thus a single thp flush will | |
808 | * invalidate the entire TLB which is not desitable. | |
809 | * e.g. see arch/arc: flush_pmd_tlb_range | |
810 | */ | |
811 | #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) | |
812 | #else | |
813 | #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() | |
814 | #endif | |
815 | #endif | |
816 | ||
08ea8c07 BX |
817 | struct file; |
818 | int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, | |
819 | unsigned long size, pgprot_t *vma_prot); | |
1da177e4 LT |
820 | #endif /* !__ASSEMBLY__ */ |
821 | ||
40d158e6 AV |
822 | #ifndef io_remap_pfn_range |
823 | #define io_remap_pfn_range remap_pfn_range | |
824 | #endif | |
825 | ||
fd8cfd30 HD |
826 | #ifndef has_transparent_hugepage |
827 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
828 | #define has_transparent_hugepage() 1 | |
829 | #else | |
830 | #define has_transparent_hugepage() 0 | |
831 | #endif | |
832 | #endif | |
833 | ||
1da177e4 | 834 | #endif /* _ASM_GENERIC_PGTABLE_H */ |