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mm, x86: add support for PUD-sized transparent hugepages
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CommitLineData
1da177e4
LT
1#ifndef _ASM_GENERIC_PGTABLE_H
2#define _ASM_GENERIC_PGTABLE_H
3
f25748e3
DW
4#include <linux/pfn.h>
5
673eae82 6#ifndef __ASSEMBLY__
9535239f 7#ifdef CONFIG_MMU
673eae82 8
fbd71844 9#include <linux/mm_types.h>
187f1882 10#include <linux/bug.h>
e61ce6ad 11#include <linux/errno.h>
fbd71844 12
235a8f02
KS
13#if 4 - defined(__PAGETABLE_PUD_FOLDED) - defined(__PAGETABLE_PMD_FOLDED) != \
14 CONFIG_PGTABLE_LEVELS
15#error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{PUD,PMD}_FOLDED
16#endif
17
6ee8630e
HD
18/*
19 * On almost all architectures and configurations, 0 can be used as the
20 * upper ceiling to free_pgtables(): on many architectures it has the same
21 * effect as using TASK_SIZE. However, there is one configuration which
22 * must impose a more careful limit, to avoid freeing kernel pgtables.
23 */
24#ifndef USER_PGTABLES_CEILING
25#define USER_PGTABLES_CEILING 0UL
26#endif
27
1da177e4 28#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
e2cda322
AA
29extern int ptep_set_access_flags(struct vm_area_struct *vma,
30 unsigned long address, pte_t *ptep,
31 pte_t entry, int dirty);
32#endif
33
34#ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
bd5e88ad 35#ifdef CONFIG_TRANSPARENT_HUGEPAGE
e2cda322
AA
36extern int pmdp_set_access_flags(struct vm_area_struct *vma,
37 unsigned long address, pmd_t *pmdp,
38 pmd_t entry, int dirty);
a00cc7d9
MW
39extern int pudp_set_access_flags(struct vm_area_struct *vma,
40 unsigned long address, pud_t *pudp,
41 pud_t entry, int dirty);
bd5e88ad
VG
42#else
43static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
44 unsigned long address, pmd_t *pmdp,
45 pmd_t entry, int dirty)
46{
47 BUILD_BUG();
48 return 0;
49}
a00cc7d9
MW
50static inline int pudp_set_access_flags(struct vm_area_struct *vma,
51 unsigned long address, pud_t *pudp,
52 pud_t entry, int dirty)
53{
54 BUILD_BUG();
55 return 0;
56}
bd5e88ad 57#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
58#endif
59
60#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
e2cda322
AA
61static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
62 unsigned long address,
63 pte_t *ptep)
64{
65 pte_t pte = *ptep;
66 int r = 1;
67 if (!pte_young(pte))
68 r = 0;
69 else
70 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
71 return r;
72}
73#endif
74
75#ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
76#ifdef CONFIG_TRANSPARENT_HUGEPAGE
77static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
78 unsigned long address,
79 pmd_t *pmdp)
80{
81 pmd_t pmd = *pmdp;
82 int r = 1;
83 if (!pmd_young(pmd))
84 r = 0;
85 else
86 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
87 return r;
88}
bd5e88ad 89#else
e2cda322
AA
90static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
91 unsigned long address,
92 pmd_t *pmdp)
93{
bd5e88ad 94 BUILD_BUG();
e2cda322
AA
95 return 0;
96}
97#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
98#endif
99
100#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
e2cda322
AA
101int ptep_clear_flush_young(struct vm_area_struct *vma,
102 unsigned long address, pte_t *ptep);
103#endif
104
105#ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
bd5e88ad
VG
106#ifdef CONFIG_TRANSPARENT_HUGEPAGE
107extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
108 unsigned long address, pmd_t *pmdp);
109#else
110/*
111 * Despite relevant to THP only, this API is called from generic rmap code
112 * under PageTransHuge(), hence needs a dummy implementation for !THP
113 */
114static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
115 unsigned long address, pmd_t *pmdp)
116{
117 BUILD_BUG();
118 return 0;
119}
120#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
121#endif
122
1da177e4 123#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
e2cda322
AA
124static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
125 unsigned long address,
126 pte_t *ptep)
127{
128 pte_t pte = *ptep;
129 pte_clear(mm, address, ptep);
130 return pte;
131}
132#endif
133
e2cda322 134#ifdef CONFIG_TRANSPARENT_HUGEPAGE
a00cc7d9 135#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
8809aa2d
AK
136static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
137 unsigned long address,
138 pmd_t *pmdp)
e2cda322
AA
139{
140 pmd_t pmd = *pmdp;
2d28a227 141 pmd_clear(pmdp);
e2cda322 142 return pmd;
49b24d6b 143}
a00cc7d9
MW
144#endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */
145#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
146static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
147 unsigned long address,
148 pud_t *pudp)
149{
150 pud_t pud = *pudp;
151
152 pud_clear(pudp);
153 return pud;
154}
155#endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */
e2cda322 156#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4 157
fcbe08d6 158#ifdef CONFIG_TRANSPARENT_HUGEPAGE
a00cc7d9 159#ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
8809aa2d 160static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm,
fcbe08d6
MS
161 unsigned long address, pmd_t *pmdp,
162 int full)
163{
8809aa2d 164 return pmdp_huge_get_and_clear(mm, address, pmdp);
fcbe08d6 165}
fcbe08d6
MS
166#endif
167
a00cc7d9
MW
168#ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
169static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm,
170 unsigned long address, pud_t *pudp,
171 int full)
172{
173 return pudp_huge_get_and_clear(mm, address, pudp);
174}
175#endif
176#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
177
a600388d 178#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
e2cda322
AA
179static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
180 unsigned long address, pte_t *ptep,
181 int full)
182{
183 pte_t pte;
184 pte = ptep_get_and_clear(mm, address, ptep);
185 return pte;
186}
a600388d
ZA
187#endif
188
9888a1ca
ZA
189/*
190 * Some architectures may be able to avoid expensive synchronization
191 * primitives when modifications are made to PTE's which are already
192 * not present, or in the process of an address space destruction.
193 */
194#ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
e2cda322
AA
195static inline void pte_clear_not_present_full(struct mm_struct *mm,
196 unsigned long address,
197 pte_t *ptep,
198 int full)
199{
200 pte_clear(mm, address, ptep);
201}
a600388d
ZA
202#endif
203
1da177e4 204#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
e2cda322
AA
205extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
206 unsigned long address,
207 pte_t *ptep);
208#endif
209
8809aa2d
AK
210#ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
211extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
e2cda322
AA
212 unsigned long address,
213 pmd_t *pmdp);
a00cc7d9
MW
214extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
215 unsigned long address,
216 pud_t *pudp);
1da177e4
LT
217#endif
218
219#ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
8c65b4a6 220struct mm_struct;
1da177e4
LT
221static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
222{
223 pte_t old_pte = *ptep;
224 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
225}
226#endif
227
e2cda322
AA
228#ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
229#ifdef CONFIG_TRANSPARENT_HUGEPAGE
230static inline void pmdp_set_wrprotect(struct mm_struct *mm,
231 unsigned long address, pmd_t *pmdp)
232{
233 pmd_t old_pmd = *pmdp;
234 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
235}
bd5e88ad 236#else
e2cda322
AA
237static inline void pmdp_set_wrprotect(struct mm_struct *mm,
238 unsigned long address, pmd_t *pmdp)
239{
bd5e88ad 240 BUILD_BUG();
e2cda322
AA
241}
242#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
243#endif
a00cc7d9
MW
244#ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
245#ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
246static inline void pudp_set_wrprotect(struct mm_struct *mm,
247 unsigned long address, pud_t *pudp)
248{
249 pud_t old_pud = *pudp;
250
251 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud));
252}
253#else
254static inline void pudp_set_wrprotect(struct mm_struct *mm,
255 unsigned long address, pud_t *pudp)
256{
257 BUILD_BUG();
258}
259#endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
260#endif
e2cda322 261
15a25b2e
AK
262#ifndef pmdp_collapse_flush
263#ifdef CONFIG_TRANSPARENT_HUGEPAGE
f28b6ff8
AK
264extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
265 unsigned long address, pmd_t *pmdp);
15a25b2e
AK
266#else
267static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
268 unsigned long address,
269 pmd_t *pmdp)
270{
271 BUILD_BUG();
272 return *pmdp;
273}
274#define pmdp_collapse_flush pmdp_collapse_flush
275#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
276#endif
277
e3ebcf64 278#ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
6b0b50b0
AK
279extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
280 pgtable_t pgtable);
e3ebcf64
GS
281#endif
282
283#ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
6b0b50b0 284extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
e3ebcf64
GS
285#endif
286
46dcde73
GS
287#ifndef __HAVE_ARCH_PMDP_INVALIDATE
288extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
289 pmd_t *pmdp);
290#endif
291
c777e2a8
AK
292#ifndef __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
293static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
294 unsigned long address, pmd_t *pmdp)
295{
296
297}
298#endif
299
1da177e4 300#ifndef __HAVE_ARCH_PTE_SAME
e2cda322
AA
301static inline int pte_same(pte_t pte_a, pte_t pte_b)
302{
303 return pte_val(pte_a) == pte_val(pte_b);
304}
305#endif
306
45961722
KW
307#ifndef __HAVE_ARCH_PTE_UNUSED
308/*
309 * Some architectures provide facilities to virtualization guests
310 * so that they can flag allocated pages as unused. This allows the
311 * host to transparently reclaim unused pages. This function returns
312 * whether the pte's page is unused.
313 */
314static inline int pte_unused(pte_t pte)
315{
316 return 0;
317}
318#endif
319
e2cda322
AA
320#ifndef __HAVE_ARCH_PMD_SAME
321#ifdef CONFIG_TRANSPARENT_HUGEPAGE
322static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
323{
324 return pmd_val(pmd_a) == pmd_val(pmd_b);
325}
a00cc7d9
MW
326
327static inline int pud_same(pud_t pud_a, pud_t pud_b)
328{
329 return pud_val(pud_a) == pud_val(pud_b);
330}
e2cda322
AA
331#else /* CONFIG_TRANSPARENT_HUGEPAGE */
332static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
333{
bd5e88ad 334 BUILD_BUG();
e2cda322
AA
335 return 0;
336}
a00cc7d9
MW
337
338static inline int pud_same(pud_t pud_a, pud_t pud_b)
339{
340 BUILD_BUG();
341 return 0;
342}
e2cda322 343#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1da177e4
LT
344#endif
345
1da177e4
LT
346#ifndef __HAVE_ARCH_PGD_OFFSET_GATE
347#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
348#endif
349
0b0968a3 350#ifndef __HAVE_ARCH_MOVE_PTE
8b1f3124 351#define move_pte(pte, prot, old_addr, new_addr) (pte)
8b1f3124
NP
352#endif
353
2c3cf556 354#ifndef pte_accessible
20841405 355# define pte_accessible(mm, pte) ((void)(pte), 1)
2c3cf556
RR
356#endif
357
61c77326
SL
358#ifndef flush_tlb_fix_spurious_fault
359#define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address)
360#endif
361
0634a632
PM
362#ifndef pgprot_noncached
363#define pgprot_noncached(prot) (prot)
364#endif
365
2520bd31 366#ifndef pgprot_writecombine
367#define pgprot_writecombine pgprot_noncached
368#endif
369
d1b4bfbf
TK
370#ifndef pgprot_writethrough
371#define pgprot_writethrough pgprot_noncached
372#endif
373
8b921acf
LD
374#ifndef pgprot_device
375#define pgprot_device pgprot_noncached
376#endif
377
64e45507
PF
378#ifndef pgprot_modify
379#define pgprot_modify pgprot_modify
380static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
381{
382 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
383 newprot = pgprot_noncached(newprot);
384 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
385 newprot = pgprot_writecombine(newprot);
386 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
387 newprot = pgprot_device(newprot);
388 return newprot;
389}
390#endif
391
1da177e4 392/*
8f6c99c1
HD
393 * When walking page tables, get the address of the next boundary,
394 * or the end address of the range if that comes earlier. Although no
395 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
1da177e4
LT
396 */
397
1da177e4
LT
398#define pgd_addr_end(addr, end) \
399({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
400 (__boundary - 1 < (end) - 1)? __boundary: (end); \
401})
1da177e4
LT
402
403#ifndef pud_addr_end
404#define pud_addr_end(addr, end) \
405({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
406 (__boundary - 1 < (end) - 1)? __boundary: (end); \
407})
408#endif
409
410#ifndef pmd_addr_end
411#define pmd_addr_end(addr, end) \
412({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
413 (__boundary - 1 < (end) - 1)? __boundary: (end); \
414})
415#endif
416
1da177e4
LT
417/*
418 * When walking page tables, we usually want to skip any p?d_none entries;
419 * and any p?d_bad entries - reporting the error before resetting to none.
420 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
421 */
422void pgd_clear_bad(pgd_t *);
423void pud_clear_bad(pud_t *);
424void pmd_clear_bad(pmd_t *);
425
426static inline int pgd_none_or_clear_bad(pgd_t *pgd)
427{
428 if (pgd_none(*pgd))
429 return 1;
430 if (unlikely(pgd_bad(*pgd))) {
431 pgd_clear_bad(pgd);
432 return 1;
433 }
434 return 0;
435}
436
437static inline int pud_none_or_clear_bad(pud_t *pud)
438{
439 if (pud_none(*pud))
440 return 1;
441 if (unlikely(pud_bad(*pud))) {
442 pud_clear_bad(pud);
443 return 1;
444 }
445 return 0;
446}
447
448static inline int pmd_none_or_clear_bad(pmd_t *pmd)
449{
450 if (pmd_none(*pmd))
451 return 1;
452 if (unlikely(pmd_bad(*pmd))) {
453 pmd_clear_bad(pmd);
454 return 1;
455 }
456 return 0;
457}
9535239f 458
1ea0704e
JF
459static inline pte_t __ptep_modify_prot_start(struct mm_struct *mm,
460 unsigned long addr,
461 pte_t *ptep)
462{
463 /*
464 * Get the current pte state, but zero it out to make it
465 * non-present, preventing the hardware from asynchronously
466 * updating it.
467 */
468 return ptep_get_and_clear(mm, addr, ptep);
469}
470
471static inline void __ptep_modify_prot_commit(struct mm_struct *mm,
472 unsigned long addr,
473 pte_t *ptep, pte_t pte)
474{
475 /*
476 * The pte is non-present, so there's no hardware state to
477 * preserve.
478 */
479 set_pte_at(mm, addr, ptep, pte);
480}
481
482#ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
483/*
484 * Start a pte protection read-modify-write transaction, which
485 * protects against asynchronous hardware modifications to the pte.
486 * The intention is not to prevent the hardware from making pte
487 * updates, but to prevent any updates it may make from being lost.
488 *
489 * This does not protect against other software modifications of the
490 * pte; the appropriate pte lock must be held over the transation.
491 *
492 * Note that this interface is intended to be batchable, meaning that
493 * ptep_modify_prot_commit may not actually update the pte, but merely
494 * queue the update to be done at some later time. The update must be
495 * actually committed before the pte lock is released, however.
496 */
497static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
498 unsigned long addr,
499 pte_t *ptep)
500{
501 return __ptep_modify_prot_start(mm, addr, ptep);
502}
503
504/*
505 * Commit an update to a pte, leaving any hardware-controlled bits in
506 * the PTE unmodified.
507 */
508static inline void ptep_modify_prot_commit(struct mm_struct *mm,
509 unsigned long addr,
510 pte_t *ptep, pte_t pte)
511{
512 __ptep_modify_prot_commit(mm, addr, ptep, pte);
513}
514#endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
fe1a6875 515#endif /* CONFIG_MMU */
1ea0704e 516
9535239f
GU
517/*
518 * A facility to provide lazy MMU batching. This allows PTE updates and
519 * page invalidations to be delayed until a call to leave lazy MMU mode
520 * is issued. Some architectures may benefit from doing this, and it is
521 * beneficial for both shadow and direct mode hypervisors, which may batch
522 * the PTE updates which happen during this window. Note that using this
523 * interface requires that read hazards be removed from the code. A read
524 * hazard could result in the direct mode hypervisor case, since the actual
525 * write to the page tables may not yet have taken place, so reads though
526 * a raw PTE pointer after it has been modified are not guaranteed to be
527 * up to date. This mode can only be entered and left under the protection of
528 * the page table locks for all page tables which may be modified. In the UP
529 * case, this is required so that preemption is disabled, and in the SMP case,
530 * it must synchronize the delayed page table writes properly on other CPUs.
531 */
532#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
533#define arch_enter_lazy_mmu_mode() do {} while (0)
534#define arch_leave_lazy_mmu_mode() do {} while (0)
535#define arch_flush_lazy_mmu_mode() do {} while (0)
536#endif
537
538/*
7fd7d83d
JF
539 * A facility to provide batching of the reload of page tables and
540 * other process state with the actual context switch code for
541 * paravirtualized guests. By convention, only one of the batched
542 * update (lazy) modes (CPU, MMU) should be active at any given time,
543 * entry should never be nested, and entry and exits should always be
544 * paired. This is for sanity of maintaining and reasoning about the
545 * kernel code. In this case, the exit (end of the context switch) is
546 * in architecture-specific code, and so doesn't need a generic
547 * definition.
9535239f 548 */
7fd7d83d 549#ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
224101ed 550#define arch_start_context_switch(prev) do {} while (0)
9535239f
GU
551#endif
552
0f8975ec
PE
553#ifndef CONFIG_HAVE_ARCH_SOFT_DIRTY
554static inline int pte_soft_dirty(pte_t pte)
555{
556 return 0;
557}
558
559static inline int pmd_soft_dirty(pmd_t pmd)
560{
561 return 0;
562}
563
564static inline pte_t pte_mksoft_dirty(pte_t pte)
565{
566 return pte;
567}
568
569static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
570{
571 return pmd;
572}
179ef71c 573
a7b76174
MS
574static inline pte_t pte_clear_soft_dirty(pte_t pte)
575{
576 return pte;
577}
578
579static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
580{
581 return pmd;
582}
583
179ef71c
CG
584static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
585{
586 return pte;
587}
588
589static inline int pte_swp_soft_dirty(pte_t pte)
590{
591 return 0;
592}
593
594static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
595{
596 return pte;
597}
0f8975ec
PE
598#endif
599
34801ba9 600#ifndef __HAVE_PFNMAP_TRACKING
601/*
5180da41
SS
602 * Interfaces that can be used by architecture code to keep track of
603 * memory type of pfn mappings specified by the remap_pfn_range,
604 * vm_insert_pfn.
605 */
606
607/*
608 * track_pfn_remap is called when a _new_ pfn mapping is being established
609 * by remap_pfn_range() for physical range indicated by pfn and size.
34801ba9 610 */
5180da41 611static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
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612 unsigned long pfn, unsigned long addr,
613 unsigned long size)
34801ba9 614{
615 return 0;
616}
617
618/*
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619 * track_pfn_insert is called when a _new_ single pfn is established
620 * by vm_insert_pfn().
621 */
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622static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
623 pfn_t pfn)
5180da41 624{
5180da41
SS
625}
626
627/*
628 * track_pfn_copy is called when vma that is covering the pfnmap gets
34801ba9 629 * copied through copy_page_range().
630 */
5180da41 631static inline int track_pfn_copy(struct vm_area_struct *vma)
34801ba9 632{
633 return 0;
634}
635
636/*
d9fe4fab 637 * untrack_pfn is called while unmapping a pfnmap for a region.
34801ba9 638 * untrack can be called for a specific region indicated by pfn and size or
5180da41 639 * can be for the entire vma (in which case pfn, size are zero).
34801ba9 640 */
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641static inline void untrack_pfn(struct vm_area_struct *vma,
642 unsigned long pfn, unsigned long size)
34801ba9 643{
644}
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645
646/*
647 * untrack_pfn_moved is called while mremapping a pfnmap for a new region.
648 */
649static inline void untrack_pfn_moved(struct vm_area_struct *vma)
650{
651}
34801ba9 652#else
5180da41 653extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
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654 unsigned long pfn, unsigned long addr,
655 unsigned long size);
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656extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
657 pfn_t pfn);
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SS
658extern int track_pfn_copy(struct vm_area_struct *vma);
659extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
660 unsigned long size);
d9fe4fab 661extern void untrack_pfn_moved(struct vm_area_struct *vma);
34801ba9 662#endif
663
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664#ifdef __HAVE_COLOR_ZERO_PAGE
665static inline int is_zero_pfn(unsigned long pfn)
666{
667 extern unsigned long zero_pfn;
668 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
669 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
670}
671
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672#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
673
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674#else
675static inline int is_zero_pfn(unsigned long pfn)
676{
677 extern unsigned long zero_pfn;
678 return pfn == zero_pfn;
679}
680
681static inline unsigned long my_zero_pfn(unsigned long addr)
682{
683 extern unsigned long zero_pfn;
684 return zero_pfn;
685}
686#endif
687
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688#ifdef CONFIG_MMU
689
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690#ifndef CONFIG_TRANSPARENT_HUGEPAGE
691static inline int pmd_trans_huge(pmd_t pmd)
692{
693 return 0;
694}
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695#ifndef __HAVE_ARCH_PMD_WRITE
696static inline int pmd_write(pmd_t pmd)
697{
698 BUG();
699 return 0;
700}
701#endif /* __HAVE_ARCH_PMD_WRITE */
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702#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
703
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704#if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
705 (defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
706 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD))
707static inline int pud_trans_huge(pud_t pud)
708{
709 return 0;
710}
711#endif
712
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713#ifndef pmd_read_atomic
714static inline pmd_t pmd_read_atomic(pmd_t *pmdp)
715{
716 /*
717 * Depend on compiler for an atomic pmd read. NOTE: this is
718 * only going to work, if the pmdval_t isn't larger than
719 * an unsigned long.
720 */
721 return *pmdp;
722}
723#endif
724
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725#ifndef arch_needs_pgtable_deposit
726#define arch_needs_pgtable_deposit() (false)
727#endif
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728/*
729 * This function is meant to be used by sites walking pagetables with
730 * the mmap_sem hold in read mode to protect against MADV_DONTNEED and
731 * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd
732 * into a null pmd and the transhuge page fault can convert a null pmd
733 * into an hugepmd or into a regular pmd (if the hugepage allocation
734 * fails). While holding the mmap_sem in read mode the pmd becomes
735 * stable and stops changing under us only if it's not null and not a
736 * transhuge pmd. When those races occurs and this function makes a
737 * difference vs the standard pmd_none_or_clear_bad, the result is
738 * undefined so behaving like if the pmd was none is safe (because it
739 * can return none anyway). The compiler level barrier() is critically
740 * important to compute the two checks atomically on the same pmdval.
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741 *
742 * For 32bit kernels with a 64bit large pmd_t this automatically takes
743 * care of reading the pmd atomically to avoid SMP race conditions
744 * against pmd_populate() when the mmap_sem is hold for reading by the
745 * caller (a special atomic read not done by "gcc" as in the generic
746 * version above, is also needed when THP is disabled because the page
747 * fault can populate the pmd from under us).
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748 */
749static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd)
750{
26c19178 751 pmd_t pmdval = pmd_read_atomic(pmd);
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752 /*
753 * The barrier will stabilize the pmdval in a register or on
754 * the stack so that it will stop changing under the code.
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755 *
756 * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE,
757 * pmd_read_atomic is allowed to return a not atomic pmdval
758 * (for example pointing to an hugepage that has never been
759 * mapped in the pmd). The below checks will only care about
760 * the low part of the pmd with 32bit PAE x86 anyway, with the
761 * exception of pmd_none(). So the important thing is that if
762 * the low part of the pmd is found null, the high part will
763 * be also null or the pmd_none() check below would be
764 * confused.
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765 */
766#ifdef CONFIG_TRANSPARENT_HUGEPAGE
767 barrier();
768#endif
ee53664b 769 if (pmd_none(pmdval) || pmd_trans_huge(pmdval))
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770 return 1;
771 if (unlikely(pmd_bad(pmdval))) {
ee53664b 772 pmd_clear_bad(pmd);
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773 return 1;
774 }
775 return 0;
776}
777
778/*
779 * This is a noop if Transparent Hugepage Support is not built into
780 * the kernel. Otherwise it is equivalent to
781 * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in
782 * places that already verified the pmd is not none and they want to
783 * walk ptes while holding the mmap sem in read mode (write mode don't
784 * need this). If THP is not enabled, the pmd can't go away under the
785 * code even if MADV_DONTNEED runs, but if THP is enabled we need to
786 * run a pmd_trans_unstable before walking the ptes after
787 * split_huge_page_pmd returns (because it may have run when the pmd
788 * become null, but then a page fault can map in a THP and not a
789 * regular page).
790 */
791static inline int pmd_trans_unstable(pmd_t *pmd)
792{
793#ifdef CONFIG_TRANSPARENT_HUGEPAGE
794 return pmd_none_or_trans_huge_or_clear_bad(pmd);
795#else
796 return 0;
5f6e8da7 797#endif
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798}
799
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800#ifndef CONFIG_NUMA_BALANCING
801/*
802 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but
803 * the only case the kernel cares is for NUMA balancing and is only ever set
804 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked
805 * _PAGE_PROTNONE so by by default, implement the helper as "always no". It
806 * is the responsibility of the caller to distinguish between PROT_NONE
807 * protections and NUMA hinting fault protections.
808 */
809static inline int pte_protnone(pte_t pte)
810{
811 return 0;
812}
813
814static inline int pmd_protnone(pmd_t pmd)
815{
816 return 0;
817}
818#endif /* CONFIG_NUMA_BALANCING */
819
1a5a9906 820#endif /* CONFIG_MMU */
5f6e8da7 821
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822#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
823int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
824int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
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825int pud_clear_huge(pud_t *pud);
826int pmd_clear_huge(pmd_t *pmd);
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827#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
828static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
829{
830 return 0;
831}
832static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
833{
834 return 0;
835}
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836static inline int pud_clear_huge(pud_t *pud)
837{
838 return 0;
839}
840static inline int pmd_clear_huge(pmd_t *pmd)
841{
842 return 0;
843}
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844#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
845
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846#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
847#ifdef CONFIG_TRANSPARENT_HUGEPAGE
848/*
849 * ARCHes with special requirements for evicting THP backing TLB entries can
850 * implement this. Otherwise also, it can help optimize normal TLB flush in
851 * THP regime. stock flush_tlb_range() typically has optimization to nuke the
852 * entire TLB TLB if flush span is greater than a threshold, which will
853 * likely be true for a single huge page. Thus a single thp flush will
854 * invalidate the entire TLB which is not desitable.
855 * e.g. see arch/arc: flush_pmd_tlb_range
856 */
857#define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
a00cc7d9 858#define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
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859#else
860#define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
a00cc7d9 861#define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
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862#endif
863#endif
864
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865struct file;
866int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
867 unsigned long size, pgprot_t *vma_prot);
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868#endif /* !__ASSEMBLY__ */
869
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870#ifndef io_remap_pfn_range
871#define io_remap_pfn_range remap_pfn_range
872#endif
873
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874#ifndef has_transparent_hugepage
875#ifdef CONFIG_TRANSPARENT_HUGEPAGE
876#define has_transparent_hugepage() 1
877#else
878#define has_transparent_hugepage() 0
879#endif
880#endif
881
1da177e4 882#endif /* _ASM_GENERIC_PGTABLE_H */