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1da177e4 LT |
1 | #ifndef _ASM_IO_H |
2 | #define _ASM_IO_H | |
3 | ||
1da177e4 LT |
4 | #include <linux/string.h> |
5 | #include <linux/compiler.h> | |
6 | ||
7 | /* | |
8 | * This file contains the definitions for the x86 IO instructions | |
9 | * inb/inw/inl/outb/outw/outl and the "string versions" of the same | |
10 | * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" | |
11 | * versions of the single-IO instructions (inb_p/inw_p/..). | |
12 | * | |
13 | * This file is not meant to be obfuscating: it's just complicated | |
14 | * to (a) handle it all in a way that makes gcc able to optimize it | |
15 | * as well as possible and (b) trying to avoid writing the same thing | |
16 | * over and over again with slight variations and possibly making a | |
17 | * mistake somewhere. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * Thanks to James van Artsdalen for a better timing-fix than | |
22 | * the two short jumps: using outb's to a nonexistent port seems | |
23 | * to guarantee better timings even on fast machines. | |
24 | * | |
25 | * On the other hand, I'd like to be sure of a non-existent port: | |
26 | * I feel a bit unsafe about using 0x80 (should be safe, though) | |
27 | * | |
28 | * Linus | |
29 | */ | |
30 | ||
31 | /* | |
32 | * Bit simplified and optimized by Jan Hubicka | |
33 | * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. | |
34 | * | |
35 | * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, | |
36 | * isa_read[wl] and isa_write[wl] fixed | |
37 | * - Arnaldo Carvalho de Melo <acme@conectiva.com.br> | |
38 | */ | |
39 | ||
40 | #define IO_SPACE_LIMIT 0xffff | |
41 | ||
42 | #define XQUAD_PORTIO_BASE 0xfe400000 | |
43 | #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */ | |
44 | ||
45 | #ifdef __KERNEL__ | |
46 | ||
47 | #include <asm-generic/iomap.h> | |
48 | ||
49 | #include <linux/vmalloc.h> | |
50 | ||
51 | /* | |
52 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
53 | * access | |
54 | */ | |
55 | #define xlate_dev_mem_ptr(p) __va(p) | |
56 | ||
57 | /* | |
58 | * Convert a virtual cached pointer to an uncached pointer | |
59 | */ | |
60 | #define xlate_dev_kmem_ptr(p) p | |
61 | ||
62 | /** | |
63 | * virt_to_phys - map virtual addresses to physical | |
64 | * @address: address to remap | |
65 | * | |
66 | * The returned physical address is the physical (CPU) mapping for | |
67 | * the memory address given. It is only valid to use this function on | |
68 | * addresses directly mapped or allocated via kmalloc. | |
69 | * | |
70 | * This function does not give bus mappings for DMA transfers. In | |
71 | * almost all conceivable cases a device driver should not be using | |
72 | * this function | |
73 | */ | |
74 | ||
75 | static inline unsigned long virt_to_phys(volatile void * address) | |
76 | { | |
77 | return __pa(address); | |
78 | } | |
79 | ||
80 | /** | |
81 | * phys_to_virt - map physical address to virtual | |
82 | * @address: address to remap | |
83 | * | |
84 | * The returned virtual address is a current CPU mapping for | |
85 | * the memory address given. It is only valid to use this function on | |
86 | * addresses that have a kernel mapping | |
87 | * | |
88 | * This function does not handle bus mappings for DMA transfers. In | |
89 | * almost all conceivable cases a device driver should not be using | |
90 | * this function | |
91 | */ | |
92 | ||
93 | static inline void * phys_to_virt(unsigned long address) | |
94 | { | |
95 | return __va(address); | |
96 | } | |
97 | ||
98 | /* | |
99 | * Change "struct page" to physical address. | |
100 | */ | |
101 | #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) | |
102 | ||
103 | extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); | |
104 | ||
105 | /** | |
106 | * ioremap - map bus memory into CPU space | |
107 | * @offset: bus address of the memory | |
108 | * @size: size of the resource to map | |
109 | * | |
110 | * ioremap performs a platform specific sequence of operations to | |
111 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ | |
112 | * writew/writel functions and the other mmio helpers. The returned | |
113 | * address is not guaranteed to be usable directly as a virtual | |
114 | * address. | |
115 | */ | |
116 | ||
117 | static inline void __iomem * ioremap(unsigned long offset, unsigned long size) | |
118 | { | |
119 | return __ioremap(offset, size, 0); | |
120 | } | |
121 | ||
122 | extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); | |
123 | extern void iounmap(volatile void __iomem *addr); | |
124 | ||
125 | /* | |
126 | * bt_ioremap() and bt_iounmap() are for temporary early boot-time | |
127 | * mappings, before the real ioremap() is functional. | |
128 | * A boot-time mapping is currently limited to at most 16 pages. | |
129 | */ | |
130 | extern void *bt_ioremap(unsigned long offset, unsigned long size); | |
131 | extern void bt_iounmap(void *addr, unsigned long size); | |
18a8bd94 | 132 | extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys); |
1da177e4 | 133 | |
e9928674 AK |
134 | /* Use early IO mappings for DMI because it's initialized early */ |
135 | #define dmi_ioremap bt_ioremap | |
136 | #define dmi_iounmap bt_iounmap | |
137 | #define dmi_alloc alloc_bootmem | |
138 | ||
1da177e4 LT |
139 | /* |
140 | * ISA I/O bus memory addresses are 1:1 with the physical address. | |
141 | */ | |
142 | #define isa_virt_to_bus virt_to_phys | |
143 | #define isa_page_to_bus page_to_phys | |
144 | #define isa_bus_to_virt phys_to_virt | |
145 | ||
146 | /* | |
147 | * However PCI ones are not necessarily 1:1 and therefore these interfaces | |
148 | * are forbidden in portable PCI drivers. | |
149 | * | |
150 | * Allow them on x86 for legacy drivers, though. | |
151 | */ | |
152 | #define virt_to_bus virt_to_phys | |
153 | #define bus_to_virt phys_to_virt | |
154 | ||
155 | /* | |
156 | * readX/writeX() are used to access memory mapped devices. On some | |
157 | * architectures the memory mapped IO stuff needs to be accessed | |
158 | * differently. On the x86 architecture, we just read/write the | |
159 | * memory location directly. | |
160 | */ | |
161 | ||
162 | static inline unsigned char readb(const volatile void __iomem *addr) | |
163 | { | |
164 | return *(volatile unsigned char __force *) addr; | |
165 | } | |
166 | static inline unsigned short readw(const volatile void __iomem *addr) | |
167 | { | |
168 | return *(volatile unsigned short __force *) addr; | |
169 | } | |
170 | static inline unsigned int readl(const volatile void __iomem *addr) | |
171 | { | |
172 | return *(volatile unsigned int __force *) addr; | |
173 | } | |
174 | #define readb_relaxed(addr) readb(addr) | |
175 | #define readw_relaxed(addr) readw(addr) | |
176 | #define readl_relaxed(addr) readl(addr) | |
177 | #define __raw_readb readb | |
178 | #define __raw_readw readw | |
179 | #define __raw_readl readl | |
180 | ||
181 | static inline void writeb(unsigned char b, volatile void __iomem *addr) | |
182 | { | |
183 | *(volatile unsigned char __force *) addr = b; | |
184 | } | |
185 | static inline void writew(unsigned short b, volatile void __iomem *addr) | |
186 | { | |
187 | *(volatile unsigned short __force *) addr = b; | |
188 | } | |
189 | static inline void writel(unsigned int b, volatile void __iomem *addr) | |
190 | { | |
191 | *(volatile unsigned int __force *) addr = b; | |
192 | } | |
193 | #define __raw_writeb writeb | |
194 | #define __raw_writew writew | |
195 | #define __raw_writel writel | |
196 | ||
197 | #define mmiowb() | |
198 | ||
199 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) | |
200 | { | |
201 | memset((void __force *) addr, val, count); | |
202 | } | |
203 | static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) | |
204 | { | |
205 | __memcpy(dst, (void __force *) src, count); | |
206 | } | |
207 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) | |
208 | { | |
209 | __memcpy((void __force *) dst, src, count); | |
210 | } | |
211 | ||
212 | /* | |
213 | * ISA space is 'always mapped' on a typical x86 system, no need to | |
214 | * explicitly ioremap() it. The fact that the ISA IO space is mapped | |
215 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values | |
216 | * are physical addresses. The following constant pointer can be | |
217 | * used as the IO-area pointer (it can be iounmapped as well, so the | |
218 | * analogy with PCI is quite large): | |
219 | */ | |
220 | #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) | |
221 | ||
1da177e4 LT |
222 | /* |
223 | * Cache management | |
224 | * | |
225 | * This needed for two cases | |
226 | * 1. Out of order aware processors | |
227 | * 2. Accidentally out of order processors (PPro errata #51) | |
228 | */ | |
229 | ||
230 | #if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE) | |
231 | ||
232 | static inline void flush_write_buffers(void) | |
233 | { | |
234 | __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory"); | |
235 | } | |
236 | ||
237 | #define dma_cache_inv(_start,_size) flush_write_buffers() | |
238 | #define dma_cache_wback(_start,_size) flush_write_buffers() | |
239 | #define dma_cache_wback_inv(_start,_size) flush_write_buffers() | |
240 | ||
241 | #else | |
242 | ||
243 | /* Nothing to do */ | |
244 | ||
245 | #define dma_cache_inv(_start,_size) do { } while (0) | |
246 | #define dma_cache_wback(_start,_size) do { } while (0) | |
247 | #define dma_cache_wback_inv(_start,_size) do { } while (0) | |
248 | #define flush_write_buffers() | |
249 | ||
250 | #endif | |
251 | ||
252 | #endif /* __KERNEL__ */ | |
253 | ||
90a0a06a RR |
254 | static inline void native_io_delay(void) |
255 | { | |
256 | asm volatile("outb %%al,$0x80" : : : "memory"); | |
257 | } | |
258 | ||
d3561b7f RR |
259 | #if defined(CONFIG_PARAVIRT) |
260 | #include <asm/paravirt.h> | |
1da177e4 | 261 | #else |
d3561b7f | 262 | |
1da177e4 | 263 | static inline void slow_down_io(void) { |
90a0a06a | 264 | native_io_delay(); |
1da177e4 | 265 | #ifdef REALLY_SLOW_IO |
90a0a06a RR |
266 | native_io_delay(); |
267 | native_io_delay(); | |
268 | native_io_delay(); | |
1da177e4 | 269 | #endif |
1da177e4 LT |
270 | } |
271 | ||
d3561b7f RR |
272 | #endif |
273 | ||
1da177e4 LT |
274 | #ifdef CONFIG_X86_NUMAQ |
275 | extern void *xquad_portio; /* Where the IO area was mapped */ | |
276 | #define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port) | |
277 | #define __BUILDIO(bwl,bw,type) \ | |
278 | static inline void out##bwl##_quad(unsigned type value, int port, int quad) { \ | |
279 | if (xquad_portio) \ | |
280 | write##bwl(value, XQUAD_PORT_ADDR(port, quad)); \ | |
281 | else \ | |
282 | out##bwl##_local(value, port); \ | |
283 | } \ | |
284 | static inline void out##bwl(unsigned type value, int port) { \ | |
285 | out##bwl##_quad(value, port, 0); \ | |
286 | } \ | |
287 | static inline unsigned type in##bwl##_quad(int port, int quad) { \ | |
288 | if (xquad_portio) \ | |
289 | return read##bwl(XQUAD_PORT_ADDR(port, quad)); \ | |
290 | else \ | |
291 | return in##bwl##_local(port); \ | |
292 | } \ | |
293 | static inline unsigned type in##bwl(int port) { \ | |
294 | return in##bwl##_quad(port, 0); \ | |
295 | } | |
296 | #else | |
297 | #define __BUILDIO(bwl,bw,type) \ | |
298 | static inline void out##bwl(unsigned type value, int port) { \ | |
299 | out##bwl##_local(value, port); \ | |
300 | } \ | |
301 | static inline unsigned type in##bwl(int port) { \ | |
302 | return in##bwl##_local(port); \ | |
303 | } | |
304 | #endif | |
305 | ||
306 | ||
307 | #define BUILDIO(bwl,bw,type) \ | |
308 | static inline void out##bwl##_local(unsigned type value, int port) { \ | |
309 | __asm__ __volatile__("out" #bwl " %" #bw "0, %w1" : : "a"(value), "Nd"(port)); \ | |
310 | } \ | |
311 | static inline unsigned type in##bwl##_local(int port) { \ | |
312 | unsigned type value; \ | |
313 | __asm__ __volatile__("in" #bwl " %w1, %" #bw "0" : "=a"(value) : "Nd"(port)); \ | |
314 | return value; \ | |
315 | } \ | |
316 | static inline void out##bwl##_local_p(unsigned type value, int port) { \ | |
317 | out##bwl##_local(value, port); \ | |
318 | slow_down_io(); \ | |
319 | } \ | |
320 | static inline unsigned type in##bwl##_local_p(int port) { \ | |
321 | unsigned type value = in##bwl##_local(port); \ | |
322 | slow_down_io(); \ | |
323 | return value; \ | |
324 | } \ | |
325 | __BUILDIO(bwl,bw,type) \ | |
326 | static inline void out##bwl##_p(unsigned type value, int port) { \ | |
327 | out##bwl(value, port); \ | |
328 | slow_down_io(); \ | |
329 | } \ | |
330 | static inline unsigned type in##bwl##_p(int port) { \ | |
331 | unsigned type value = in##bwl(port); \ | |
332 | slow_down_io(); \ | |
333 | return value; \ | |
334 | } \ | |
335 | static inline void outs##bwl(int port, const void *addr, unsigned long count) { \ | |
336 | __asm__ __volatile__("rep; outs" #bwl : "+S"(addr), "+c"(count) : "d"(port)); \ | |
337 | } \ | |
338 | static inline void ins##bwl(int port, void *addr, unsigned long count) { \ | |
339 | __asm__ __volatile__("rep; ins" #bwl : "+D"(addr), "+c"(count) : "d"(port)); \ | |
340 | } | |
341 | ||
342 | BUILDIO(b,b,char) | |
343 | BUILDIO(w,w,short) | |
344 | BUILDIO(l,,int) | |
345 | ||
346 | #endif |