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1da177e4 LT |
1 | #ifndef __ASM_MACH_APIC_H |
2 | #define __ASM_MACH_APIC_H | |
3 | ||
1da177e4 LT |
4 | #include <asm/smp.h> |
5 | ||
6 | #define esr_disable (1) | |
7 | #define NO_BALANCE_IRQ (0) | |
8 | ||
1da177e4 LT |
9 | /* In clustered mode, the high nibble of APIC ID is a cluster number. |
10 | * The low nibble is a 4-bit bitmap. */ | |
11 | #define XAPIC_DEST_CPUS_SHIFT 4 | |
12 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) | |
13 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) | |
14 | ||
15 | #define APIC_DFR_VALUE (APIC_DFR_CLUSTER) | |
16 | ||
17 | static inline cpumask_t target_cpus(void) | |
18 | { | |
19 | /* CPU_MASK_ALL (0xff) has undefined behaviour with | |
20 | * dest_LowestPrio mode logical clustered apic interrupt routing | |
21 | * Just start on cpu 0. IRQ balancing will spread load | |
22 | */ | |
23 | return cpumask_of_cpu(0); | |
24 | } | |
25 | #define TARGET_CPUS (target_cpus()) | |
26 | ||
27 | #define INT_DELIVERY_MODE (dest_LowestPrio) | |
28 | #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ | |
29 | ||
30 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) | |
31 | { | |
32 | return 0; | |
33 | } | |
34 | ||
35 | /* we don't use the phys_cpu_present_map to indicate apicid presence */ | |
36 | static inline unsigned long check_apicid_present(int bit) | |
37 | { | |
38 | return 1; | |
39 | } | |
40 | ||
41 | #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) | |
42 | ||
43 | extern u8 bios_cpu_apicid[]; | |
44 | extern u8 cpu_2_logical_apicid[]; | |
45 | ||
46 | static inline void init_apic_ldr(void) | |
47 | { | |
48 | unsigned long val, id; | |
874c4fe3 | 49 | int count = 0; |
1da177e4 LT |
50 | u8 my_id = (u8)hard_smp_processor_id(); |
51 | u8 my_cluster = (u8)apicid_cluster(my_id); | |
874c4fe3 AK |
52 | #ifdef CONFIG_SMP |
53 | u8 lid; | |
54 | int i; | |
1da177e4 LT |
55 | |
56 | /* Create logical APIC IDs by counting CPUs already in cluster. */ | |
57 | for (count = 0, i = NR_CPUS; --i >= 0; ) { | |
58 | lid = cpu_2_logical_apicid[i]; | |
59 | if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster) | |
60 | ++count; | |
61 | } | |
874c4fe3 | 62 | #endif |
1da177e4 LT |
63 | /* We only have a 4 wide bitmap in cluster mode. If a deranged |
64 | * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ | |
65 | BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); | |
66 | id = my_cluster | (1UL << count); | |
67 | apic_write_around(APIC_DFR, APIC_DFR_VALUE); | |
68 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
69 | val |= SET_APIC_LOGICAL_ID(id); | |
70 | apic_write_around(APIC_LDR, val); | |
71 | } | |
72 | ||
73 | static inline int multi_timer_check(int apic, int irq) | |
74 | { | |
75 | return 0; | |
76 | } | |
77 | ||
78 | static inline int apic_id_registered(void) | |
79 | { | |
80 | return 1; | |
81 | } | |
82 | ||
83 | static inline void clustered_apic_check(void) | |
84 | { | |
85 | printk("Enabling APIC mode: Summit. Using %d I/O APICs\n", | |
86 | nr_ioapics); | |
87 | } | |
88 | ||
89 | static inline int apicid_to_node(int logical_apicid) | |
90 | { | |
3b08606d | 91 | return apicid_2_node[logical_apicid]; |
1da177e4 LT |
92 | } |
93 | ||
94 | /* Mapping from cpu number to logical apicid */ | |
95 | static inline int cpu_to_logical_apicid(int cpu) | |
96 | { | |
874c4fe3 | 97 | #ifdef CONFIG_SMP |
1da177e4 LT |
98 | if (cpu >= NR_CPUS) |
99 | return BAD_APICID; | |
100 | return (int)cpu_2_logical_apicid[cpu]; | |
874c4fe3 AK |
101 | #else |
102 | return logical_smp_processor_id(); | |
103 | #endif | |
1da177e4 LT |
104 | } |
105 | ||
106 | static inline int cpu_present_to_apicid(int mps_cpu) | |
107 | { | |
108 | if (mps_cpu < NR_CPUS) | |
109 | return (int)bios_cpu_apicid[mps_cpu]; | |
110 | else | |
111 | return BAD_APICID; | |
112 | } | |
113 | ||
114 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map) | |
115 | { | |
116 | /* For clustered we don't have a good way to do this yet - hack */ | |
117 | return physids_promote(0x0F); | |
118 | } | |
119 | ||
120 | static inline physid_mask_t apicid_to_cpu_present(int apicid) | |
121 | { | |
122 | return physid_mask_of_physid(0); | |
123 | } | |
124 | ||
125 | static inline int mpc_apic_id(struct mpc_config_processor *m, | |
126 | struct mpc_config_translation *translation_record) | |
127 | { | |
128 | printk("Processor #%d %ld:%ld APIC version %d\n", | |
129 | m->mpc_apicid, | |
130 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, | |
131 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, | |
132 | m->mpc_apicver); | |
133 | return (m->mpc_apicid); | |
134 | } | |
135 | ||
136 | static inline void setup_portio_remap(void) | |
137 | { | |
138 | } | |
139 | ||
140 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | |
141 | { | |
142 | return 1; | |
143 | } | |
144 | ||
145 | static inline void enable_apic_mode(void) | |
146 | { | |
147 | } | |
148 | ||
149 | static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) | |
150 | { | |
151 | int num_bits_set; | |
152 | int cpus_found = 0; | |
153 | int cpu; | |
154 | int apicid; | |
155 | ||
156 | num_bits_set = cpus_weight(cpumask); | |
157 | /* Return id to all */ | |
158 | if (num_bits_set == NR_CPUS) | |
159 | return (int) 0xFF; | |
160 | /* | |
161 | * The cpus in the mask must all be on the apic cluster. If are not | |
162 | * on the same apicid cluster return default value of TARGET_CPUS. | |
163 | */ | |
164 | cpu = first_cpu(cpumask); | |
165 | apicid = cpu_to_logical_apicid(cpu); | |
166 | while (cpus_found < num_bits_set) { | |
167 | if (cpu_isset(cpu, cpumask)) { | |
168 | int new_apicid = cpu_to_logical_apicid(cpu); | |
169 | if (apicid_cluster(apicid) != | |
170 | apicid_cluster(new_apicid)){ | |
171 | printk ("%s: Not a valid mask!\n",__FUNCTION__); | |
172 | return 0xFF; | |
173 | } | |
174 | apicid = apicid | new_apicid; | |
175 | cpus_found++; | |
176 | } | |
177 | cpu++; | |
178 | } | |
179 | return apicid; | |
180 | } | |
181 | ||
182 | /* cpuid returns the value latched in the HW at reset, not the APIC ID | |
183 | * register's value. For any box whose BIOS changes APIC IDs, like | |
184 | * clustered APIC systems, we must use hard_smp_processor_id. | |
185 | * | |
186 | * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID. | |
187 | */ | |
188 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) | |
189 | { | |
190 | return hard_smp_processor_id() >> index_msb; | |
191 | } | |
192 | ||
193 | #endif /* __ASM_MACH_APIC_H */ |