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1#ifndef __ASM_MSR_H
2#define __ASM_MSR_H
3
4/*
5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
8 */
9
10#define rdmsr(msr,val1,val2) \
11 __asm__ __volatile__("rdmsr" \
12 : "=a" (val1), "=d" (val2) \
13 : "c" (msr))
14
15#define wrmsr(msr,val1,val2) \
16 __asm__ __volatile__("wrmsr" \
17 : /* no outputs */ \
18 : "c" (msr), "a" (val1), "d" (val2))
19
20#define rdmsrl(msr,val) do { \
21 unsigned long l__,h__; \
22 rdmsr (msr, l__, h__); \
23 val = l__; \
24 val |= ((u64)h__<<32); \
25} while(0)
26
27static inline void wrmsrl (unsigned long msr, unsigned long long val)
28{
29 unsigned long lo, hi;
30 lo = (unsigned long) val;
31 hi = val >> 32;
32 wrmsr (msr, lo, hi);
33}
34
35/* wrmsr with exception handling */
36#define wrmsr_safe(msr,a,b) ({ int ret__; \
37 asm volatile("2: wrmsr ; xorl %0,%0\n" \
38 "1:\n\t" \
39 ".section .fixup,\"ax\"\n\t" \
40 "3: movl %4,%0 ; jmp 1b\n\t" \
41 ".previous\n\t" \
42 ".section __ex_table,\"a\"\n" \
43 " .align 4\n\t" \
44 " .long 2b,3b\n\t" \
45 ".previous" \
46 : "=a" (ret__) \
47 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
48 ret__; })
49
50#define rdtsc(low,high) \
51 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
52
53#define rdtscl(low) \
54 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
55
56#define rdtscll(val) \
57 __asm__ __volatile__("rdtsc" : "=A" (val))
58
59#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
60
61#define rdpmc(counter,low,high) \
62 __asm__ __volatile__("rdpmc" \
63 : "=a" (low), "=d" (high) \
64 : "c" (counter))
65
66/* symbolic names for some interesting MSRs */
67/* Intel defined MSRs. */
68#define MSR_IA32_P5_MC_ADDR 0
69#define MSR_IA32_P5_MC_TYPE 1
70#define MSR_IA32_PLATFORM_ID 0x17
71#define MSR_IA32_EBL_CR_POWERON 0x2a
72
73#define MSR_IA32_APICBASE 0x1b
74#define MSR_IA32_APICBASE_BSP (1<<8)
75#define MSR_IA32_APICBASE_ENABLE (1<<11)
76#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
77
78#define MSR_IA32_UCODE_WRITE 0x79
79#define MSR_IA32_UCODE_REV 0x8b
80
81#define MSR_P6_PERFCTR0 0xc1
82#define MSR_P6_PERFCTR1 0xc2
83
84#define MSR_IA32_BBL_CR_CTL 0x119
85
86#define MSR_IA32_SYSENTER_CS 0x174
87#define MSR_IA32_SYSENTER_ESP 0x175
88#define MSR_IA32_SYSENTER_EIP 0x176
89
90#define MSR_IA32_MCG_CAP 0x179
91#define MSR_IA32_MCG_STATUS 0x17a
92#define MSR_IA32_MCG_CTL 0x17b
93
94/* P4/Xeon+ specific */
95#define MSR_IA32_MCG_EAX 0x180
96#define MSR_IA32_MCG_EBX 0x181
97#define MSR_IA32_MCG_ECX 0x182
98#define MSR_IA32_MCG_EDX 0x183
99#define MSR_IA32_MCG_ESI 0x184
100#define MSR_IA32_MCG_EDI 0x185
101#define MSR_IA32_MCG_EBP 0x186
102#define MSR_IA32_MCG_ESP 0x187
103#define MSR_IA32_MCG_EFLAGS 0x188
104#define MSR_IA32_MCG_EIP 0x189
105#define MSR_IA32_MCG_RESERVED 0x18A
106
107#define MSR_P6_EVNTSEL0 0x186
108#define MSR_P6_EVNTSEL1 0x187
109
110#define MSR_IA32_PERF_STATUS 0x198
111#define MSR_IA32_PERF_CTL 0x199
112
113#define MSR_IA32_THERM_CONTROL 0x19a
114#define MSR_IA32_THERM_INTERRUPT 0x19b
115#define MSR_IA32_THERM_STATUS 0x19c
116#define MSR_IA32_MISC_ENABLE 0x1a0
117
118#define MSR_IA32_DEBUGCTLMSR 0x1d9
119#define MSR_IA32_LASTBRANCHFROMIP 0x1db
120#define MSR_IA32_LASTBRANCHTOIP 0x1dc
121#define MSR_IA32_LASTINTFROMIP 0x1dd
122#define MSR_IA32_LASTINTTOIP 0x1de
123
124#define MSR_IA32_MC0_CTL 0x400
125#define MSR_IA32_MC0_STATUS 0x401
126#define MSR_IA32_MC0_ADDR 0x402
127#define MSR_IA32_MC0_MISC 0x403
128
129/* Pentium IV performance counter MSRs */
130#define MSR_P4_BPU_PERFCTR0 0x300
131#define MSR_P4_BPU_PERFCTR1 0x301
132#define MSR_P4_BPU_PERFCTR2 0x302
133#define MSR_P4_BPU_PERFCTR3 0x303
134#define MSR_P4_MS_PERFCTR0 0x304
135#define MSR_P4_MS_PERFCTR1 0x305
136#define MSR_P4_MS_PERFCTR2 0x306
137#define MSR_P4_MS_PERFCTR3 0x307
138#define MSR_P4_FLAME_PERFCTR0 0x308
139#define MSR_P4_FLAME_PERFCTR1 0x309
140#define MSR_P4_FLAME_PERFCTR2 0x30a
141#define MSR_P4_FLAME_PERFCTR3 0x30b
142#define MSR_P4_IQ_PERFCTR0 0x30c
143#define MSR_P4_IQ_PERFCTR1 0x30d
144#define MSR_P4_IQ_PERFCTR2 0x30e
145#define MSR_P4_IQ_PERFCTR3 0x30f
146#define MSR_P4_IQ_PERFCTR4 0x310
147#define MSR_P4_IQ_PERFCTR5 0x311
148#define MSR_P4_BPU_CCCR0 0x360
149#define MSR_P4_BPU_CCCR1 0x361
150#define MSR_P4_BPU_CCCR2 0x362
151#define MSR_P4_BPU_CCCR3 0x363
152#define MSR_P4_MS_CCCR0 0x364
153#define MSR_P4_MS_CCCR1 0x365
154#define MSR_P4_MS_CCCR2 0x366
155#define MSR_P4_MS_CCCR3 0x367
156#define MSR_P4_FLAME_CCCR0 0x368
157#define MSR_P4_FLAME_CCCR1 0x369
158#define MSR_P4_FLAME_CCCR2 0x36a
159#define MSR_P4_FLAME_CCCR3 0x36b
160#define MSR_P4_IQ_CCCR0 0x36c
161#define MSR_P4_IQ_CCCR1 0x36d
162#define MSR_P4_IQ_CCCR2 0x36e
163#define MSR_P4_IQ_CCCR3 0x36f
164#define MSR_P4_IQ_CCCR4 0x370
165#define MSR_P4_IQ_CCCR5 0x371
166#define MSR_P4_ALF_ESCR0 0x3ca
167#define MSR_P4_ALF_ESCR1 0x3cb
168#define MSR_P4_BPU_ESCR0 0x3b2
169#define MSR_P4_BPU_ESCR1 0x3b3
170#define MSR_P4_BSU_ESCR0 0x3a0
171#define MSR_P4_BSU_ESCR1 0x3a1
172#define MSR_P4_CRU_ESCR0 0x3b8
173#define MSR_P4_CRU_ESCR1 0x3b9
174#define MSR_P4_CRU_ESCR2 0x3cc
175#define MSR_P4_CRU_ESCR3 0x3cd
176#define MSR_P4_CRU_ESCR4 0x3e0
177#define MSR_P4_CRU_ESCR5 0x3e1
178#define MSR_P4_DAC_ESCR0 0x3a8
179#define MSR_P4_DAC_ESCR1 0x3a9
180#define MSR_P4_FIRM_ESCR0 0x3a4
181#define MSR_P4_FIRM_ESCR1 0x3a5
182#define MSR_P4_FLAME_ESCR0 0x3a6
183#define MSR_P4_FLAME_ESCR1 0x3a7
184#define MSR_P4_FSB_ESCR0 0x3a2
185#define MSR_P4_FSB_ESCR1 0x3a3
186#define MSR_P4_IQ_ESCR0 0x3ba
187#define MSR_P4_IQ_ESCR1 0x3bb
188#define MSR_P4_IS_ESCR0 0x3b4
189#define MSR_P4_IS_ESCR1 0x3b5
190#define MSR_P4_ITLB_ESCR0 0x3b6
191#define MSR_P4_ITLB_ESCR1 0x3b7
192#define MSR_P4_IX_ESCR0 0x3c8
193#define MSR_P4_IX_ESCR1 0x3c9
194#define MSR_P4_MOB_ESCR0 0x3aa
195#define MSR_P4_MOB_ESCR1 0x3ab
196#define MSR_P4_MS_ESCR0 0x3c0
197#define MSR_P4_MS_ESCR1 0x3c1
198#define MSR_P4_PMH_ESCR0 0x3ac
199#define MSR_P4_PMH_ESCR1 0x3ad
200#define MSR_P4_RAT_ESCR0 0x3bc
201#define MSR_P4_RAT_ESCR1 0x3bd
202#define MSR_P4_SAAT_ESCR0 0x3ae
203#define MSR_P4_SAAT_ESCR1 0x3af
204#define MSR_P4_SSU_ESCR0 0x3be
205#define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
206#define MSR_P4_TBPU_ESCR0 0x3c2
207#define MSR_P4_TBPU_ESCR1 0x3c3
208#define MSR_P4_TC_ESCR0 0x3c4
209#define MSR_P4_TC_ESCR1 0x3c5
210#define MSR_P4_U2L_ESCR0 0x3b0
211#define MSR_P4_U2L_ESCR1 0x3b1
212
213/* AMD Defined MSRs */
214#define MSR_K6_EFER 0xC0000080
215#define MSR_K6_STAR 0xC0000081
216#define MSR_K6_WHCR 0xC0000082
217#define MSR_K6_UWCCR 0xC0000085
218#define MSR_K6_EPMR 0xC0000086
219#define MSR_K6_PSOR 0xC0000087
220#define MSR_K6_PFIR 0xC0000088
221
222#define MSR_K7_EVNTSEL0 0xC0010000
223#define MSR_K7_EVNTSEL1 0xC0010001
224#define MSR_K7_EVNTSEL2 0xC0010002
225#define MSR_K7_EVNTSEL3 0xC0010003
226#define MSR_K7_PERFCTR0 0xC0010004
227#define MSR_K7_PERFCTR1 0xC0010005
228#define MSR_K7_PERFCTR2 0xC0010006
229#define MSR_K7_PERFCTR3 0xC0010007
230#define MSR_K7_HWCR 0xC0010015
231#define MSR_K7_CLK_CTL 0xC001001b
232#define MSR_K7_FID_VID_CTL 0xC0010041
233#define MSR_K7_FID_VID_STATUS 0xC0010042
234
235/* extended feature register */
236#define MSR_EFER 0xc0000080
237
238/* EFER bits: */
239
240/* Execute Disable enable */
241#define _EFER_NX 11
242#define EFER_NX (1<<_EFER_NX)
243
244/* Centaur-Hauls/IDT defined MSRs. */
245#define MSR_IDT_FCR1 0x107
246#define MSR_IDT_FCR2 0x108
247#define MSR_IDT_FCR3 0x109
248#define MSR_IDT_FCR4 0x10a
249
250#define MSR_IDT_MCR0 0x110
251#define MSR_IDT_MCR1 0x111
252#define MSR_IDT_MCR2 0x112
253#define MSR_IDT_MCR3 0x113
254#define MSR_IDT_MCR4 0x114
255#define MSR_IDT_MCR5 0x115
256#define MSR_IDT_MCR6 0x116
257#define MSR_IDT_MCR7 0x117
258#define MSR_IDT_MCR_CTRL 0x120
259
260/* VIA Cyrix defined MSRs*/
261#define MSR_VIA_FCR 0x1107
262#define MSR_VIA_LONGHAUL 0x110a
263#define MSR_VIA_RNG 0x110b
264#define MSR_VIA_BCR2 0x1147
265
266/* Transmeta defined MSRs */
267#define MSR_TMTA_LONGRUN_CTRL 0x80868010
268#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
269#define MSR_TMTA_LRTI_READOUT 0x80868018
270#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
271
272#endif /* __ASM_MSR_H */