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1da177e4 LT |
1 | #ifndef _I386_PGTABLE_H |
2 | #define _I386_PGTABLE_H | |
3 | ||
1da177e4 LT |
4 | |
5 | /* | |
6 | * The Linux memory management assumes a three-level page table setup. On | |
7 | * the i386, we use that, but "fold" the mid level into the top-level page | |
8 | * table, so that we physically have the same two-level page table as the | |
9 | * i386 mmu expects. | |
10 | * | |
11 | * This file contains the functions and defines necessary to modify and use | |
12 | * the i386 page table tree. | |
13 | */ | |
14 | #ifndef __ASSEMBLY__ | |
15 | #include <asm/processor.h> | |
16 | #include <asm/fixmap.h> | |
17 | #include <linux/threads.h> | |
da181a8b | 18 | #include <asm/paravirt.h> |
1da177e4 LT |
19 | |
20 | #ifndef _I386_BITOPS_H | |
21 | #include <asm/bitops.h> | |
22 | #endif | |
23 | ||
24 | #include <linux/slab.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/spinlock.h> | |
27 | ||
8c65b4a6 TS |
28 | struct mm_struct; |
29 | struct vm_area_struct; | |
30 | ||
1da177e4 LT |
31 | /* |
32 | * ZERO_PAGE is a global shared page that is always zero: used | |
33 | * for zero-mapped memory areas etc.. | |
34 | */ | |
35 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | |
36 | extern unsigned long empty_zero_page[1024]; | |
37 | extern pgd_t swapper_pg_dir[1024]; | |
e18b890b CL |
38 | extern struct kmem_cache *pgd_cache; |
39 | extern struct kmem_cache *pmd_cache; | |
1da177e4 LT |
40 | extern spinlock_t pgd_lock; |
41 | extern struct page *pgd_list; | |
42 | ||
e18b890b CL |
43 | void pmd_ctor(void *, struct kmem_cache *, unsigned long); |
44 | void pgd_ctor(void *, struct kmem_cache *, unsigned long); | |
45 | void pgd_dtor(void *, struct kmem_cache *, unsigned long); | |
1da177e4 LT |
46 | void pgtable_cache_init(void); |
47 | void paging_init(void); | |
48 | ||
49 | /* | |
50 | * The Linux x86 paging architecture is 'compile-time dual-mode', it | |
51 | * implements both the traditional 2-level x86 page tables and the | |
52 | * newer 3-level PAE-mode page tables. | |
53 | */ | |
54 | #ifdef CONFIG_X86_PAE | |
55 | # include <asm/pgtable-3level-defs.h> | |
56 | # define PMD_SIZE (1UL << PMD_SHIFT) | |
57 | # define PMD_MASK (~(PMD_SIZE-1)) | |
58 | #else | |
59 | # include <asm/pgtable-2level-defs.h> | |
60 | #endif | |
61 | ||
62 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
63 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
64 | ||
65 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) | |
d455a369 | 66 | #define FIRST_USER_ADDRESS 0 |
1da177e4 LT |
67 | |
68 | #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) | |
69 | #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) | |
70 | ||
71 | #define TWOLEVEL_PGDIR_SHIFT 22 | |
72 | #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT) | |
73 | #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS) | |
74 | ||
75 | /* Just any arbitrary offset to the start of the vmalloc VM area: the | |
76 | * current 8MB value just means that there will be a 8MB "hole" after the | |
77 | * physical memory until the kernel virtual memory starts. That means that | |
78 | * any out-of-bounds memory accesses will hopefully be caught. | |
79 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | |
80 | * area for the same reason. ;) | |
81 | */ | |
82 | #define VMALLOC_OFFSET (8*1024*1024) | |
83 | #define VMALLOC_START (((unsigned long) high_memory + vmalloc_earlyreserve + \ | |
84 | 2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1)) | |
85 | #ifdef CONFIG_HIGHMEM | |
86 | # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) | |
87 | #else | |
88 | # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) | |
89 | #endif | |
90 | ||
91 | /* | |
9b4ee40e | 92 | * _PAGE_PSE set in the page directory entry just means that |
1da177e4 LT |
93 | * the page directory entry points directly to a 4MB-aligned block of |
94 | * memory. | |
95 | */ | |
96 | #define _PAGE_BIT_PRESENT 0 | |
97 | #define _PAGE_BIT_RW 1 | |
98 | #define _PAGE_BIT_USER 2 | |
99 | #define _PAGE_BIT_PWT 3 | |
100 | #define _PAGE_BIT_PCD 4 | |
101 | #define _PAGE_BIT_ACCESSED 5 | |
102 | #define _PAGE_BIT_DIRTY 6 | |
103 | #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */ | |
104 | #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */ | |
105 | #define _PAGE_BIT_UNUSED1 9 /* available for programmer */ | |
106 | #define _PAGE_BIT_UNUSED2 10 | |
107 | #define _PAGE_BIT_UNUSED3 11 | |
108 | #define _PAGE_BIT_NX 63 | |
109 | ||
110 | #define _PAGE_PRESENT 0x001 | |
111 | #define _PAGE_RW 0x002 | |
112 | #define _PAGE_USER 0x004 | |
113 | #define _PAGE_PWT 0x008 | |
114 | #define _PAGE_PCD 0x010 | |
115 | #define _PAGE_ACCESSED 0x020 | |
116 | #define _PAGE_DIRTY 0x040 | |
117 | #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */ | |
118 | #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */ | |
119 | #define _PAGE_UNUSED1 0x200 /* available for programmer */ | |
120 | #define _PAGE_UNUSED2 0x400 | |
121 | #define _PAGE_UNUSED3 0x800 | |
122 | ||
9b4ee40e PBG |
123 | /* If _PAGE_PRESENT is clear, we use these: */ |
124 | #define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */ | |
125 | #define _PAGE_PROTNONE 0x080 /* if the user mapped it with PROT_NONE; | |
126 | pte_present gives true */ | |
1da177e4 LT |
127 | #ifdef CONFIG_X86_PAE |
128 | #define _PAGE_NX (1ULL<<_PAGE_BIT_NX) | |
129 | #else | |
130 | #define _PAGE_NX 0 | |
131 | #endif | |
132 | ||
133 | #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY) | |
134 | #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) | |
135 | #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) | |
136 | ||
137 | #define PAGE_NONE \ | |
138 | __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED) | |
139 | #define PAGE_SHARED \ | |
140 | __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED) | |
141 | ||
142 | #define PAGE_SHARED_EXEC \ | |
143 | __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED) | |
144 | #define PAGE_COPY_NOEXEC \ | |
145 | __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX) | |
146 | #define PAGE_COPY_EXEC \ | |
147 | __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) | |
148 | #define PAGE_COPY \ | |
149 | PAGE_COPY_NOEXEC | |
150 | #define PAGE_READONLY \ | |
151 | __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX) | |
152 | #define PAGE_READONLY_EXEC \ | |
153 | __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) | |
154 | ||
155 | #define _PAGE_KERNEL \ | |
156 | (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX) | |
157 | #define _PAGE_KERNEL_EXEC \ | |
158 | (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED) | |
159 | ||
160 | extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC; | |
161 | #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW) | |
d01ad8dd | 162 | #define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW) |
1da177e4 LT |
163 | #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD) |
164 | #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) | |
165 | #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE) | |
166 | ||
167 | #define PAGE_KERNEL __pgprot(__PAGE_KERNEL) | |
168 | #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO) | |
169 | #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC) | |
d01ad8dd | 170 | #define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX) |
1da177e4 LT |
171 | #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE) |
172 | #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE) | |
173 | #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC) | |
174 | ||
175 | /* | |
176 | * The i386 can't do page protection for execute, and considers that | |
177 | * the same are read. Also, write permissions imply read permissions. | |
178 | * This is the closest we can get.. | |
179 | */ | |
180 | #define __P000 PAGE_NONE | |
181 | #define __P001 PAGE_READONLY | |
182 | #define __P010 PAGE_COPY | |
183 | #define __P011 PAGE_COPY | |
184 | #define __P100 PAGE_READONLY_EXEC | |
185 | #define __P101 PAGE_READONLY_EXEC | |
186 | #define __P110 PAGE_COPY_EXEC | |
187 | #define __P111 PAGE_COPY_EXEC | |
188 | ||
189 | #define __S000 PAGE_NONE | |
190 | #define __S001 PAGE_READONLY | |
191 | #define __S010 PAGE_SHARED | |
192 | #define __S011 PAGE_SHARED | |
193 | #define __S100 PAGE_READONLY_EXEC | |
194 | #define __S101 PAGE_READONLY_EXEC | |
195 | #define __S110 PAGE_SHARED_EXEC | |
196 | #define __S111 PAGE_SHARED_EXEC | |
197 | ||
198 | /* | |
199 | * Define this if things work differently on an i386 and an i486: | |
200 | * it will (on an i486) warn about kernel memory accesses that are | |
e49332bd | 201 | * done without a 'access_ok(VERIFY_WRITE,..)' |
1da177e4 | 202 | */ |
e49332bd | 203 | #undef TEST_ACCESS_OK |
1da177e4 LT |
204 | |
205 | /* The boot page tables (all created as a single array) */ | |
206 | extern unsigned long pg0[]; | |
207 | ||
208 | #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE)) | |
1da177e4 | 209 | |
705e87c0 HD |
210 | /* To avoid harmful races, pmd_none(x) should check only the lower when PAE */ |
211 | #define pmd_none(x) (!(unsigned long)pmd_val(x)) | |
1da177e4 | 212 | #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) |
1da177e4 LT |
213 | #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE) |
214 | ||
215 | ||
216 | #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) | |
217 | ||
218 | /* | |
219 | * The following only work if pte_present() is true. | |
220 | * Undefined behaviour if not.. | |
221 | */ | |
222 | static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; } | |
223 | static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; } | |
224 | static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; } | |
225 | static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } | |
226 | static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; } | |
8f860591 | 227 | static inline int pte_huge(pte_t pte) { return (pte).pte_low & _PAGE_PSE; } |
1da177e4 LT |
228 | |
229 | /* | |
230 | * The following only works if pte_present() is not true. | |
231 | */ | |
232 | static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; } | |
233 | ||
234 | static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; } | |
235 | static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; } | |
236 | static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; } | |
237 | static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; } | |
238 | static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; } | |
239 | static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; } | |
240 | static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; } | |
241 | static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; } | |
242 | static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; } | |
243 | static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; } | |
8f860591 | 244 | static inline pte_t pte_mkhuge(pte_t pte) { (pte).pte_low |= _PAGE_PSE; return pte; } |
1da177e4 LT |
245 | |
246 | #ifdef CONFIG_X86_PAE | |
247 | # include <asm/pgtable-3level.h> | |
248 | #else | |
249 | # include <asm/pgtable-2level.h> | |
250 | #endif | |
251 | ||
da181a8b | 252 | #ifndef CONFIG_PARAVIRT |
789e6ac0 ZA |
253 | /* |
254 | * Rules for using pte_update - it must be called after any PTE update which | |
255 | * has not been done using the set_pte / clear_pte interfaces. It is used by | |
256 | * shadow mode hypervisors to resynchronize the shadow page tables. Kernel PTE | |
257 | * updates should either be sets, clears, or set_pte_atomic for P->P | |
258 | * transitions, which means this hook should only be called for user PTEs. | |
259 | * This hook implies a P->P protection or access change has taken place, which | |
260 | * requires a subsequent TLB flush. The notification can optionally be delayed | |
261 | * until the TLB flush event by using the pte_update_defer form of the | |
262 | * interface, but care must be taken to assure that the flush happens while | |
263 | * still holding the same page table lock so that the shadow and primary pages | |
264 | * do not become out of sync on SMP. | |
265 | */ | |
266 | #define pte_update(mm, addr, ptep) do { } while (0) | |
267 | #define pte_update_defer(mm, addr, ptep) do { } while (0) | |
da181a8b | 268 | #endif |
789e6ac0 | 269 | |
9e5e3162 ZA |
270 | /* local pte updates need not use xchg for locking */ |
271 | static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) | |
272 | { | |
273 | pte_t res = *ptep; | |
274 | ||
275 | /* Pure native function needs no input for mm, addr */ | |
276 | native_pte_clear(NULL, 0, ptep); | |
277 | return res; | |
278 | } | |
279 | ||
2965a0e6 RR |
280 | /* |
281 | * We only update the dirty/accessed state if we set | |
282 | * the dirty bit by hand in the kernel, since the hardware | |
283 | * will do the accessed bit for us, and we don't want to | |
284 | * race with other CPU's that might be updating the dirty | |
285 | * bit at the same time. | |
286 | */ | |
287 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
288 | #define ptep_set_access_flags(vma, address, ptep, entry, dirty) \ | |
289 | do { \ | |
290 | if (dirty) { \ | |
291 | (ptep)->pte_low = (entry).pte_low; \ | |
dfbea0ad | 292 | pte_update_defer((vma)->vm_mm, (address), (ptep)); \ |
2965a0e6 RR |
293 | flush_tlb_page(vma, address); \ |
294 | } \ | |
295 | } while (0) | |
296 | ||
6049742d | 297 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY |
0013572b ZA |
298 | #define ptep_test_and_clear_dirty(vma, addr, ptep) ({ \ |
299 | int ret = 0; \ | |
300 | if (pte_dirty(*ptep)) \ | |
301 | ret = test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); \ | |
302 | if (ret) \ | |
303 | pte_update_defer(vma->vm_mm, addr, ptep); \ | |
304 | ret; \ | |
305 | }) | |
10a8d6ae | 306 | |
6049742d | 307 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
0013572b ZA |
308 | #define ptep_test_and_clear_young(vma, addr, ptep) ({ \ |
309 | int ret = 0; \ | |
310 | if (pte_young(*ptep)) \ | |
311 | ret = test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); \ | |
312 | if (ret) \ | |
313 | pte_update_defer(vma->vm_mm, addr, ptep); \ | |
314 | ret; \ | |
315 | }) | |
25e4df5b | 316 | |
d6d861e3 ZA |
317 | /* |
318 | * Rules for using ptep_establish: the pte MUST be a user pte, and | |
319 | * must be a present->present transition. | |
320 | */ | |
321 | #define __HAVE_ARCH_PTEP_ESTABLISH | |
322 | #define ptep_establish(vma, address, ptep, pteval) \ | |
323 | do { \ | |
324 | set_pte_present((vma)->vm_mm, address, ptep, pteval); \ | |
325 | flush_tlb_page(vma, address); \ | |
326 | } while (0) | |
327 | ||
25e4df5b ZA |
328 | #define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH |
329 | #define ptep_clear_flush_dirty(vma, address, ptep) \ | |
330 | ({ \ | |
331 | int __dirty; \ | |
10a8d6ae | 332 | __dirty = ptep_test_and_clear_dirty((vma), (address), (ptep)); \ |
0013572b | 333 | if (__dirty) \ |
25e4df5b | 334 | flush_tlb_page(vma, address); \ |
25e4df5b ZA |
335 | __dirty; \ |
336 | }) | |
337 | ||
338 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
339 | #define ptep_clear_flush_young(vma, address, ptep) \ | |
340 | ({ \ | |
341 | int __young; \ | |
10a8d6ae | 342 | __young = ptep_test_and_clear_young((vma), (address), (ptep)); \ |
0013572b | 343 | if (__young) \ |
25e4df5b | 344 | flush_tlb_page(vma, address); \ |
25e4df5b ZA |
345 | __young; \ |
346 | }) | |
1da177e4 | 347 | |
8ecb8950 ZA |
348 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
349 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | |
350 | { | |
4cdd9c89 | 351 | pte_t pte = native_ptep_get_and_clear(ptep); |
8ecb8950 ZA |
352 | pte_update(mm, addr, ptep); |
353 | return pte; | |
354 | } | |
355 | ||
6049742d | 356 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
a600388d ZA |
357 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full) |
358 | { | |
359 | pte_t pte; | |
360 | if (full) { | |
9e5e3162 ZA |
361 | /* |
362 | * Full address destruction in progress; paravirt does not | |
363 | * care about updates and native needs no locking | |
364 | */ | |
365 | pte = native_local_ptep_get_and_clear(ptep); | |
a600388d ZA |
366 | } else { |
367 | pte = ptep_get_and_clear(mm, addr, ptep); | |
368 | } | |
369 | return pte; | |
370 | } | |
371 | ||
6049742d | 372 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
1da177e4 LT |
373 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
374 | { | |
375 | clear_bit(_PAGE_BIT_RW, &ptep->pte_low); | |
789e6ac0 | 376 | pte_update(mm, addr, ptep); |
1da177e4 LT |
377 | } |
378 | ||
d7271b14 ZA |
379 | /* |
380 | * clone_pgd_range(pgd_t *dst, pgd_t *src, int count); | |
381 | * | |
382 | * dst - pointer to pgd range anwhere on a pgd page | |
383 | * src - "" | |
384 | * count - the number of pgds to copy. | |
385 | * | |
386 | * dst and src can be on the same page, but the range must not overlap, | |
387 | * and must not cross a page boundary. | |
388 | */ | |
389 | static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count) | |
390 | { | |
391 | memcpy(dst, src, count * sizeof(pgd_t)); | |
392 | } | |
393 | ||
1da177e4 LT |
394 | /* |
395 | * Macro to mark a page protection value as "uncacheable". On processors which do not support | |
396 | * it, this is a no-op. | |
397 | */ | |
398 | #define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \ | |
399 | ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot)) | |
400 | ||
401 | /* | |
402 | * Conversion functions: convert a page and protection to a page entry, | |
403 | * and a page entry and page directory to the page they refer to. | |
404 | */ | |
405 | ||
406 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
1da177e4 LT |
407 | |
408 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |
409 | { | |
410 | pte.pte_low &= _PAGE_CHG_MASK; | |
411 | pte.pte_low |= pgprot_val(newprot); | |
412 | #ifdef CONFIG_X86_PAE | |
413 | /* | |
414 | * Chop off the NX bit (if present), and add the NX portion of | |
415 | * the newprot (if present): | |
416 | */ | |
417 | pte.pte_high &= ~(1 << (_PAGE_BIT_NX - 32)); | |
418 | pte.pte_high |= (pgprot_val(newprot) >> 32) & \ | |
419 | (__supported_pte_mask >> 32); | |
420 | #endif | |
421 | return pte; | |
422 | } | |
423 | ||
1da177e4 LT |
424 | #define pmd_large(pmd) \ |
425 | ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT)) | |
426 | ||
427 | /* | |
428 | * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD] | |
429 | * | |
430 | * this macro returns the index of the entry in the pgd page which would | |
431 | * control the given virtual address | |
432 | */ | |
433 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) | |
434 | #define pgd_index_k(addr) pgd_index(addr) | |
435 | ||
436 | /* | |
437 | * pgd_offset() returns a (pgd_t *) | |
438 | * pgd_index() is used get the offset into the pgd page's array of pgd_t's; | |
439 | */ | |
440 | #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) | |
441 | ||
442 | /* | |
443 | * a shortcut which implies the use of the kernel's pgd, instead | |
444 | * of a process's | |
445 | */ | |
446 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
447 | ||
448 | /* | |
449 | * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD] | |
450 | * | |
451 | * this macro returns the index of the entry in the pmd page which would | |
452 | * control the given virtual address | |
453 | */ | |
454 | #define pmd_index(address) \ | |
455 | (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
456 | ||
457 | /* | |
458 | * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE] | |
459 | * | |
460 | * this macro returns the index of the entry in the pte page which would | |
461 | * control the given virtual address | |
462 | */ | |
463 | #define pte_index(address) \ | |
464 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
465 | #define pte_offset_kernel(dir, address) \ | |
46a82b2d | 466 | ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address)) |
1da177e4 | 467 | |
ca140fda PBG |
468 | #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) |
469 | ||
46a82b2d | 470 | #define pmd_page_vaddr(pmd) \ |
ca140fda PBG |
471 | ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) |
472 | ||
1da177e4 LT |
473 | /* |
474 | * Helper function that returns the kernel pagetable entry controlling | |
475 | * the virtual address 'address'. NULL means no pagetable entry present. | |
476 | * NOTE: the return type is pte_t but if the pmd is PSE then we return it | |
477 | * as a pte too. | |
478 | */ | |
479 | extern pte_t *lookup_address(unsigned long address); | |
480 | ||
481 | /* | |
482 | * Make a given kernel text page executable/non-executable. | |
483 | * Returns the previous executability setting of that page (which | |
484 | * is used to restore the previous state). Used by the SMP bootup code. | |
485 | * NOTE: this is an __init function for security reasons. | |
486 | */ | |
487 | #ifdef CONFIG_X86_PAE | |
488 | extern int set_kernel_exec(unsigned long vaddr, int enable); | |
489 | #else | |
490 | static inline int set_kernel_exec(unsigned long vaddr, int enable) { return 0;} | |
491 | #endif | |
492 | ||
1da177e4 | 493 | #if defined(CONFIG_HIGHPTE) |
a27fe809 | 494 | #define pte_offset_map(dir, address) \ |
ce6234b5 | 495 | ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE0) + pte_index(address)) |
a27fe809 | 496 | #define pte_offset_map_nested(dir, address) \ |
ce6234b5 | 497 | ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE1) + pte_index(address)) |
1da177e4 LT |
498 | #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) |
499 | #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) | |
500 | #else | |
501 | #define pte_offset_map(dir, address) \ | |
502 | ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address)) | |
503 | #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) | |
504 | #define pte_unmap(pte) do { } while (0) | |
505 | #define pte_unmap_nested(pte) do { } while (0) | |
506 | #endif | |
507 | ||
23002d88 ZA |
508 | /* Clear a kernel PTE and flush it from the TLB */ |
509 | #define kpte_clear_flush(ptep, vaddr) \ | |
510 | do { \ | |
511 | pte_clear(&init_mm, vaddr, ptep); \ | |
512 | __flush_tlb_one(vaddr); \ | |
513 | } while (0) | |
514 | ||
1da177e4 LT |
515 | /* |
516 | * The i386 doesn't have any external MMU info: the kernel page | |
517 | * tables contain all the necessary information. | |
1da177e4 LT |
518 | */ |
519 | #define update_mmu_cache(vma,address,pte) do { } while (0) | |
b239fb25 JF |
520 | |
521 | void native_pagetable_setup_start(pgd_t *base); | |
522 | void native_pagetable_setup_done(pgd_t *base); | |
523 | ||
524 | #ifndef CONFIG_PARAVIRT | |
525 | static inline void paravirt_pagetable_setup_start(pgd_t *base) | |
526 | { | |
527 | native_pagetable_setup_start(base); | |
528 | } | |
529 | ||
530 | static inline void paravirt_pagetable_setup_done(pgd_t *base) | |
531 | { | |
532 | native_pagetable_setup_done(base); | |
533 | } | |
534 | #endif /* !CONFIG_PARAVIRT */ | |
535 | ||
1da177e4 LT |
536 | #endif /* !__ASSEMBLY__ */ |
537 | ||
05b79bdc | 538 | #ifdef CONFIG_FLATMEM |
1da177e4 | 539 | #define kern_addr_valid(addr) (1) |
05b79bdc | 540 | #endif /* CONFIG_FLATMEM */ |
1da177e4 | 541 | |
1da177e4 LT |
542 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ |
543 | remap_pfn_range(vma, vaddr, pfn, size, prot) | |
544 | ||
545 | #define MK_IOSPACE_PFN(space, pfn) (pfn) | |
546 | #define GET_IOSPACE(pfn) 0 | |
547 | #define GET_PFN(pfn) (pfn) | |
548 | ||
1da177e4 LT |
549 | #include <asm-generic/pgtable.h> |
550 | ||
551 | #endif /* _I386_PGTABLE_H */ |