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[mirror_ubuntu-artful-kernel.git] / include / asm-i386 / processor.h
CommitLineData
1da177e4
LT		 1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
1da177e4
LT		 20#include <linux/threads.h>
21#include <asm/percpu.h>
1e9f28fa 22#include <linux/cpumask.h>
d7cd5611 23#include <linux/init.h>
1da177e4
LT		 24
25/* flag for disabling the tsc */
26extern int tsc_disable;
27
28struct desc_struct {
29 unsigned long a,b;
30};
31
32#define desc_empty(desc) \
12aaa085 33 (!((desc)->a | (desc)->b))
1da177e4
LT		 34
35#define desc_equal(desc1, desc2) \
36 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37/*
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
40 */
41#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
42
43/*
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
47 */
48
49struct cpuinfo_x86 {
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
52 __u8 x86_model;
53 __u8 x86_mask;
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
56 char hard_math;
57 char rfu;
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
63 call */
64 int x86_cache_alignment; /* In bytes */
3f98bc49
AK		 65 char fdiv_bug;
66 char f00f_bug;
67 char coma_bug;
68 char pad0;
69 int x86_power;
1da177e4 70 unsigned long loops_per_jiffy;
1e9f28fa
SS		 71#ifdef CONFIG_SMP
72 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
73#endif
94605eff 74 unsigned char x86_max_cores; /* cpuid returned max cores value */
94605eff 75 unsigned char apicid;
770d132f 76 unsigned short x86_clflush_size;
4b89aff9
RS		 77#ifdef CONFIG_SMP
78 unsigned char booted_cores; /* number of cores as seen by OS */
79 __u8 phys_proc_id; /* Physical processor id. */
80 __u8 cpu_core_id; /* Core id */
81#endif
1da177e4
LT		 82} __attribute__((__aligned__(SMP_CACHE_BYTES)));
83
84#define X86_VENDOR_INTEL 0
85#define X86_VENDOR_CYRIX 1
86#define X86_VENDOR_AMD 2
87#define X86_VENDOR_UMC 3
88#define X86_VENDOR_NEXGEN 4
89#define X86_VENDOR_CENTAUR 5
90#define X86_VENDOR_RISE 6
91#define X86_VENDOR_TRANSMETA 7
92#define X86_VENDOR_NSC 8
93#define X86_VENDOR_NUM 9
94#define X86_VENDOR_UNKNOWN 0xff
95
96/*
97 * capabilities of CPUs
98 */
99
100extern struct cpuinfo_x86 boot_cpu_data;
101extern struct cpuinfo_x86 new_cpu_data;
102extern struct tss_struct doublefault_tss;
103DECLARE_PER_CPU(struct tss_struct, init_tss);
104
105#ifdef CONFIG_SMP
106extern struct cpuinfo_x86 cpu_data[];
107#define current_cpu_data cpu_data[smp_processor_id()]
108#else
109#define cpu_data (&boot_cpu_data)
110#define current_cpu_data boot_cpu_data
111#endif
112
1e9f28fa 113extern int cpu_llc_id[NR_CPUS];
1da177e4
LT		 114extern char ignore_fpu_irq;
115
d7cd5611
RR		 116void __init cpu_detect(struct cpuinfo_x86 *c);
117
1da177e4
LT		 118extern void identify_cpu(struct cpuinfo_x86 *);
119extern void print_cpu_info(struct cpuinfo_x86 *);
120extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
240cd6a8 121extern unsigned short num_cache_leaves;
1da177e4
LT		 122
123#ifdef CONFIG_X86_HT
124extern void detect_ht(struct cpuinfo_x86 *c);
125#else
126static inline void detect_ht(struct cpuinfo_x86 *c) {}
127#endif
128
129/*
130 * EFLAGS bits
131 */
132#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
133#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
134#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
135#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
136#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
137#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
138#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
139#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
140#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
141#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
142#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
143#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
144#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
145#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
146#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
147#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
148#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
149
d3561b7f
RR		 150static inline fastcall void native_cpuid(unsigned int *eax, unsigned int *ebx,
151 unsigned int *ecx, unsigned int *edx)
9f093394
RR		 152{
153 /* ecx is often an input as well as an output. */
154 __asm__("cpuid"
155 : "=a" (*eax),
156 "=b" (*ebx),
157 "=c" (*ecx),
158 "=d" (*edx)
159 : "0" (*eax), "2" (*ecx));
160}
161
4bb0d3ec 162#define load_cr3(pgdir) write_cr3(__pa(pgdir))
1da177e4
LT		 163
164/*
165 * Intel CPU features in CR4
166 */
167#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
168#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
169#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
170#define X86_CR4_DE 0x0008 /* enable debugging extensions */
171#define X86_CR4_PSE 0x0010 /* enable page size extensions */
172#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
173#define X86_CR4_MCE 0x0040 /* Machine check enable */
174#define X86_CR4_PGE 0x0080 /* enable global pages */
175#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
176#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
177#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
178
179/*
180 * Save the cr4 feature set we're using (ie
181 * Pentium 4MB enable and PPro Global page
182 * enable), so that any CPU's that boot up
183 * after us can get the correct flags.
184 */
185extern unsigned long mmu_cr4_features;
186
187static inline void set_in_cr4 (unsigned long mask)
188{
4bb0d3ec 189 unsigned cr4;
1da177e4 190 mmu_cr4_features |= mask;
4bb0d3ec
ZA		 191 cr4 = read_cr4();
192 cr4 |= mask;
193 write_cr4(cr4);
1da177e4
LT		 194}
195
196static inline void clear_in_cr4 (unsigned long mask)
197{
4bb0d3ec 198 unsigned cr4;
1da177e4 199 mmu_cr4_features &= ~mask;
4bb0d3ec
ZA		 200 cr4 = read_cr4();
201 cr4 &= ~mask;
202 write_cr4(cr4);
1da177e4
LT		 203}
204
205/*
206 * NSC/Cyrix CPU configuration register indexes
207 */
208
209#define CX86_PCR0 0x20
210#define CX86_GCR 0xb8
211#define CX86_CCR0 0xc0
212#define CX86_CCR1 0xc1
213#define CX86_CCR2 0xc2
214#define CX86_CCR3 0xc3
215#define CX86_CCR4 0xe8
216#define CX86_CCR5 0xe9
217#define CX86_CCR6 0xea
218#define CX86_CCR7 0xeb
219#define CX86_PCR1 0xf0
220#define CX86_DIR0 0xfe
221#define CX86_DIR1 0xff
222#define CX86_ARR_BASE 0xc4
223#define CX86_RCR_BASE 0xdc
224
225/*
226 * NSC/Cyrix CPU indexed register access macros
227 */
228
229#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
230
231#define setCx86(reg, data) do { \
232 outb((reg), 0x22); \
233 outb((data), 0x23); \
234} while (0)
235
487472bc
AK		 236/* Stop speculative execution */
237static inline void sync_core(void)
245067d1 238{
487472bc
AK		 239 int tmp;
240 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
245067d1
ZA		 241}
242
1da177e4
LT		 243static inline void __monitor(const void *eax, unsigned long ecx,
244 unsigned long edx)
245{
246 /* "monitor %eax,%ecx,%edx;" */
247 asm volatile(
248 ".byte 0x0f,0x01,0xc8;"
249 : :"a" (eax), "c" (ecx), "d"(edx));
250}
251
252static inline void __mwait(unsigned long eax, unsigned long ecx)
253{
254 /* "mwait %eax,%ecx;" */
255 asm volatile(
256 ".byte 0x0f,0x01,0xc9;"
257 : :"a" (eax), "c" (ecx));
258}
259
2ff2d3d7
SE		 260static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
261{
262 /* "mwait %eax,%ecx;" */
263 asm volatile(
264 "sti; .byte 0x0f,0x01,0xc9;"
265 : :"a" (eax), "c" (ecx));
266}
267
991528d7
VP		 268extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
269
1da177e4
LT		 270/* from system description table in BIOS. Mostly for MCA use, but
271others may find it useful. */
272extern unsigned int machine_id;
273extern unsigned int machine_submodel_id;
274extern unsigned int BIOS_revision;
275extern unsigned int mca_pentium_flag;
276
277/* Boot loader type from the setup header */
278extern int bootloader_type;
279
280/*
281 * User space process size: 3GB (default).
282 */
283#define TASK_SIZE (PAGE_OFFSET)
284
285/* This decides where the kernel will search for a free chunk of vm
286 * space during mmap's.
287 */
288#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
289
290#define HAVE_ARCH_PICK_MMAP_LAYOUT
291
292/*
293 * Size of io_bitmap.
294 */
295#define IO_BITMAP_BITS 65536
296#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
297#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
298#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
299#define INVALID_IO_BITMAP_OFFSET 0x8000
300#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
301
302struct i387_fsave_struct {
303 long cwd;
304 long swd;
305 long twd;
306 long fip;
307 long fcs;
308 long foo;
309 long fos;
310 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
311 long status; /* software status information */
312};
313
314struct i387_fxsave_struct {
315 unsigned short cwd;
316 unsigned short swd;
317 unsigned short twd;
318 unsigned short fop;
319 long fip;
320 long fcs;
321 long foo;
322 long fos;
323 long mxcsr;
324 long mxcsr_mask;
325 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
326 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
327 long padding[56];
328} __attribute__ ((aligned (16)));
329
330struct i387_soft_struct {
331 long cwd;
332 long swd;
333 long twd;
334 long fip;
335 long fcs;
336 long foo;
337 long fos;
338 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
339 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
340 struct info *info;
341 unsigned long entry_eip;
342};
343
344union i387_union {
345 struct i387_fsave_struct fsave;
346 struct i387_fxsave_struct fxsave;
347 struct i387_soft_struct soft;
348};
349
350typedef struct {
351 unsigned long seg;
352} mm_segment_t;
353
354struct thread_struct;
355
356struct tss_struct {
357 unsigned short back_link,__blh;
358 unsigned long esp0;
359 unsigned short ss0,__ss0h;
360 unsigned long esp1;
361 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
362 unsigned long esp2;
363 unsigned short ss2,__ss2h;
364 unsigned long __cr3;
365 unsigned long eip;
366 unsigned long eflags;
367 unsigned long eax,ecx,edx,ebx;
368 unsigned long esp;
369 unsigned long ebp;
370 unsigned long esi;
371 unsigned long edi;
372 unsigned short es, __esh;
373 unsigned short cs, __csh;
374 unsigned short ss, __ssh;
375 unsigned short ds, __dsh;
376 unsigned short fs, __fsh;
377 unsigned short gs, __gsh;
378 unsigned short ldt, __ldth;
379 unsigned short trace, io_bitmap_base;
380 /*
381 * The extra 1 is there because the CPU will access an
382 * additional byte beyond the end of the IO permission
383 * bitmap. The extra byte must be all 1 bits, and must
384 * be within the limit.
385 */
386 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
387 /*
388 * Cache the current maximum and the last task that used the bitmap:
389 */
390 unsigned long io_bitmap_max;
391 struct thread_struct *io_bitmap_owner;
392 /*
393 * pads the TSS to be cacheline-aligned (size is 0x100)
394 */
395 unsigned long __cacheline_filler[35];
396 /*
397 * .. and then another 0x100 bytes for emergency kernel stack
398 */
399 unsigned long stack[64];
400} __attribute__((packed));
401
402#define ARCH_MIN_TASKALIGN 16
403
404struct thread_struct {
405/* cached TLS descriptors. */
406 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
407 unsigned long esp0;
408 unsigned long sysenter_cs;
409 unsigned long eip;
410 unsigned long esp;
411 unsigned long fs;
412 unsigned long gs;
413/* Hardware debugging registers */
414 unsigned long debugreg[8]; /* %%db0-7 debug registers */
415/* fault info */
416 unsigned long cr2, trap_no, error_code;
417/* floating point info */
418 union i387_union i387;
419/* virtual 86 mode info */
420 struct vm86_struct __user * vm86_info;
421 unsigned long screen_bitmap;
422 unsigned long v86flags, v86mask, saved_esp0;
423 unsigned int saved_fs, saved_gs;
424/* IO permissions */
425 unsigned long *io_bitmap_ptr;
a5201129 426 unsigned long iopl;
1da177e4
LT		 427/* max allowed port in the bitmap, in bytes: */
428 unsigned long io_bitmap_max;
429};
430
431#define INIT_THREAD { \
432 .vm86_info = NULL, \
433 .sysenter_cs = __KERNEL_CS, \
434 .io_bitmap_ptr = NULL, \
464d1a78 435 .fs = __KERNEL_PDA, \
1da177e4
LT		 436}
437
438/*
439 * Note that the .io_bitmap member must be extra-big. This is because
440 * the CPU will access an additional byte beyond the end of the IO
441 * permission bitmap. The extra byte must be all 1 bits, and must
442 * be within the limit.
443 */
444#define INIT_TSS { \
445 .esp0 = sizeof(init_stack) + (long)&init_stack, \
446 .ss0 = __KERNEL_DS, \
447 .ss1 = __KERNEL_CS, \
1da177e4
LT		 448 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
449 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
450}
451
1da177e4 452#define start_thread(regs, new_eip, new_esp) do { \
464d1a78
JF		 453 __asm__("movl %0,%%gs": :"r" (0)); \
454 regs->xfs = 0; \
1da177e4
LT		 455 set_fs(USER_DS); \
456 regs->xds = __USER_DS; \
457 regs->xes = __USER_DS; \
458 regs->xss = __USER_DS; \
459 regs->xcs = __USER_CS; \
460 regs->eip = new_eip; \
461 regs->esp = new_esp; \
462} while (0)
463
464/* Forward declaration, a strange C thing */
465struct task_struct;
466struct mm_struct;
467
468/* Free all resources held by a thread. */
469extern void release_thread(struct task_struct *);
470
471/* Prepare to copy thread state - unlazy all lazy status */
472extern void prepare_to_copy(struct task_struct *tsk);
473
474/*
475 * create a kernel thread without removing it from tasklists
476 */
477extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
478
479extern unsigned long thread_saved_pc(struct task_struct *tsk);
176a2718 480void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
1da177e4
LT		 481
482unsigned long get_wchan(struct task_struct *p);
483
484#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
485#define KSTK_TOP(info) \
486({ \
487 unsigned long *__ptr = (unsigned long *)(info); \
488 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
489})
490
07b047fc 491/*
492 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
493 * This is necessary to guarantee that the entire "struct pt_regs"
494 * is accessable even if the CPU haven't stored the SS/ESP registers
495 * on the stack (interrupt gate does not save these registers
496 * when switching to the same priv ring).
497 * Therefore beware: accessing the xss/esp fields of the
498 * "struct pt_regs" is possible, but they may contain the
499 * completely wrong values.
500 */
1da177e4
LT		 501#define task_pt_regs(task) \
502({ \
503 struct pt_regs *__regs__; \
65e0fdff 504 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
1da177e4
LT		 505 __regs__ - 1; \
506})
507
508#define KSTK_EIP(task) (task_pt_regs(task)->eip)
509#define KSTK_ESP(task) (task_pt_regs(task)->esp)
510
511
512struct microcode_header {
513 unsigned int hdrver;
514 unsigned int rev;
515 unsigned int date;
516 unsigned int sig;
517 unsigned int cksum;
518 unsigned int ldrver;
519 unsigned int pf;
520 unsigned int datasize;
521 unsigned int totalsize;
522 unsigned int reserved[3];
523};
524
525struct microcode {
526 struct microcode_header hdr;
527 unsigned int bits[0];
528};
529
530typedef struct microcode microcode_t;
531typedef struct microcode_header microcode_header_t;
532
533/* microcode format is extended from prescott processors */
534struct extended_signature {
535 unsigned int sig;
536 unsigned int pf;
537 unsigned int cksum;
538};
539
540struct extended_sigtable {
541 unsigned int count;
542 unsigned int cksum;
543 unsigned int reserved[3];
544 struct extended_signature sigs[0];
545};
1da177e4
LT		 546
547/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
548static inline void rep_nop(void)
549{
550 __asm__ __volatile__("rep;nop": : :"memory");
551}
552
553#define cpu_relax() rep_nop()
554
139ec7c4
RR		 555#ifdef CONFIG_PARAVIRT
556#include <asm/paravirt.h>
557#else
558#define paravirt_enabled() 0
559#define __cpuid native_cpuid
560
561static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
562{
563 tss->esp0 = thread->esp0;
564 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
565 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
566 tss->ss1 = thread->sysenter_cs;
567 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
568 }
569}
570
571/*
572 * These special macros can be used to get or set a debugging register
573 */
574#define get_debugreg(var, register) \
575 __asm__("movl %%db" #register ", %0" \
576 :"=r" (var))
577#define set_debugreg(value, register) \
578 __asm__("movl %0,%%db" #register \
579 : /* no output */ \
580 :"r" (value))
581
582#define set_iopl_mask native_set_iopl_mask
583#endif /* CONFIG_PARAVIRT */
584
585/*
586 * Set IOPL bits in EFLAGS from given mask
587 */
588static fastcall inline void native_set_iopl_mask(unsigned mask)
589{
590 unsigned int reg;
591 __asm__ __volatile__ ("pushfl;"
592 "popl %0;"
593 "andl %1, %0;"
594 "orl %2, %0;"
595 "pushl %0;"
596 "popfl"
597 : "=&r" (reg)
598 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
599}
600
601/*
602 * Generic CPUID function
603 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
604 * resulting in stale register contents being returned.
605 */
606static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
607{
608 *eax = op;
609 *ecx = 0;
610 __cpuid(eax, ebx, ecx, edx);
611}
612
613/* Some CPUID calls want 'count' to be placed in ecx */
614static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
615 int *edx)
616{
617 *eax = op;
618 *ecx = count;
619 __cpuid(eax, ebx, ecx, edx);
620}
621
622/*
623 * CPUID functions returning a single datum
624 */
625static inline unsigned int cpuid_eax(unsigned int op)
626{
627 unsigned int eax, ebx, ecx, edx;
628
629 cpuid(op, &eax, &ebx, &ecx, &edx);
630 return eax;
631}
632static inline unsigned int cpuid_ebx(unsigned int op)
633{
634 unsigned int eax, ebx, ecx, edx;
635
636 cpuid(op, &eax, &ebx, &ecx, &edx);
637 return ebx;
638}
639static inline unsigned int cpuid_ecx(unsigned int op)
640{
641 unsigned int eax, ebx, ecx, edx;
642
643 cpuid(op, &eax, &ebx, &ecx, &edx);
644 return ecx;
645}
646static inline unsigned int cpuid_edx(unsigned int op)
647{
648 unsigned int eax, ebx, ecx, edx;
649
650 cpuid(op, &eax, &ebx, &ecx, &edx);
651 return edx;
652}
653
1da177e4
LT		 654/* generic versions from gas */
655#define GENERIC_NOP1 ".byte 0x90\n"
656#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
657#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
658#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
659#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
660#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
661#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
662#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
663
664/* Opteron nops */
665#define K8_NOP1 GENERIC_NOP1
666#define K8_NOP2 ".byte 0x66,0x90\n"
667#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
668#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
669#define K8_NOP5 K8_NOP3 K8_NOP2
670#define K8_NOP6 K8_NOP3 K8_NOP3
671#define K8_NOP7 K8_NOP4 K8_NOP3
672#define K8_NOP8 K8_NOP4 K8_NOP4
673
674/* K7 nops */
675/* uses eax dependencies (arbitary choice) */
676#define K7_NOP1 GENERIC_NOP1
677#define K7_NOP2 ".byte 0x8b,0xc0\n"
678#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
679#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
680#define K7_NOP5 K7_NOP4 ASM_NOP1
681#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
682#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
683#define K7_NOP8 K7_NOP7 ASM_NOP1
684
685#ifdef CONFIG_MK8
686#define ASM_NOP1 K8_NOP1
687#define ASM_NOP2 K8_NOP2
688#define ASM_NOP3 K8_NOP3
689#define ASM_NOP4 K8_NOP4
690#define ASM_NOP5 K8_NOP5
691#define ASM_NOP6 K8_NOP6
692#define ASM_NOP7 K8_NOP7
693#define ASM_NOP8 K8_NOP8
694#elif defined(CONFIG_MK7)
695#define ASM_NOP1 K7_NOP1
696#define ASM_NOP2 K7_NOP2
697#define ASM_NOP3 K7_NOP3
698#define ASM_NOP4 K7_NOP4
699#define ASM_NOP5 K7_NOP5
700#define ASM_NOP6 K7_NOP6
701#define ASM_NOP7 K7_NOP7
702#define ASM_NOP8 K7_NOP8
703#else
704#define ASM_NOP1 GENERIC_NOP1
705#define ASM_NOP2 GENERIC_NOP2
706#define ASM_NOP3 GENERIC_NOP3
707#define ASM_NOP4 GENERIC_NOP4
708#define ASM_NOP5 GENERIC_NOP5
709#define ASM_NOP6 GENERIC_NOP6
710#define ASM_NOP7 GENERIC_NOP7
711#define ASM_NOP8 GENERIC_NOP8
712#endif
713
714#define ASM_NOP_MAX 8
715
716/* Prefetch instructions for Pentium III and AMD Athlon */
717/* It's not worth to care about 3dnow! prefetches for the K6
718 because they are microcoded there and very slow.
719 However we don't do prefetches for pre XP Athlons currently
720 That should be fixed. */
721#define ARCH_HAS_PREFETCH
e2afe674 722static inline void prefetch(const void *x)
1da177e4
LT		 723{
724 alternative_input(ASM_NOP4,
725 "prefetchnta (%1)",
726 X86_FEATURE_XMM,
727 "r" (x));
728}
729
730#define ARCH_HAS_PREFETCH
731#define ARCH_HAS_PREFETCHW
732#define ARCH_HAS_SPINLOCK_PREFETCH
733
734/* 3dnow! prefetch to get an exclusive cache line. Useful for
735 spinlocks to avoid one state transition in the cache coherency protocol. */
e2afe674 736static inline void prefetchw(const void *x)
1da177e4
LT		 737{
738 alternative_input(ASM_NOP4,
739 "prefetchw (%1)",
740 X86_FEATURE_3DNOW,
741 "r" (x));
742}
743#define spin_lock_prefetch(x) prefetchw(x)
744
745extern void select_idle_routine(const struct cpuinfo_x86 *c);
746
747#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
748
749extern unsigned long boot_option_idle_override;
6fe940d6
LS		 750extern void enable_sep_cpu(void);
751extern int sysenter_setup(void);
1da177e4 752
62111195 753extern int init_gdt(int cpu, struct task_struct *idle);
9ee79a3d 754extern void cpu_set_gdt(int);
62111195
JF		 755extern void secondary_cpu_init(void);
756
1da177e4 757#endif /* __ASM_I386_PROCESSOR_H */
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