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1 | #ifndef _ASM_IA64_HW_IRQ_H |
2 | #define _ASM_IA64_HW_IRQ_H | |
3 | ||
4 | /* | |
5 | * Copyright (C) 2001-2003 Hewlett-Packard Co | |
6 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
7 | */ | |
8 | ||
9 | #include <linux/interrupt.h> | |
10 | #include <linux/sched.h> | |
11 | #include <linux/types.h> | |
12 | #include <linux/profile.h> | |
13 | ||
14 | #include <asm/machvec.h> | |
15 | #include <asm/ptrace.h> | |
16 | #include <asm/smp.h> | |
17 | ||
18 | typedef u8 ia64_vector; | |
19 | ||
20 | /* | |
21 | * 0 special | |
22 | * | |
23 | * 1,3-14 are reserved from firmware | |
24 | * | |
25 | * 16-255 (vectored external interrupts) are available | |
26 | * | |
27 | * 15 spurious interrupt (see IVR) | |
28 | * | |
29 | * 16 lowest priority, 255 highest priority | |
30 | * | |
31 | * 15 classes of 16 interrupts each. | |
32 | */ | |
33 | #define IA64_MIN_VECTORED_IRQ 16 | |
34 | #define IA64_MAX_VECTORED_IRQ 255 | |
35 | #define IA64_NUM_VECTORS 256 | |
36 | ||
37 | #define AUTO_ASSIGN -1 | |
38 | ||
39 | #define IA64_SPURIOUS_INT_VECTOR 0x0f | |
40 | ||
41 | /* | |
42 | * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI. | |
43 | */ | |
44 | #define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */ | |
45 | #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */ | |
46 | #define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */ | |
47 | #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ | |
48 | /* | |
49 | * Vectors 0x20-0x2f are reserved for legacy ISA IRQs. | |
10083072 MM |
50 | * Use vectors 0x30-0xe7 as the default device vector range for ia64. |
51 | * Platforms may choose to reduce this range in platform_irq_setup, but the | |
52 | * platform range must fall within | |
53 | * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR] | |
1da177e4 | 54 | */ |
10083072 MM |
55 | extern int ia64_first_device_vector; |
56 | extern int ia64_last_device_vector; | |
57 | ||
58 | #define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 | |
59 | #define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 | |
60 | #define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector | |
61 | #define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector | |
62 | #define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1) | |
1da177e4 LT |
63 | #define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) |
64 | ||
65 | #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ | |
66 | #define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */ | |
67 | #define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ | |
68 | #define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ | |
3be44b9c | 69 | #define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */ |
1da177e4 LT |
70 | #define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */ |
71 | #define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */ | |
72 | ||
73 | /* Used for encoding redirected irqs */ | |
74 | ||
75 | #define IA64_IRQ_REDIRECTED (1 << 31) | |
76 | ||
77 | /* IA64 inter-cpu interrupt related definitions */ | |
78 | ||
79 | #define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000 | |
80 | ||
81 | /* Delivery modes for inter-cpu interrupts */ | |
82 | enum { | |
83 | IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */ | |
84 | IA64_IPI_DM_PMI = 0x2, /* pend a PMI */ | |
85 | IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */ | |
86 | IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */ | |
87 | IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */ | |
88 | }; | |
89 | ||
90 | extern __u8 isa_irq_to_vector_map[16]; | |
91 | #define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] | |
92 | ||
e1b30a39 YI |
93 | struct irq_cfg { |
94 | ia64_vector vector; | |
4994be1b | 95 | cpumask_t domain; |
e1b30a39 YI |
96 | }; |
97 | extern spinlock_t vector_lock; | |
98 | extern struct irq_cfg irq_cfg[NR_IRQS]; | |
4994be1b | 99 | #define irq_to_domain(x) irq_cfg[(x)].domain |
e1b30a39 YI |
100 | DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); |
101 | ||
1da177e4 LT |
102 | extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ |
103 | ||
4994be1b | 104 | extern int bind_irq_vector(int irq, int vector, cpumask_t domain); |
1da177e4 LT |
105 | extern int assign_irq_vector (int irq); /* allocate a free vector */ |
106 | extern void free_irq_vector (int vector); | |
10083072 | 107 | extern int reserve_irq_vector (int vector); |
e1b30a39 | 108 | extern void __setup_vector_irq(int cpu); |
cd378f18 | 109 | extern int reassign_irq_vector(int irq, int cpu); |
1da177e4 LT |
110 | extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); |
111 | extern void register_percpu_irq (ia64_vector vec, struct irqaction *action); | |
e1b30a39 YI |
112 | extern int check_irq_used (int irq); |
113 | extern void destroy_and_reserve_irq (unsigned int irq); | |
1da177e4 | 114 | |
c0ad90a3 | 115 | static inline void ia64_resend_irq(unsigned int vector) |
1da177e4 LT |
116 | { |
117 | platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Default implementations for the irq-descriptor API: | |
122 | */ | |
123 | ||
124 | extern irq_desc_t irq_desc[NR_IRQS]; | |
125 | ||
126 | #ifndef CONFIG_IA64_GENERIC | |
127 | static inline unsigned int | |
128 | __ia64_local_vector_to_irq (ia64_vector vec) | |
129 | { | |
e1b30a39 | 130 | return __get_cpu_var(vector_irq)[vec]; |
1da177e4 LT |
131 | } |
132 | #endif | |
133 | ||
134 | /* | |
135 | * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt | |
136 | * vectors. On smaller systems, there is a one-to-one correspondence between interrupt | |
137 | * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt | |
138 | * domains meaning that the translation from vector number to irq number depends on the | |
139 | * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent | |
140 | * differences and provides a uniform means to translate between vector and irq numbers | |
141 | * and to obtain the irq descriptor for a given irq number. | |
142 | */ | |
143 | ||
1da177e4 LT |
144 | /* Extract the IA-64 vector that corresponds to IRQ. */ |
145 | static inline ia64_vector | |
146 | irq_to_vector (int irq) | |
147 | { | |
e1b30a39 | 148 | return irq_cfg[irq].vector; |
1da177e4 LT |
149 | } |
150 | ||
151 | /* | |
152 | * Convert the local IA-64 vector to the corresponding irq number. This translation is | |
153 | * done in the context of the interrupt domain that the currently executing CPU belongs | |
154 | * to. | |
155 | */ | |
156 | static inline unsigned int | |
157 | local_vector_to_irq (ia64_vector vec) | |
158 | { | |
159 | return platform_local_vector_to_irq(vec); | |
160 | } | |
161 | ||
162 | #endif /* _ASM_IA64_HW_IRQ_H */ |