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1 | #ifndef _ASM_IA64_PAL_H |
2 | #define _ASM_IA64_PAL_H | |
3 | ||
4 | /* | |
5 | * Processor Abstraction Layer definitions. | |
6 | * | |
7 | * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 | |
8 | * chapter 11 IA-64 Processor Abstraction Layer | |
9 | * | |
10 | * Copyright (C) 1998-2001 Hewlett-Packard Co | |
11 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
12 | * Stephane Eranian <eranian@hpl.hp.com> | |
13 | * Copyright (C) 1999 VA Linux Systems | |
14 | * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
15 | * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> | |
16 | * | |
17 | * 99/10/01 davidm Make sure we pass zero for reserved parameters. | |
18 | * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. | |
19 | * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info | |
20 | * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added | |
21 | * 00/05/25 eranian Support for stack calls, and static physical calls | |
22 | * 00/06/18 eranian Support for stacked physical calls | |
23 | */ | |
24 | ||
25 | /* | |
26 | * Note that some of these calls use a static-register only calling | |
27 | * convention which has nothing to do with the regular calling | |
28 | * convention. | |
29 | */ | |
30 | #define PAL_CACHE_FLUSH 1 /* flush i/d cache */ | |
31 | #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */ | |
32 | #define PAL_CACHE_INIT 3 /* initialize i/d cache */ | |
33 | #define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */ | |
34 | #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */ | |
35 | #define PAL_PTCE_INFO 6 /* purge TLB info */ | |
36 | #define PAL_VM_INFO 7 /* return supported virtual memory features */ | |
37 | #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */ | |
38 | #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */ | |
39 | #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */ | |
40 | #define PAL_DEBUG_INFO 11 /* get number of debug registers */ | |
41 | #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */ | |
42 | #define PAL_FREQ_BASE 13 /* base frequency of the platform */ | |
43 | #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */ | |
44 | #define PAL_PERF_MON_INFO 15 /* return performance monitor info */ | |
45 | #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */ | |
46 | #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */ | |
47 | #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */ | |
48 | #define PAL_RSE_INFO 19 /* return rse information */ | |
49 | #define PAL_VERSION 20 /* return version of PAL code */ | |
50 | #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */ | |
51 | #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */ | |
52 | #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */ | |
53 | #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */ | |
54 | #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */ | |
55 | #define PAL_MC_RESUME 26 /* Return to interrupted process */ | |
56 | #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */ | |
57 | #define PAL_HALT 28 /* enter the low power HALT state */ | |
58 | #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/ | |
59 | #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */ | |
60 | #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */ | |
61 | #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */ | |
62 | #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */ | |
63 | #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */ | |
64 | ||
65 | #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */ | |
66 | #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */ | |
67 | #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ | |
68 | #define PAL_SHUTDOWN 40 /* enter processor shutdown state */ | |
69 | #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ | |
e927ecb0 | 70 | #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */ |
f1918005 | 71 | #define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */ |
1da177e4 LT |
72 | |
73 | #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ | |
74 | #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ | |
75 | #define PAL_TEST_PROC 258 /* perform late processor self-test */ | |
76 | #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ | |
77 | #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ | |
78 | #define PAL_VM_TR_READ 261 /* read contents of translation register */ | |
4db8699b VP |
79 | #define PAL_GET_PSTATE 262 /* get the current P-state */ |
80 | #define PAL_SET_PSTATE 263 /* set the P-state */ | |
76d08bb3 | 81 | #define PAL_BRAND_INFO 274 /* Processor branding information */ |
1da177e4 LT |
82 | |
83 | #ifndef __ASSEMBLY__ | |
84 | ||
85 | #include <linux/types.h> | |
86 | #include <asm/fpu.h> | |
87 | ||
88 | /* | |
89 | * Data types needed to pass information into PAL procedures and | |
90 | * interpret information returned by them. | |
91 | */ | |
92 | ||
93 | /* Return status from the PAL procedure */ | |
94 | typedef s64 pal_status_t; | |
95 | ||
96 | #define PAL_STATUS_SUCCESS 0 /* No error */ | |
97 | #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ | |
98 | #define PAL_STATUS_EINVAL (-2) /* Invalid argument */ | |
99 | #define PAL_STATUS_ERROR (-3) /* Error */ | |
100 | #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the | |
101 | * specified level and type of | |
102 | * cache without sideeffects | |
103 | * and "restrict" was 1 | |
104 | */ | |
105 | ||
106 | /* Processor cache level in the heirarchy */ | |
107 | typedef u64 pal_cache_level_t; | |
108 | #define PAL_CACHE_LEVEL_L0 0 /* L0 */ | |
109 | #define PAL_CACHE_LEVEL_L1 1 /* L1 */ | |
110 | #define PAL_CACHE_LEVEL_L2 2 /* L2 */ | |
111 | ||
112 | ||
113 | /* Processor cache type at a particular level in the heirarchy */ | |
114 | ||
115 | typedef u64 pal_cache_type_t; | |
116 | #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */ | |
117 | #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */ | |
118 | #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */ | |
119 | ||
120 | ||
121 | #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */ | |
122 | #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */ | |
123 | ||
124 | /* Processor cache line size in bytes */ | |
125 | typedef int pal_cache_line_size_t; | |
126 | ||
127 | /* Processor cache line state */ | |
128 | typedef u64 pal_cache_line_state_t; | |
129 | #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */ | |
130 | #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */ | |
131 | #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */ | |
132 | #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */ | |
133 | ||
134 | typedef struct pal_freq_ratio { | |
2ab9391d | 135 | u32 den, num; /* numerator & denominator */ |
1da177e4 LT |
136 | } itc_ratio, proc_ratio; |
137 | ||
138 | typedef union pal_cache_config_info_1_s { | |
139 | struct { | |
140 | u64 u : 1, /* 0 Unified cache ? */ | |
141 | at : 2, /* 2-1 Cache mem attr*/ | |
142 | reserved : 5, /* 7-3 Reserved */ | |
143 | associativity : 8, /* 16-8 Associativity*/ | |
144 | line_size : 8, /* 23-17 Line size */ | |
145 | stride : 8, /* 31-24 Stride */ | |
146 | store_latency : 8, /*39-32 Store latency*/ | |
147 | load_latency : 8, /* 47-40 Load latency*/ | |
148 | store_hints : 8, /* 55-48 Store hints*/ | |
149 | load_hints : 8; /* 63-56 Load hints */ | |
150 | } pcci1_bits; | |
151 | u64 pcci1_data; | |
152 | } pal_cache_config_info_1_t; | |
153 | ||
154 | typedef union pal_cache_config_info_2_s { | |
155 | struct { | |
2ab9391d | 156 | u32 cache_size; /*cache size in bytes*/ |
1da177e4 LT |
157 | |
158 | ||
2ab9391d | 159 | u32 alias_boundary : 8, /* 39-32 aliased addr |
1da177e4 LT |
160 | * separation for max |
161 | * performance. | |
162 | */ | |
163 | tag_ls_bit : 8, /* 47-40 LSb of addr*/ | |
164 | tag_ms_bit : 8, /* 55-48 MSb of addr*/ | |
165 | reserved : 8; /* 63-56 Reserved */ | |
166 | } pcci2_bits; | |
167 | u64 pcci2_data; | |
168 | } pal_cache_config_info_2_t; | |
169 | ||
170 | ||
171 | typedef struct pal_cache_config_info_s { | |
172 | pal_status_t pcci_status; | |
173 | pal_cache_config_info_1_t pcci_info_1; | |
174 | pal_cache_config_info_2_t pcci_info_2; | |
175 | u64 pcci_reserved; | |
176 | } pal_cache_config_info_t; | |
177 | ||
178 | #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints | |
179 | #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints | |
180 | #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency | |
181 | #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency | |
182 | #define pcci_stride pcci_info_1.pcci1_bits.stride | |
183 | #define pcci_line_size pcci_info_1.pcci1_bits.line_size | |
184 | #define pcci_assoc pcci_info_1.pcci1_bits.associativity | |
185 | #define pcci_cache_attr pcci_info_1.pcci1_bits.at | |
186 | #define pcci_unified pcci_info_1.pcci1_bits.u | |
187 | #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit | |
188 | #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit | |
189 | #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary | |
190 | #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size | |
191 | ||
192 | ||
193 | ||
194 | /* Possible values for cache attributes */ | |
195 | ||
196 | #define PAL_CACHE_ATTR_WT 0 /* Write through cache */ | |
197 | #define PAL_CACHE_ATTR_WB 1 /* Write back cache */ | |
198 | #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write | |
199 | * back depending on TLB | |
200 | * memory attributes | |
201 | */ | |
202 | ||
203 | ||
204 | /* Possible values for cache hints */ | |
205 | ||
206 | #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */ | |
207 | #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */ | |
208 | #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */ | |
209 | ||
210 | /* Processor cache protection information */ | |
211 | typedef union pal_cache_protection_element_u { | |
212 | u32 pcpi_data; | |
213 | struct { | |
214 | u32 data_bits : 8, /* # data bits covered by | |
215 | * each unit of protection | |
216 | */ | |
217 | ||
218 | tagprot_lsb : 6, /* Least -do- */ | |
219 | tagprot_msb : 6, /* Most Sig. tag address | |
220 | * bit that this | |
221 | * protection covers. | |
222 | */ | |
223 | prot_bits : 6, /* # of protection bits */ | |
224 | method : 4, /* Protection method */ | |
225 | t_d : 2; /* Indicates which part | |
226 | * of the cache this | |
227 | * protection encoding | |
228 | * applies. | |
229 | */ | |
230 | } pcp_info; | |
231 | } pal_cache_protection_element_t; | |
232 | ||
233 | #define pcpi_cache_prot_part pcp_info.t_d | |
234 | #define pcpi_prot_method pcp_info.method | |
235 | #define pcpi_prot_bits pcp_info.prot_bits | |
236 | #define pcpi_tagprot_msb pcp_info.tagprot_msb | |
237 | #define pcpi_tagprot_lsb pcp_info.tagprot_lsb | |
238 | #define pcpi_data_bits pcp_info.data_bits | |
239 | ||
240 | /* Processor cache part encodings */ | |
241 | #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */ | |
242 | #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */ | |
243 | #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is | |
244 | * more significant ) | |
245 | */ | |
246 | #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is | |
247 | * more significant ) | |
248 | */ | |
249 | #define PAL_CACHE_PROT_PART_MAX 6 | |
250 | ||
251 | ||
252 | typedef struct pal_cache_protection_info_s { | |
253 | pal_status_t pcpi_status; | |
254 | pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX]; | |
255 | } pal_cache_protection_info_t; | |
256 | ||
257 | ||
258 | /* Processor cache protection method encodings */ | |
259 | #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ | |
260 | #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */ | |
261 | #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */ | |
262 | #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */ | |
263 | ||
264 | ||
265 | /* Processor cache line identification in the heirarchy */ | |
266 | typedef union pal_cache_line_id_u { | |
267 | u64 pclid_data; | |
268 | struct { | |
269 | u64 cache_type : 8, /* 7-0 cache type */ | |
270 | level : 8, /* 15-8 level of the | |
271 | * cache in the | |
272 | * heirarchy. | |
273 | */ | |
274 | way : 8, /* 23-16 way in the set | |
275 | */ | |
276 | part : 8, /* 31-24 part of the | |
277 | * cache | |
278 | */ | |
279 | reserved : 32; /* 63-32 is reserved*/ | |
280 | } pclid_info_read; | |
281 | struct { | |
282 | u64 cache_type : 8, /* 7-0 cache type */ | |
283 | level : 8, /* 15-8 level of the | |
284 | * cache in the | |
285 | * heirarchy. | |
286 | */ | |
287 | way : 8, /* 23-16 way in the set | |
288 | */ | |
289 | part : 8, /* 31-24 part of the | |
290 | * cache | |
291 | */ | |
292 | mesi : 8, /* 39-32 cache line | |
293 | * state | |
294 | */ | |
295 | start : 8, /* 47-40 lsb of data to | |
296 | * invert | |
297 | */ | |
298 | length : 8, /* 55-48 #bits to | |
299 | * invert | |
300 | */ | |
301 | trigger : 8; /* 63-56 Trigger error | |
302 | * by doing a load | |
303 | * after the write | |
304 | */ | |
305 | ||
306 | } pclid_info_write; | |
307 | } pal_cache_line_id_u_t; | |
308 | ||
309 | #define pclid_read_part pclid_info_read.part | |
310 | #define pclid_read_way pclid_info_read.way | |
311 | #define pclid_read_level pclid_info_read.level | |
312 | #define pclid_read_cache_type pclid_info_read.cache_type | |
313 | ||
314 | #define pclid_write_trigger pclid_info_write.trigger | |
315 | #define pclid_write_length pclid_info_write.length | |
316 | #define pclid_write_start pclid_info_write.start | |
317 | #define pclid_write_mesi pclid_info_write.mesi | |
318 | #define pclid_write_part pclid_info_write.part | |
319 | #define pclid_write_way pclid_info_write.way | |
320 | #define pclid_write_level pclid_info_write.level | |
321 | #define pclid_write_cache_type pclid_info_write.cache_type | |
322 | ||
323 | /* Processor cache line part encodings */ | |
324 | #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */ | |
325 | #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ | |
326 | #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ | |
327 | #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ | |
328 | #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag | |
329 | * protection | |
330 | */ | |
331 | typedef struct pal_cache_line_info_s { | |
332 | pal_status_t pcli_status; /* Return status of the read cache line | |
333 | * info call. | |
334 | */ | |
335 | u64 pcli_data; /* 64-bit data, tag, protection bits .. */ | |
336 | u64 pcli_data_len; /* data length in bits */ | |
337 | pal_cache_line_state_t pcli_cache_line_state; /* mesi state */ | |
338 | ||
339 | } pal_cache_line_info_t; | |
340 | ||
341 | ||
342 | /* Machine Check related crap */ | |
343 | ||
344 | /* Pending event status bits */ | |
345 | typedef u64 pal_mc_pending_events_t; | |
346 | ||
347 | #define PAL_MC_PENDING_MCA (1 << 0) | |
348 | #define PAL_MC_PENDING_INIT (1 << 1) | |
349 | ||
350 | /* Error information type */ | |
351 | typedef u64 pal_mc_info_index_t; | |
352 | ||
353 | #define PAL_MC_INFO_PROCESSOR 0 /* Processor */ | |
354 | #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */ | |
355 | #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */ | |
356 | #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */ | |
357 | #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ | |
358 | #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ | |
359 | #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ | |
360 | #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation | |
361 | * dependent | |
362 | */ | |
363 | ||
364 | ||
365 | typedef struct pal_process_state_info_s { | |
366 | u64 reserved1 : 2, | |
367 | rz : 1, /* PAL_CHECK processor | |
368 | * rendezvous | |
369 | * successful. | |
370 | */ | |
371 | ||
372 | ra : 1, /* PAL_CHECK attempted | |
373 | * a rendezvous. | |
374 | */ | |
375 | me : 1, /* Distinct multiple | |
376 | * errors occurred | |
377 | */ | |
378 | ||
379 | mn : 1, /* Min. state save | |
380 | * area has been | |
381 | * registered with PAL | |
382 | */ | |
383 | ||
384 | sy : 1, /* Storage integrity | |
385 | * synched | |
386 | */ | |
387 | ||
388 | ||
389 | co : 1, /* Continuable */ | |
390 | ci : 1, /* MC isolated */ | |
391 | us : 1, /* Uncontained storage | |
392 | * damage. | |
393 | */ | |
394 | ||
395 | ||
396 | hd : 1, /* Non-essential hw | |
397 | * lost (no loss of | |
398 | * functionality) | |
399 | * causing the | |
400 | * processor to run in | |
401 | * degraded mode. | |
402 | */ | |
403 | ||
404 | tl : 1, /* 1 => MC occurred | |
405 | * after an instr was | |
406 | * executed but before | |
407 | * the trap that | |
408 | * resulted from instr | |
409 | * execution was | |
410 | * generated. | |
411 | * (Trap Lost ) | |
412 | */ | |
413 | mi : 1, /* More information available | |
414 | * call PAL_MC_ERROR_INFO | |
415 | */ | |
416 | pi : 1, /* Precise instruction pointer */ | |
417 | pm : 1, /* Precise min-state save area */ | |
418 | ||
419 | dy : 1, /* Processor dynamic | |
420 | * state valid | |
421 | */ | |
422 | ||
423 | ||
424 | in : 1, /* 0 = MC, 1 = INIT */ | |
425 | rs : 1, /* RSE valid */ | |
426 | cm : 1, /* MC corrected */ | |
427 | ex : 1, /* MC is expected */ | |
428 | cr : 1, /* Control regs valid*/ | |
429 | pc : 1, /* Perf cntrs valid */ | |
430 | dr : 1, /* Debug regs valid */ | |
431 | tr : 1, /* Translation regs | |
432 | * valid | |
433 | */ | |
434 | rr : 1, /* Region regs valid */ | |
435 | ar : 1, /* App regs valid */ | |
436 | br : 1, /* Branch regs valid */ | |
437 | pr : 1, /* Predicate registers | |
438 | * valid | |
439 | */ | |
440 | ||
441 | fp : 1, /* fp registers valid*/ | |
442 | b1 : 1, /* Preserved bank one | |
443 | * general registers | |
444 | * are valid | |
445 | */ | |
446 | b0 : 1, /* Preserved bank zero | |
447 | * general registers | |
448 | * are valid | |
449 | */ | |
450 | gr : 1, /* General registers | |
451 | * are valid | |
452 | * (excl. banked regs) | |
453 | */ | |
454 | dsize : 16, /* size of dynamic | |
455 | * state returned | |
456 | * by the processor | |
457 | */ | |
458 | ||
459 | reserved2 : 11, | |
460 | cc : 1, /* Cache check */ | |
461 | tc : 1, /* TLB check */ | |
462 | bc : 1, /* Bus check */ | |
463 | rc : 1, /* Register file check */ | |
464 | uc : 1; /* Uarch check */ | |
465 | ||
466 | } pal_processor_state_info_t; | |
467 | ||
468 | typedef struct pal_cache_check_info_s { | |
469 | u64 op : 4, /* Type of cache | |
470 | * operation that | |
471 | * caused the machine | |
472 | * check. | |
473 | */ | |
474 | level : 2, /* Cache level */ | |
475 | reserved1 : 2, | |
476 | dl : 1, /* Failure in data part | |
477 | * of cache line | |
478 | */ | |
479 | tl : 1, /* Failure in tag part | |
480 | * of cache line | |
481 | */ | |
482 | dc : 1, /* Failure in dcache */ | |
483 | ic : 1, /* Failure in icache */ | |
484 | mesi : 3, /* Cache line state */ | |
485 | mv : 1, /* mesi valid */ | |
486 | way : 5, /* Way in which the | |
487 | * error occurred | |
488 | */ | |
489 | wiv : 1, /* Way field valid */ | |
490 | reserved2 : 10, | |
491 | ||
492 | index : 20, /* Cache line index */ | |
493 | reserved3 : 2, | |
494 | ||
495 | is : 1, /* instruction set (1 == ia32) */ | |
496 | iv : 1, /* instruction set field valid */ | |
497 | pl : 2, /* privilege level */ | |
498 | pv : 1, /* privilege level field valid */ | |
499 | mcc : 1, /* Machine check corrected */ | |
500 | tv : 1, /* Target address | |
501 | * structure is valid | |
502 | */ | |
503 | rq : 1, /* Requester identifier | |
504 | * structure is valid | |
505 | */ | |
506 | rp : 1, /* Responder identifier | |
507 | * structure is valid | |
508 | */ | |
509 | pi : 1; /* Precise instruction pointer | |
510 | * structure is valid | |
511 | */ | |
512 | } pal_cache_check_info_t; | |
513 | ||
514 | typedef struct pal_tlb_check_info_s { | |
515 | ||
516 | u64 tr_slot : 8, /* Slot# of TR where | |
517 | * error occurred | |
518 | */ | |
519 | trv : 1, /* tr_slot field is valid */ | |
520 | reserved1 : 1, | |
521 | level : 2, /* TLB level where failure occurred */ | |
522 | reserved2 : 4, | |
523 | dtr : 1, /* Fail in data TR */ | |
524 | itr : 1, /* Fail in inst TR */ | |
525 | dtc : 1, /* Fail in data TC */ | |
526 | itc : 1, /* Fail in inst. TC */ | |
527 | op : 4, /* Cache operation */ | |
528 | reserved3 : 30, | |
529 | ||
530 | is : 1, /* instruction set (1 == ia32) */ | |
531 | iv : 1, /* instruction set field valid */ | |
532 | pl : 2, /* privilege level */ | |
533 | pv : 1, /* privilege level field valid */ | |
534 | mcc : 1, /* Machine check corrected */ | |
535 | tv : 1, /* Target address | |
536 | * structure is valid | |
537 | */ | |
538 | rq : 1, /* Requester identifier | |
539 | * structure is valid | |
540 | */ | |
541 | rp : 1, /* Responder identifier | |
542 | * structure is valid | |
543 | */ | |
544 | pi : 1; /* Precise instruction pointer | |
545 | * structure is valid | |
546 | */ | |
547 | } pal_tlb_check_info_t; | |
548 | ||
549 | typedef struct pal_bus_check_info_s { | |
550 | u64 size : 5, /* Xaction size */ | |
551 | ib : 1, /* Internal bus error */ | |
552 | eb : 1, /* External bus error */ | |
553 | cc : 1, /* Error occurred | |
554 | * during cache-cache | |
555 | * transfer. | |
556 | */ | |
557 | type : 8, /* Bus xaction type*/ | |
558 | sev : 5, /* Bus error severity*/ | |
559 | hier : 2, /* Bus hierarchy level */ | |
560 | reserved1 : 1, | |
561 | bsi : 8, /* Bus error status | |
562 | * info | |
563 | */ | |
564 | reserved2 : 22, | |
565 | ||
566 | is : 1, /* instruction set (1 == ia32) */ | |
567 | iv : 1, /* instruction set field valid */ | |
568 | pl : 2, /* privilege level */ | |
569 | pv : 1, /* privilege level field valid */ | |
570 | mcc : 1, /* Machine check corrected */ | |
571 | tv : 1, /* Target address | |
572 | * structure is valid | |
573 | */ | |
574 | rq : 1, /* Requester identifier | |
575 | * structure is valid | |
576 | */ | |
577 | rp : 1, /* Responder identifier | |
578 | * structure is valid | |
579 | */ | |
580 | pi : 1; /* Precise instruction pointer | |
581 | * structure is valid | |
582 | */ | |
583 | } pal_bus_check_info_t; | |
584 | ||
585 | typedef struct pal_reg_file_check_info_s { | |
586 | u64 id : 4, /* Register file identifier */ | |
587 | op : 4, /* Type of register | |
588 | * operation that | |
589 | * caused the machine | |
590 | * check. | |
591 | */ | |
592 | reg_num : 7, /* Register number */ | |
593 | rnv : 1, /* reg_num valid */ | |
594 | reserved2 : 38, | |
595 | ||
596 | is : 1, /* instruction set (1 == ia32) */ | |
597 | iv : 1, /* instruction set field valid */ | |
598 | pl : 2, /* privilege level */ | |
599 | pv : 1, /* privilege level field valid */ | |
600 | mcc : 1, /* Machine check corrected */ | |
601 | reserved3 : 3, | |
602 | pi : 1; /* Precise instruction pointer | |
603 | * structure is valid | |
604 | */ | |
605 | } pal_reg_file_check_info_t; | |
606 | ||
607 | typedef struct pal_uarch_check_info_s { | |
608 | u64 sid : 5, /* Structure identification */ | |
609 | level : 3, /* Level of failure */ | |
610 | array_id : 4, /* Array identification */ | |
611 | op : 4, /* Type of | |
612 | * operation that | |
613 | * caused the machine | |
614 | * check. | |
615 | */ | |
616 | way : 6, /* Way of structure */ | |
617 | wv : 1, /* way valid */ | |
618 | xv : 1, /* index valid */ | |
619 | reserved1 : 8, | |
620 | index : 8, /* Index or set of the uarch | |
621 | * structure that failed. | |
622 | */ | |
623 | reserved2 : 24, | |
624 | ||
625 | is : 1, /* instruction set (1 == ia32) */ | |
626 | iv : 1, /* instruction set field valid */ | |
627 | pl : 2, /* privilege level */ | |
628 | pv : 1, /* privilege level field valid */ | |
629 | mcc : 1, /* Machine check corrected */ | |
630 | tv : 1, /* Target address | |
631 | * structure is valid | |
632 | */ | |
633 | rq : 1, /* Requester identifier | |
634 | * structure is valid | |
635 | */ | |
636 | rp : 1, /* Responder identifier | |
637 | * structure is valid | |
638 | */ | |
639 | pi : 1; /* Precise instruction pointer | |
640 | * structure is valid | |
641 | */ | |
642 | } pal_uarch_check_info_t; | |
643 | ||
644 | typedef union pal_mc_error_info_u { | |
645 | u64 pmei_data; | |
646 | pal_processor_state_info_t pme_processor; | |
647 | pal_cache_check_info_t pme_cache; | |
648 | pal_tlb_check_info_t pme_tlb; | |
649 | pal_bus_check_info_t pme_bus; | |
650 | pal_reg_file_check_info_t pme_reg_file; | |
651 | pal_uarch_check_info_t pme_uarch; | |
652 | } pal_mc_error_info_t; | |
653 | ||
654 | #define pmci_proc_unknown_check pme_processor.uc | |
655 | #define pmci_proc_bus_check pme_processor.bc | |
656 | #define pmci_proc_tlb_check pme_processor.tc | |
657 | #define pmci_proc_cache_check pme_processor.cc | |
658 | #define pmci_proc_dynamic_state_size pme_processor.dsize | |
659 | #define pmci_proc_gpr_valid pme_processor.gr | |
660 | #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0 | |
661 | #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1 | |
662 | #define pmci_proc_fp_valid pme_processor.fp | |
663 | #define pmci_proc_predicate_regs_valid pme_processor.pr | |
664 | #define pmci_proc_branch_regs_valid pme_processor.br | |
665 | #define pmci_proc_app_regs_valid pme_processor.ar | |
666 | #define pmci_proc_region_regs_valid pme_processor.rr | |
667 | #define pmci_proc_translation_regs_valid pme_processor.tr | |
668 | #define pmci_proc_debug_regs_valid pme_processor.dr | |
669 | #define pmci_proc_perf_counters_valid pme_processor.pc | |
670 | #define pmci_proc_control_regs_valid pme_processor.cr | |
671 | #define pmci_proc_machine_check_expected pme_processor.ex | |
672 | #define pmci_proc_machine_check_corrected pme_processor.cm | |
673 | #define pmci_proc_rse_valid pme_processor.rs | |
674 | #define pmci_proc_machine_check_or_init pme_processor.in | |
675 | #define pmci_proc_dynamic_state_valid pme_processor.dy | |
676 | #define pmci_proc_operation pme_processor.op | |
677 | #define pmci_proc_trap_lost pme_processor.tl | |
678 | #define pmci_proc_hardware_damage pme_processor.hd | |
679 | #define pmci_proc_uncontained_storage_damage pme_processor.us | |
680 | #define pmci_proc_machine_check_isolated pme_processor.ci | |
681 | #define pmci_proc_continuable pme_processor.co | |
682 | #define pmci_proc_storage_intergrity_synced pme_processor.sy | |
683 | #define pmci_proc_min_state_save_area_regd pme_processor.mn | |
684 | #define pmci_proc_distinct_multiple_errors pme_processor.me | |
685 | #define pmci_proc_pal_attempted_rendezvous pme_processor.ra | |
686 | #define pmci_proc_pal_rendezvous_complete pme_processor.rz | |
687 | ||
688 | ||
689 | #define pmci_cache_level pme_cache.level | |
690 | #define pmci_cache_line_state pme_cache.mesi | |
691 | #define pmci_cache_line_state_valid pme_cache.mv | |
692 | #define pmci_cache_line_index pme_cache.index | |
693 | #define pmci_cache_instr_cache_fail pme_cache.ic | |
694 | #define pmci_cache_data_cache_fail pme_cache.dc | |
695 | #define pmci_cache_line_tag_fail pme_cache.tl | |
696 | #define pmci_cache_line_data_fail pme_cache.dl | |
697 | #define pmci_cache_operation pme_cache.op | |
698 | #define pmci_cache_way_valid pme_cache.wv | |
699 | #define pmci_cache_target_address_valid pme_cache.tv | |
700 | #define pmci_cache_way pme_cache.way | |
701 | #define pmci_cache_mc pme_cache.mc | |
702 | ||
703 | #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc | |
704 | #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc | |
705 | #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr | |
706 | #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr | |
707 | #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot | |
708 | #define pmci_tlb_mc pme_tlb.mc | |
709 | ||
710 | #define pmci_bus_status_info pme_bus.bsi | |
711 | #define pmci_bus_req_address_valid pme_bus.rq | |
712 | #define pmci_bus_resp_address_valid pme_bus.rp | |
713 | #define pmci_bus_target_address_valid pme_bus.tv | |
714 | #define pmci_bus_error_severity pme_bus.sev | |
715 | #define pmci_bus_transaction_type pme_bus.type | |
716 | #define pmci_bus_cache_cache_transfer pme_bus.cc | |
717 | #define pmci_bus_transaction_size pme_bus.size | |
718 | #define pmci_bus_internal_error pme_bus.ib | |
719 | #define pmci_bus_external_error pme_bus.eb | |
720 | #define pmci_bus_mc pme_bus.mc | |
721 | ||
722 | /* | |
723 | * NOTE: this min_state_save area struct only includes the 1KB | |
724 | * architectural state save area. The other 3 KB is scratch space | |
725 | * for PAL. | |
726 | */ | |
727 | ||
728 | typedef struct pal_min_state_area_s { | |
729 | u64 pmsa_nat_bits; /* nat bits for saved GRs */ | |
730 | u64 pmsa_gr[15]; /* GR1 - GR15 */ | |
731 | u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */ | |
732 | u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */ | |
733 | u64 pmsa_pr; /* predicate registers */ | |
734 | u64 pmsa_br0; /* branch register 0 */ | |
735 | u64 pmsa_rsc; /* ar.rsc */ | |
736 | u64 pmsa_iip; /* cr.iip */ | |
737 | u64 pmsa_ipsr; /* cr.ipsr */ | |
738 | u64 pmsa_ifs; /* cr.ifs */ | |
739 | u64 pmsa_xip; /* previous iip */ | |
740 | u64 pmsa_xpsr; /* previous psr */ | |
741 | u64 pmsa_xfs; /* previous ifs */ | |
742 | u64 pmsa_br1; /* branch register 1 */ | |
743 | u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */ | |
744 | } pal_min_state_area_t; | |
745 | ||
746 | ||
747 | struct ia64_pal_retval { | |
748 | /* | |
749 | * A zero status value indicates call completed without error. | |
750 | * A negative status value indicates reason of call failure. | |
751 | * A positive status value indicates success but an | |
752 | * informational value should be printed (e.g., "reboot for | |
753 | * change to take effect"). | |
754 | */ | |
755 | s64 status; | |
756 | u64 v0; | |
757 | u64 v1; | |
758 | u64 v2; | |
759 | }; | |
760 | ||
761 | /* | |
762 | * Note: Currently unused PAL arguments are generally labeled | |
763 | * "reserved" so the value specified in the PAL documentation | |
764 | * (generally 0) MUST be passed. Reserved parameters are not optional | |
765 | * parameters. | |
766 | */ | |
767 | extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64); | |
768 | extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64); | |
769 | extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64); | |
770 | extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64); | |
771 | extern void ia64_save_scratch_fpregs (struct ia64_fpreg *); | |
772 | extern void ia64_load_scratch_fpregs (struct ia64_fpreg *); | |
773 | ||
774 | #define PAL_CALL(iprv,a0,a1,a2,a3) do { \ | |
775 | struct ia64_fpreg fr[6]; \ | |
776 | ia64_save_scratch_fpregs(fr); \ | |
777 | iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \ | |
778 | ia64_load_scratch_fpregs(fr); \ | |
779 | } while (0) | |
780 | ||
781 | #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do { \ | |
782 | struct ia64_fpreg fr[6]; \ | |
783 | ia64_save_scratch_fpregs(fr); \ | |
784 | iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \ | |
785 | ia64_load_scratch_fpregs(fr); \ | |
786 | } while (0) | |
787 | ||
788 | #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \ | |
789 | struct ia64_fpreg fr[6]; \ | |
790 | ia64_save_scratch_fpregs(fr); \ | |
791 | iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \ | |
792 | ia64_load_scratch_fpregs(fr); \ | |
793 | } while (0) | |
794 | ||
795 | #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \ | |
796 | struct ia64_fpreg fr[6]; \ | |
797 | ia64_save_scratch_fpregs(fr); \ | |
798 | iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \ | |
799 | ia64_load_scratch_fpregs(fr); \ | |
800 | } while (0) | |
801 | ||
802 | #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \ | |
803 | struct ia64_fpreg fr[6]; \ | |
804 | ia64_save_scratch_fpregs(fr); \ | |
805 | iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \ | |
806 | ia64_load_scratch_fpregs(fr); \ | |
807 | } while (0) | |
808 | ||
809 | typedef int (*ia64_pal_handler) (u64, ...); | |
810 | extern ia64_pal_handler ia64_pal; | |
811 | extern void ia64_pal_handler_init (void *); | |
812 | ||
813 | extern ia64_pal_handler ia64_pal; | |
814 | ||
815 | extern pal_cache_config_info_t l0d_cache_config_info; | |
816 | extern pal_cache_config_info_t l0i_cache_config_info; | |
817 | extern pal_cache_config_info_t l1_cache_config_info; | |
818 | extern pal_cache_config_info_t l2_cache_config_info; | |
819 | ||
820 | extern pal_cache_protection_info_t l0d_cache_protection_info; | |
821 | extern pal_cache_protection_info_t l0i_cache_protection_info; | |
822 | extern pal_cache_protection_info_t l1_cache_protection_info; | |
823 | extern pal_cache_protection_info_t l2_cache_protection_info; | |
824 | ||
825 | extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t, | |
826 | pal_cache_type_t); | |
827 | ||
828 | extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t, | |
829 | pal_cache_type_t); | |
830 | ||
831 | ||
832 | extern void pal_error(int); | |
833 | ||
834 | ||
835 | /* Useful wrappers for the current list of pal procedures */ | |
836 | ||
837 | typedef union pal_bus_features_u { | |
838 | u64 pal_bus_features_val; | |
839 | struct { | |
840 | u64 pbf_reserved1 : 29; | |
841 | u64 pbf_req_bus_parking : 1; | |
842 | u64 pbf_bus_lock_mask : 1; | |
843 | u64 pbf_enable_half_xfer_rate : 1; | |
844 | u64 pbf_reserved2 : 22; | |
845 | u64 pbf_disable_xaction_queueing : 1; | |
846 | u64 pbf_disable_resp_err_check : 1; | |
847 | u64 pbf_disable_berr_check : 1; | |
848 | u64 pbf_disable_bus_req_internal_err_signal : 1; | |
849 | u64 pbf_disable_bus_req_berr_signal : 1; | |
850 | u64 pbf_disable_bus_init_event_check : 1; | |
851 | u64 pbf_disable_bus_init_event_signal : 1; | |
852 | u64 pbf_disable_bus_addr_err_check : 1; | |
853 | u64 pbf_disable_bus_addr_err_signal : 1; | |
854 | u64 pbf_disable_bus_data_err_check : 1; | |
855 | } pal_bus_features_s; | |
856 | } pal_bus_features_u_t; | |
857 | ||
858 | extern void pal_bus_features_print (u64); | |
859 | ||
860 | /* Provide information about configurable processor bus features */ | |
861 | static inline s64 | |
862 | ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail, | |
863 | pal_bus_features_u_t *features_status, | |
864 | pal_bus_features_u_t *features_control) | |
865 | { | |
866 | struct ia64_pal_retval iprv; | |
867 | PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0); | |
868 | if (features_avail) | |
869 | features_avail->pal_bus_features_val = iprv.v0; | |
870 | if (features_status) | |
871 | features_status->pal_bus_features_val = iprv.v1; | |
872 | if (features_control) | |
873 | features_control->pal_bus_features_val = iprv.v2; | |
874 | return iprv.status; | |
875 | } | |
876 | ||
877 | /* Enables/disables specific processor bus features */ | |
878 | static inline s64 | |
879 | ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) | |
880 | { | |
881 | struct ia64_pal_retval iprv; | |
882 | PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0); | |
883 | return iprv.status; | |
884 | } | |
885 | ||
886 | /* Get detailed cache information */ | |
887 | static inline s64 | |
888 | ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf) | |
889 | { | |
890 | struct ia64_pal_retval iprv; | |
891 | ||
892 | PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); | |
893 | ||
894 | if (iprv.status == 0) { | |
895 | conf->pcci_status = iprv.status; | |
896 | conf->pcci_info_1.pcci1_data = iprv.v0; | |
897 | conf->pcci_info_2.pcci2_data = iprv.v1; | |
898 | conf->pcci_reserved = iprv.v2; | |
899 | } | |
900 | return iprv.status; | |
901 | ||
902 | } | |
903 | ||
904 | /* Get detailed cche protection information */ | |
905 | static inline s64 | |
906 | ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot) | |
907 | { | |
908 | struct ia64_pal_retval iprv; | |
909 | ||
910 | PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); | |
911 | ||
912 | if (iprv.status == 0) { | |
913 | prot->pcpi_status = iprv.status; | |
914 | prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; | |
915 | prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; | |
916 | prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; | |
917 | prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; | |
918 | prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; | |
919 | prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; | |
920 | } | |
921 | return iprv.status; | |
922 | } | |
923 | ||
924 | /* | |
925 | * Flush the processor instruction or data caches. *PROGRESS must be | |
926 | * initialized to zero before calling this for the first time.. | |
927 | */ | |
928 | static inline s64 | |
929 | ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) | |
930 | { | |
931 | struct ia64_pal_retval iprv; | |
f15ac580 | 932 | PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); |
1da177e4 LT |
933 | if (vector) |
934 | *vector = iprv.v0; | |
935 | *progress = iprv.v1; | |
936 | return iprv.status; | |
937 | } | |
938 | ||
939 | ||
940 | /* Initialize the processor controlled caches */ | |
941 | static inline s64 | |
942 | ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest) | |
943 | { | |
944 | struct ia64_pal_retval iprv; | |
945 | PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest); | |
946 | return iprv.status; | |
947 | } | |
948 | ||
949 | /* Initialize the tags and data of a data or unified cache line of | |
950 | * processor controlled cache to known values without the availability | |
951 | * of backing memory. | |
952 | */ | |
953 | static inline s64 | |
954 | ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) | |
955 | { | |
956 | struct ia64_pal_retval iprv; | |
957 | PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0); | |
958 | return iprv.status; | |
959 | } | |
960 | ||
961 | ||
962 | /* Read the data and tag of a processor controlled cache line for diags */ | |
963 | static inline s64 | |
964 | ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) | |
965 | { | |
966 | struct ia64_pal_retval iprv; | |
b29e7132 RA |
967 | PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data, |
968 | physical_addr, 0); | |
1da177e4 LT |
969 | return iprv.status; |
970 | } | |
971 | ||
972 | /* Return summary information about the heirarchy of caches controlled by the processor */ | |
973 | static inline s64 | |
974 | ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches) | |
975 | { | |
976 | struct ia64_pal_retval iprv; | |
977 | PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0); | |
978 | if (cache_levels) | |
979 | *cache_levels = iprv.v0; | |
980 | if (unique_caches) | |
981 | *unique_caches = iprv.v1; | |
982 | return iprv.status; | |
983 | } | |
984 | ||
985 | /* Write the data and tag of a processor-controlled cache line for diags */ | |
986 | static inline s64 | |
987 | ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) | |
988 | { | |
989 | struct ia64_pal_retval iprv; | |
b29e7132 RA |
990 | PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data, |
991 | physical_addr, data); | |
1da177e4 LT |
992 | return iprv.status; |
993 | } | |
994 | ||
995 | ||
996 | /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */ | |
997 | static inline s64 | |
998 | ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics, | |
999 | u64 *buffer_size, u64 *buffer_align) | |
1000 | { | |
1001 | struct ia64_pal_retval iprv; | |
1002 | PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); | |
1003 | if (buffer_size) | |
1004 | *buffer_size = iprv.v0; | |
1005 | if (buffer_align) | |
1006 | *buffer_align = iprv.v1; | |
1007 | return iprv.status; | |
1008 | } | |
1009 | ||
1010 | /* Copy relocatable PAL procedures from ROM to memory */ | |
1011 | static inline s64 | |
1012 | ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) | |
1013 | { | |
1014 | struct ia64_pal_retval iprv; | |
1015 | PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); | |
1016 | if (pal_proc_offset) | |
1017 | *pal_proc_offset = iprv.v0; | |
1018 | return iprv.status; | |
1019 | } | |
1020 | ||
1021 | /* Return the number of instruction and data debug register pairs */ | |
1022 | static inline s64 | |
1023 | ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs) | |
1024 | { | |
1025 | struct ia64_pal_retval iprv; | |
1026 | PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0); | |
1027 | if (inst_regs) | |
1028 | *inst_regs = iprv.v0; | |
1029 | if (data_regs) | |
1030 | *data_regs = iprv.v1; | |
1031 | ||
1032 | return iprv.status; | |
1033 | } | |
1034 | ||
1035 | #ifdef TBD | |
1036 | /* Switch from IA64-system environment to IA-32 system environment */ | |
1037 | static inline s64 | |
1038 | ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) | |
1039 | { | |
1040 | struct ia64_pal_retval iprv; | |
1041 | PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); | |
1042 | return iprv.status; | |
1043 | } | |
1044 | #endif | |
1045 | ||
1046 | /* Get unique geographical address of this processor on its bus */ | |
1047 | static inline s64 | |
1048 | ia64_pal_fixed_addr (u64 *global_unique_addr) | |
1049 | { | |
1050 | struct ia64_pal_retval iprv; | |
1051 | PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0); | |
1052 | if (global_unique_addr) | |
1053 | *global_unique_addr = iprv.v0; | |
1054 | return iprv.status; | |
1055 | } | |
1056 | ||
1057 | /* Get base frequency of the platform if generated by the processor */ | |
1058 | static inline s64 | |
1059 | ia64_pal_freq_base (u64 *platform_base_freq) | |
1060 | { | |
1061 | struct ia64_pal_retval iprv; | |
1062 | PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0); | |
1063 | if (platform_base_freq) | |
1064 | *platform_base_freq = iprv.v0; | |
1065 | return iprv.status; | |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * Get the ratios for processor frequency, bus frequency and interval timer to | |
1070 | * to base frequency of the platform | |
1071 | */ | |
1072 | static inline s64 | |
1073 | ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio, | |
1074 | struct pal_freq_ratio *itc_ratio) | |
1075 | { | |
1076 | struct ia64_pal_retval iprv; | |
1077 | PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0); | |
1078 | if (proc_ratio) | |
1079 | *(u64 *)proc_ratio = iprv.v0; | |
1080 | if (bus_ratio) | |
1081 | *(u64 *)bus_ratio = iprv.v1; | |
1082 | if (itc_ratio) | |
1083 | *(u64 *)itc_ratio = iprv.v2; | |
1084 | return iprv.status; | |
1085 | } | |
1086 | ||
1087 | /* Make the processor enter HALT or one of the implementation dependent low | |
1088 | * power states where prefetching and execution are suspended and cache and | |
1089 | * TLB coherency is not maintained. | |
1090 | */ | |
1091 | static inline s64 | |
1092 | ia64_pal_halt (u64 halt_state) | |
1093 | { | |
1094 | struct ia64_pal_retval iprv; | |
1095 | PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0); | |
1096 | return iprv.status; | |
1097 | } | |
1098 | ||
1099 | typedef union pal_power_mgmt_info_u { | |
1100 | u64 ppmi_data; | |
1101 | struct { | |
1102 | u64 exit_latency : 16, | |
1103 | entry_latency : 16, | |
1104 | power_consumption : 28, | |
1105 | im : 1, | |
1106 | co : 1, | |
1107 | reserved : 2; | |
1108 | } pal_power_mgmt_info_s; | |
1109 | } pal_power_mgmt_info_u_t; | |
1110 | ||
1111 | /* Return information about processor's optional power management capabilities. */ | |
1112 | static inline s64 | |
1113 | ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) | |
1114 | { | |
1115 | struct ia64_pal_retval iprv; | |
1116 | PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0); | |
1117 | return iprv.status; | |
1118 | } | |
1119 | ||
4db8699b VP |
1120 | /* Get the current P-state information */ |
1121 | static inline s64 | |
1122 | ia64_pal_get_pstate (u64 *pstate_index) | |
1123 | { | |
1124 | struct ia64_pal_retval iprv; | |
1125 | PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0); | |
1126 | *pstate_index = iprv.v0; | |
1127 | return iprv.status; | |
1128 | } | |
1129 | ||
1130 | /* Set the P-state */ | |
1131 | static inline s64 | |
1132 | ia64_pal_set_pstate (u64 pstate_index) | |
1133 | { | |
1134 | struct ia64_pal_retval iprv; | |
1135 | PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0); | |
1136 | return iprv.status; | |
1137 | } | |
1138 | ||
76d08bb3 TL |
1139 | /* Processor branding information*/ |
1140 | static inline s64 | |
1141 | ia64_pal_get_brand_info (char *brand_info) | |
1142 | { | |
1143 | struct ia64_pal_retval iprv; | |
1144 | PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0); | |
1145 | return iprv.status; | |
1146 | } | |
1147 | ||
1da177e4 LT |
1148 | /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are |
1149 | * suspended, but cache and TLB coherency is maintained. | |
1150 | */ | |
1151 | static inline s64 | |
1152 | ia64_pal_halt_light (void) | |
1153 | { | |
1154 | struct ia64_pal_retval iprv; | |
1155 | PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0); | |
1156 | return iprv.status; | |
1157 | } | |
1158 | ||
1159 | /* Clear all the processor error logging registers and reset the indicator that allows | |
1160 | * the error logging registers to be written. This procedure also checks the pending | |
1161 | * machine check bit and pending INIT bit and reports their states. | |
1162 | */ | |
1163 | static inline s64 | |
1164 | ia64_pal_mc_clear_log (u64 *pending_vector) | |
1165 | { | |
1166 | struct ia64_pal_retval iprv; | |
1167 | PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0); | |
1168 | if (pending_vector) | |
1169 | *pending_vector = iprv.v0; | |
1170 | return iprv.status; | |
1171 | } | |
1172 | ||
1173 | /* Ensure that all outstanding transactions in a processor are completed or that any | |
1174 | * MCA due to thes outstanding transaction is taken. | |
1175 | */ | |
1176 | static inline s64 | |
1177 | ia64_pal_mc_drain (void) | |
1178 | { | |
1179 | struct ia64_pal_retval iprv; | |
1180 | PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0); | |
1181 | return iprv.status; | |
1182 | } | |
1183 | ||
1184 | /* Return the machine check dynamic processor state */ | |
1185 | static inline s64 | |
1186 | ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds) | |
1187 | { | |
1188 | struct ia64_pal_retval iprv; | |
1189 | PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0); | |
1190 | if (size) | |
1191 | *size = iprv.v0; | |
1192 | if (pds) | |
1193 | *pds = iprv.v1; | |
1194 | return iprv.status; | |
1195 | } | |
1196 | ||
1197 | /* Return processor machine check information */ | |
1198 | static inline s64 | |
1199 | ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) | |
1200 | { | |
1201 | struct ia64_pal_retval iprv; | |
1202 | PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0); | |
1203 | if (size) | |
1204 | *size = iprv.v0; | |
1205 | if (error_info) | |
1206 | *error_info = iprv.v1; | |
1207 | return iprv.status; | |
1208 | } | |
1209 | ||
1210 | /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot | |
1211 | * attempt to correct any expected machine checks. | |
1212 | */ | |
1213 | static inline s64 | |
1214 | ia64_pal_mc_expected (u64 expected, u64 *previous) | |
1215 | { | |
1216 | struct ia64_pal_retval iprv; | |
1217 | PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0); | |
1218 | if (previous) | |
1219 | *previous = iprv.v0; | |
1220 | return iprv.status; | |
1221 | } | |
1222 | ||
1223 | /* Register a platform dependent location with PAL to which it can save | |
1224 | * minimal processor state in the event of a machine check or initialization | |
1225 | * event. | |
1226 | */ | |
1227 | static inline s64 | |
1228 | ia64_pal_mc_register_mem (u64 physical_addr) | |
1229 | { | |
1230 | struct ia64_pal_retval iprv; | |
1231 | PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0); | |
1232 | return iprv.status; | |
1233 | } | |
1234 | ||
1235 | /* Restore minimal architectural processor state, set CMC interrupt if necessary | |
1236 | * and resume execution | |
1237 | */ | |
1238 | static inline s64 | |
1239 | ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) | |
1240 | { | |
1241 | struct ia64_pal_retval iprv; | |
1242 | PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0); | |
1243 | return iprv.status; | |
1244 | } | |
1245 | ||
1246 | /* Return the memory attributes implemented by the processor */ | |
1247 | static inline s64 | |
1248 | ia64_pal_mem_attrib (u64 *mem_attrib) | |
1249 | { | |
1250 | struct ia64_pal_retval iprv; | |
1251 | PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0); | |
1252 | if (mem_attrib) | |
1253 | *mem_attrib = iprv.v0 & 0xff; | |
1254 | return iprv.status; | |
1255 | } | |
1256 | ||
1257 | /* Return the amount of memory needed for second phase of processor | |
1258 | * self-test and the required alignment of memory. | |
1259 | */ | |
1260 | static inline s64 | |
1261 | ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment) | |
1262 | { | |
1263 | struct ia64_pal_retval iprv; | |
1264 | PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0); | |
1265 | if (bytes_needed) | |
1266 | *bytes_needed = iprv.v0; | |
1267 | if (alignment) | |
1268 | *alignment = iprv.v1; | |
1269 | return iprv.status; | |
1270 | } | |
1271 | ||
1272 | typedef union pal_perf_mon_info_u { | |
1273 | u64 ppmi_data; | |
1274 | struct { | |
1275 | u64 generic : 8, | |
1276 | width : 8, | |
1277 | cycles : 8, | |
1278 | retired : 8, | |
1279 | reserved : 32; | |
1280 | } pal_perf_mon_info_s; | |
1281 | } pal_perf_mon_info_u_t; | |
1282 | ||
1283 | /* Return the performance monitor information about what can be counted | |
1284 | * and how to configure the monitors to count the desired events. | |
1285 | */ | |
1286 | static inline s64 | |
1287 | ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) | |
1288 | { | |
1289 | struct ia64_pal_retval iprv; | |
1290 | PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0); | |
1291 | if (pm_info) | |
1292 | pm_info->ppmi_data = iprv.v0; | |
1293 | return iprv.status; | |
1294 | } | |
1295 | ||
1296 | /* Specifies the physical address of the processor interrupt block | |
1297 | * and I/O port space. | |
1298 | */ | |
1299 | static inline s64 | |
1300 | ia64_pal_platform_addr (u64 type, u64 physical_addr) | |
1301 | { | |
1302 | struct ia64_pal_retval iprv; | |
1303 | PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0); | |
1304 | return iprv.status; | |
1305 | } | |
1306 | ||
1307 | /* Set the SAL PMI entrypoint in memory */ | |
1308 | static inline s64 | |
1309 | ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) | |
1310 | { | |
1311 | struct ia64_pal_retval iprv; | |
1312 | PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0); | |
1313 | return iprv.status; | |
1314 | } | |
1315 | ||
1316 | struct pal_features_s; | |
1317 | /* Provide information about configurable processor features */ | |
1318 | static inline s64 | |
1319 | ia64_pal_proc_get_features (u64 *features_avail, | |
1320 | u64 *features_status, | |
1321 | u64 *features_control) | |
1322 | { | |
1323 | struct ia64_pal_retval iprv; | |
1324 | PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0); | |
1325 | if (iprv.status == 0) { | |
1326 | *features_avail = iprv.v0; | |
1327 | *features_status = iprv.v1; | |
1328 | *features_control = iprv.v2; | |
1329 | } | |
1330 | return iprv.status; | |
1331 | } | |
1332 | ||
1333 | /* Enable/disable processor dependent features */ | |
1334 | static inline s64 | |
1335 | ia64_pal_proc_set_features (u64 feature_select) | |
1336 | { | |
1337 | struct ia64_pal_retval iprv; | |
1338 | PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0); | |
1339 | return iprv.status; | |
1340 | } | |
1341 | ||
1342 | /* | |
1343 | * Put everything in a struct so we avoid the global offset table whenever | |
1344 | * possible. | |
1345 | */ | |
1346 | typedef struct ia64_ptce_info_s { | |
1347 | u64 base; | |
1348 | u32 count[2]; | |
1349 | u32 stride[2]; | |
1350 | } ia64_ptce_info_t; | |
1351 | ||
1352 | /* Return the information required for the architected loop used to purge | |
1353 | * (initialize) the entire TC | |
1354 | */ | |
1355 | static inline s64 | |
1356 | ia64_get_ptce (ia64_ptce_info_t *ptce) | |
1357 | { | |
1358 | struct ia64_pal_retval iprv; | |
1359 | ||
1360 | if (!ptce) | |
1361 | return -1; | |
1362 | ||
1363 | PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0); | |
1364 | if (iprv.status == 0) { | |
1365 | ptce->base = iprv.v0; | |
1366 | ptce->count[0] = iprv.v1 >> 32; | |
1367 | ptce->count[1] = iprv.v1 & 0xffffffff; | |
1368 | ptce->stride[0] = iprv.v2 >> 32; | |
1369 | ptce->stride[1] = iprv.v2 & 0xffffffff; | |
1370 | } | |
1371 | return iprv.status; | |
1372 | } | |
1373 | ||
1374 | /* Return info about implemented application and control registers. */ | |
1375 | static inline s64 | |
1376 | ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) | |
1377 | { | |
1378 | struct ia64_pal_retval iprv; | |
1379 | PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0); | |
1380 | if (reg_info_1) | |
1381 | *reg_info_1 = iprv.v0; | |
1382 | if (reg_info_2) | |
1383 | *reg_info_2 = iprv.v1; | |
1384 | return iprv.status; | |
1385 | } | |
1386 | ||
1387 | typedef union pal_hints_u { | |
1388 | u64 ph_data; | |
1389 | struct { | |
1390 | u64 si : 1, | |
1391 | li : 1, | |
1392 | reserved : 62; | |
1393 | } pal_hints_s; | |
1394 | } pal_hints_u_t; | |
1395 | ||
1396 | /* Return information about the register stack and RSE for this processor | |
1397 | * implementation. | |
1398 | */ | |
1399 | static inline s64 | |
1400 | ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints) | |
1401 | { | |
1402 | struct ia64_pal_retval iprv; | |
1403 | PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0); | |
1404 | if (num_phys_stacked) | |
1405 | *num_phys_stacked = iprv.v0; | |
1406 | if (hints) | |
1407 | hints->ph_data = iprv.v1; | |
1408 | return iprv.status; | |
1409 | } | |
1410 | ||
1411 | /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are | |
1412 | * suspended, but cause cache and TLB coherency to be maintained. | |
1413 | * This is usually called in IA-32 mode. | |
1414 | */ | |
1415 | static inline s64 | |
1416 | ia64_pal_shutdown (void) | |
1417 | { | |
1418 | struct ia64_pal_retval iprv; | |
1419 | PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0); | |
1420 | return iprv.status; | |
1421 | } | |
1422 | ||
1423 | /* Perform the second phase of processor self-test. */ | |
1424 | static inline s64 | |
1425 | ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state) | |
1426 | { | |
1427 | struct ia64_pal_retval iprv; | |
1428 | PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes); | |
1429 | if (self_test_state) | |
1430 | *self_test_state = iprv.v0; | |
1431 | return iprv.status; | |
1432 | } | |
1433 | ||
1434 | typedef union pal_version_u { | |
1435 | u64 pal_version_val; | |
1436 | struct { | |
1437 | u64 pv_pal_b_rev : 8; | |
1438 | u64 pv_pal_b_model : 8; | |
1439 | u64 pv_reserved1 : 8; | |
1440 | u64 pv_pal_vendor : 8; | |
1441 | u64 pv_pal_a_rev : 8; | |
1442 | u64 pv_pal_a_model : 8; | |
1443 | u64 pv_reserved2 : 16; | |
1444 | } pal_version_s; | |
1445 | } pal_version_u_t; | |
1446 | ||
1447 | ||
1bf1eba7 MW |
1448 | /* |
1449 | * Return PAL version information. While the documentation states that | |
1450 | * PAL_VERSION can be called in either physical or virtual mode, some | |
1451 | * implementations only allow physical calls. We don't call it very often, | |
1452 | * so the overhead isn't worth eliminating. | |
1453 | */ | |
1da177e4 LT |
1454 | static inline s64 |
1455 | ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) | |
1456 | { | |
1457 | struct ia64_pal_retval iprv; | |
1458 | PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0); | |
1459 | if (pal_min_version) | |
1460 | pal_min_version->pal_version_val = iprv.v0; | |
1461 | ||
1462 | if (pal_cur_version) | |
1463 | pal_cur_version->pal_version_val = iprv.v1; | |
1464 | ||
1465 | return iprv.status; | |
1466 | } | |
1467 | ||
1468 | typedef union pal_tc_info_u { | |
1469 | u64 pti_val; | |
1470 | struct { | |
1471 | u64 num_sets : 8, | |
1472 | associativity : 8, | |
1473 | num_entries : 16, | |
1474 | pf : 1, | |
1475 | unified : 1, | |
1476 | reduce_tr : 1, | |
1477 | reserved : 29; | |
1478 | } pal_tc_info_s; | |
1479 | } pal_tc_info_u_t; | |
1480 | ||
1481 | #define tc_reduce_tr pal_tc_info_s.reduce_tr | |
1482 | #define tc_unified pal_tc_info_s.unified | |
1483 | #define tc_pf pal_tc_info_s.pf | |
1484 | #define tc_num_entries pal_tc_info_s.num_entries | |
1485 | #define tc_associativity pal_tc_info_s.associativity | |
1486 | #define tc_num_sets pal_tc_info_s.num_sets | |
1487 | ||
1488 | ||
1489 | /* Return information about the virtual memory characteristics of the processor | |
1490 | * implementation. | |
1491 | */ | |
1492 | static inline s64 | |
1493 | ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages) | |
1494 | { | |
1495 | struct ia64_pal_retval iprv; | |
1496 | PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0); | |
1497 | if (tc_info) | |
1498 | tc_info->pti_val = iprv.v0; | |
1499 | if (tc_pages) | |
1500 | *tc_pages = iprv.v1; | |
1501 | return iprv.status; | |
1502 | } | |
1503 | ||
1504 | /* Get page size information about the virtual memory characteristics of the processor | |
1505 | * implementation. | |
1506 | */ | |
1507 | static inline s64 | |
1508 | ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages) | |
1509 | { | |
1510 | struct ia64_pal_retval iprv; | |
1511 | PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0); | |
1512 | if (tr_pages) | |
1513 | *tr_pages = iprv.v0; | |
1514 | if (vw_pages) | |
1515 | *vw_pages = iprv.v1; | |
1516 | return iprv.status; | |
1517 | } | |
1518 | ||
1519 | typedef union pal_vm_info_1_u { | |
1520 | u64 pvi1_val; | |
1521 | struct { | |
1522 | u64 vw : 1, | |
1523 | phys_add_size : 7, | |
1524 | key_size : 8, | |
1525 | max_pkr : 8, | |
1526 | hash_tag_id : 8, | |
1527 | max_dtr_entry : 8, | |
1528 | max_itr_entry : 8, | |
1529 | max_unique_tcs : 8, | |
1530 | num_tc_levels : 8; | |
1531 | } pal_vm_info_1_s; | |
1532 | } pal_vm_info_1_u_t; | |
1533 | ||
1534 | typedef union pal_vm_info_2_u { | |
1535 | u64 pvi2_val; | |
1536 | struct { | |
1537 | u64 impl_va_msb : 8, | |
1538 | rid_size : 8, | |
1539 | reserved : 48; | |
1540 | } pal_vm_info_2_s; | |
1541 | } pal_vm_info_2_u_t; | |
1542 | ||
1543 | /* Get summary information about the virtual memory characteristics of the processor | |
1544 | * implementation. | |
1545 | */ | |
1546 | static inline s64 | |
1547 | ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) | |
1548 | { | |
1549 | struct ia64_pal_retval iprv; | |
1550 | PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0); | |
1551 | if (vm_info_1) | |
1552 | vm_info_1->pvi1_val = iprv.v0; | |
1553 | if (vm_info_2) | |
1554 | vm_info_2->pvi2_val = iprv.v1; | |
1555 | return iprv.status; | |
1556 | } | |
1557 | ||
1558 | typedef union pal_itr_valid_u { | |
1559 | u64 piv_val; | |
1560 | struct { | |
1561 | u64 access_rights_valid : 1, | |
1562 | priv_level_valid : 1, | |
1563 | dirty_bit_valid : 1, | |
1564 | mem_attr_valid : 1, | |
1565 | reserved : 60; | |
1566 | } pal_tr_valid_s; | |
1567 | } pal_tr_valid_u_t; | |
1568 | ||
1569 | /* Read a translation register */ | |
1570 | static inline s64 | |
1571 | ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) | |
1572 | { | |
1573 | struct ia64_pal_retval iprv; | |
1574 | PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer)); | |
1575 | if (tr_valid) | |
1576 | tr_valid->piv_val = iprv.v0; | |
1577 | return iprv.status; | |
1578 | } | |
1579 | ||
1580 | /* | |
1581 | * PAL_PREFETCH_VISIBILITY transaction types | |
1582 | */ | |
1583 | #define PAL_VISIBILITY_VIRTUAL 0 | |
1584 | #define PAL_VISIBILITY_PHYSICAL 1 | |
1585 | ||
1586 | /* | |
1587 | * PAL_PREFETCH_VISIBILITY return codes | |
1588 | */ | |
1589 | #define PAL_VISIBILITY_OK 1 | |
1590 | #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0 | |
1591 | #define PAL_VISIBILITY_INVAL_ARG -2 | |
1592 | #define PAL_VISIBILITY_ERROR -3 | |
1593 | ||
1594 | static inline s64 | |
1595 | ia64_pal_prefetch_visibility (s64 trans_type) | |
1596 | { | |
1597 | struct ia64_pal_retval iprv; | |
1598 | PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0); | |
1599 | return iprv.status; | |
1600 | } | |
1601 | ||
e927ecb0 SS |
1602 | /* data structure for getting information on logical to physical mappings */ |
1603 | typedef union pal_log_overview_u { | |
1604 | struct { | |
1605 | u64 num_log :16, /* Total number of logical | |
1606 | * processors on this die | |
1607 | */ | |
1608 | tpc :8, /* Threads per core */ | |
1609 | reserved3 :8, /* Reserved */ | |
1610 | cpp :8, /* Cores per processor */ | |
1611 | reserved2 :8, /* Reserved */ | |
1612 | ppid :8, /* Physical processor ID */ | |
1613 | reserved1 :8; /* Reserved */ | |
1614 | } overview_bits; | |
1615 | u64 overview_data; | |
1616 | } pal_log_overview_t; | |
1617 | ||
1618 | typedef union pal_proc_n_log_info1_u{ | |
1619 | struct { | |
1620 | u64 tid :16, /* Thread id */ | |
1621 | reserved2 :16, /* Reserved */ | |
1622 | cid :16, /* Core id */ | |
1623 | reserved1 :16; /* Reserved */ | |
1624 | } ppli1_bits; | |
1625 | u64 ppli1_data; | |
1626 | } pal_proc_n_log_info1_t; | |
1627 | ||
1628 | typedef union pal_proc_n_log_info2_u { | |
1629 | struct { | |
1630 | u64 la :16, /* Logical address */ | |
1631 | reserved :48; /* Reserved */ | |
1632 | } ppli2_bits; | |
1633 | u64 ppli2_data; | |
1634 | } pal_proc_n_log_info2_t; | |
1635 | ||
1636 | typedef struct pal_logical_to_physical_s | |
1637 | { | |
1638 | pal_log_overview_t overview; | |
1639 | pal_proc_n_log_info1_t ppli1; | |
1640 | pal_proc_n_log_info2_t ppli2; | |
1641 | } pal_logical_to_physical_t; | |
1642 | ||
1643 | #define overview_num_log overview.overview_bits.num_log | |
1644 | #define overview_tpc overview.overview_bits.tpc | |
1645 | #define overview_cpp overview.overview_bits.cpp | |
1646 | #define overview_ppid overview.overview_bits.ppid | |
1647 | #define log1_tid ppli1.ppli1_bits.tid | |
1648 | #define log1_cid ppli1.ppli1_bits.cid | |
1649 | #define log2_la ppli2.ppli2_bits.la | |
1650 | ||
1651 | /* Get information on logical to physical processor mappings. */ | |
1652 | static inline s64 | |
1653 | ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping) | |
1654 | { | |
1655 | struct ia64_pal_retval iprv; | |
1656 | ||
1657 | PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0); | |
1658 | ||
1659 | if (iprv.status == PAL_STATUS_SUCCESS) | |
1660 | { | |
4129a953 | 1661 | mapping->overview.overview_data = iprv.v0; |
e927ecb0 SS |
1662 | mapping->ppli1.ppli1_data = iprv.v1; |
1663 | mapping->ppli2.ppli2_data = iprv.v2; | |
1664 | } | |
1665 | ||
1666 | return iprv.status; | |
1667 | } | |
f1918005 ZY |
1668 | |
1669 | typedef struct pal_cache_shared_info_s | |
1670 | { | |
1671 | u64 num_shared; | |
1672 | pal_proc_n_log_info1_t ppli1; | |
1673 | pal_proc_n_log_info2_t ppli2; | |
1674 | } pal_cache_shared_info_t; | |
1675 | ||
1676 | /* Get information on logical to physical processor mappings. */ | |
1677 | static inline s64 | |
1678 | ia64_pal_cache_shared_info(u64 level, | |
1679 | u64 type, | |
1680 | u64 proc_number, | |
1681 | pal_cache_shared_info_t *info) | |
1682 | { | |
1683 | struct ia64_pal_retval iprv; | |
1684 | ||
1685 | PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number); | |
1686 | ||
1687 | if (iprv.status == PAL_STATUS_SUCCESS) { | |
1688 | info->num_shared = iprv.v0; | |
1689 | info->ppli1.ppli1_data = iprv.v1; | |
1690 | info->ppli2.ppli2_data = iprv.v2; | |
1691 | } | |
1692 | ||
1693 | return iprv.status; | |
1694 | } | |
1da177e4 LT |
1695 | #endif /* __ASSEMBLY__ */ |
1696 | ||
1697 | #endif /* _ASM_IA64_PAL_H */ |