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1da177e4 LT |
1 | #ifndef _ASM_IA64_PCI_H |
2 | #define _ASM_IA64_PCI_H | |
3 | ||
4 | #include <linux/mm.h> | |
5 | #include <linux/slab.h> | |
6 | #include <linux/spinlock.h> | |
7 | #include <linux/string.h> | |
8 | #include <linux/types.h> | |
9 | ||
10 | #include <asm/io.h> | |
11 | #include <asm/scatterlist.h> | |
12 | ||
13 | /* | |
14 | * Can be used to override the logic in pci_scan_bus for skipping already-configured bus | |
15 | * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the | |
16 | * loader. | |
17 | */ | |
18 | #define pcibios_assign_all_busses() 0 | |
19 | #define pcibios_scan_all_fns(a, b) 0 | |
20 | ||
21 | #define PCIBIOS_MIN_IO 0x1000 | |
22 | #define PCIBIOS_MIN_MEM 0x10000000 | |
23 | ||
24 | void pcibios_config_init(void); | |
25 | ||
26 | struct pci_dev; | |
27 | ||
28 | /* | |
3efe2d84 MW |
29 | * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct |
30 | * correspondence between device bus addresses and CPU physical addresses. | |
31 | * Platforms with a hardware I/O MMU _must_ turn this off to suppress the | |
32 | * bounce buffer handling code in the block and network device layers. | |
33 | * Platforms with separate bus address spaces _must_ turn this off and provide | |
34 | * a device DMA mapping implementation that takes care of the necessary | |
1da177e4 LT |
35 | * address translation. |
36 | * | |
3efe2d84 MW |
37 | * For now, the ia64 platforms which may have separate/multiple bus address |
38 | * spaces all have I/O MMUs which support the merging of physically | |
39 | * discontiguous buffers, so we can use that as the sole factor to determine | |
40 | * the setting of PCI_DMA_BUS_IS_PHYS. | |
1da177e4 LT |
41 | */ |
42 | extern unsigned long ia64_max_iommu_merge_mask; | |
43 | #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) | |
44 | ||
45 | static inline void | |
46 | pcibios_set_master (struct pci_dev *dev) | |
47 | { | |
48 | /* No special bus mastering setup handling */ | |
49 | } | |
50 | ||
51 | static inline void | |
c9c3e457 | 52 | pcibios_penalize_isa_irq (int irq, int active) |
1da177e4 LT |
53 | { |
54 | /* We don't do dynamic PCI IRQ allocation */ | |
55 | } | |
56 | ||
1da177e4 LT |
57 | #include <asm-generic/pci-dma-compat.h> |
58 | ||
59 | /* pci_unmap_{single,page} is not a nop, thus... */ | |
60 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ | |
61 | dma_addr_t ADDR_NAME; | |
62 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ | |
63 | __u32 LEN_NAME; | |
64 | #define pci_unmap_addr(PTR, ADDR_NAME) \ | |
65 | ((PTR)->ADDR_NAME) | |
66 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ | |
67 | (((PTR)->ADDR_NAME) = (VAL)) | |
68 | #define pci_unmap_len(PTR, LEN_NAME) \ | |
69 | ((PTR)->LEN_NAME) | |
70 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ | |
71 | (((PTR)->LEN_NAME) = (VAL)) | |
72 | ||
73 | /* The ia64 platform always supports 64-bit addressing. */ | |
74 | #define pci_dac_dma_supported(pci_dev, mask) (1) | |
75 | #define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off)) | |
76 | #define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr))) | |
77 | #define pci_dac_dma_to_offset(dev,dma_addr) offset_in_page(dma_addr) | |
78 | #define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0) | |
79 | #define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0) | |
80 | ||
bb4a61b6 | 81 | #ifdef CONFIG_PCI |
e24c2d96 DM |
82 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
83 | enum pci_dma_burst_strategy *strat, | |
84 | unsigned long *strategy_parameter) | |
85 | { | |
86 | unsigned long cacheline_size; | |
87 | u8 byte; | |
88 | ||
89 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); | |
90 | if (byte == 0) | |
91 | cacheline_size = 1024; | |
92 | else | |
93 | cacheline_size = (int) byte * 4; | |
94 | ||
95 | *strat = PCI_DMA_BURST_MULTIPLE; | |
96 | *strategy_parameter = cacheline_size; | |
97 | } | |
bb4a61b6 | 98 | #endif |
e24c2d96 | 99 | |
1da177e4 LT |
100 | #define HAVE_PCI_MMAP |
101 | extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
102 | enum pci_mmap_state mmap_state, int write_combine); | |
103 | #define HAVE_PCI_LEGACY | |
104 | extern int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
105 | struct vm_area_struct *vma); | |
106 | extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off, | |
107 | size_t count); | |
108 | extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off, | |
109 | size_t count); | |
110 | extern int pci_mmap_legacy_mem(struct kobject *kobj, | |
111 | struct bin_attribute *attr, | |
112 | struct vm_area_struct *vma); | |
113 | ||
114 | #define pci_get_legacy_mem platform_pci_get_legacy_mem | |
115 | #define pci_legacy_read platform_pci_legacy_read | |
116 | #define pci_legacy_write platform_pci_legacy_write | |
117 | ||
118 | struct pci_window { | |
119 | struct resource resource; | |
120 | u64 offset; | |
121 | }; | |
122 | ||
123 | struct pci_controller { | |
124 | void *acpi_handle; | |
125 | void *iommu; | |
126 | int segment; | |
514604c6 | 127 | int node; /* nearest node with memory or -1 for global allocation */ |
1da177e4 LT |
128 | |
129 | unsigned int windows; | |
130 | struct pci_window *window; | |
131 | ||
132 | void *platform_data; | |
133 | }; | |
134 | ||
135 | #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) | |
136 | #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment) | |
137 | ||
138 | extern struct pci_ops pci_root_ops; | |
139 | ||
140 | static inline int pci_proc_domain(struct pci_bus *bus) | |
141 | { | |
142 | return (pci_domain_nr(bus) != 0); | |
143 | } | |
144 | ||
145 | static inline void pcibios_add_platform_entries(struct pci_dev *dev) | |
146 | { | |
147 | } | |
148 | ||
149 | extern void pcibios_resource_to_bus(struct pci_dev *dev, | |
150 | struct pci_bus_region *region, struct resource *res); | |
151 | ||
152 | extern void pcibios_bus_to_resource(struct pci_dev *dev, | |
153 | struct resource *res, struct pci_bus_region *region); | |
154 | ||
085ae41f DM |
155 | static inline struct resource * |
156 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) | |
157 | { | |
158 | struct resource *root = NULL; | |
159 | ||
160 | if (res->flags & IORESOURCE_IO) | |
161 | root = &ioport_resource; | |
162 | if (res->flags & IORESOURCE_MEM) | |
163 | root = &iomem_resource; | |
164 | ||
165 | return root; | |
166 | } | |
167 | ||
1da177e4 LT |
168 | #define pcibios_scan_all_fns(a, b) 0 |
169 | ||
677c0a78 BZ |
170 | #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ |
171 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |
172 | { | |
173 | return channel ? 15 : 14; | |
174 | } | |
175 | ||
1da177e4 | 176 | #endif /* _ASM_IA64_PCI_H */ |