[mirror_ubuntu-artful-kernel.git] / include / asm-m68k / io.h

/*
 * linux/include/asm-m68k/io.h
 *
 * 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
 *              IO access
 *            - added Q40 support
 *            - added skeleton for GG-II and Amiga PCMCIA
 * 2/3/01 RZ: - moved a few more defs into raw_io.h
 *
 * inX/outX/readX/writeX should not be used by any driver unless it does
 * ISA or PCI access. Other drivers should use function defined in raw_io.h
 * or define its own macros on top of these.
 *
 *    inX(),outX()              are for PCI and ISA I/O
 *    readX(),writeX()          are for PCI memory
 *    isa_readX(),isa_writeX()  are for ISA memory
 *
 * moved mem{cpy,set}_*io inside CONFIG_PCI
 */

#ifndef _IO_H
#define _IO_H

#ifdef __KERNEL__

#include <linux/compiler.h>
#include <asm/raw_io.h>
#include <asm/virtconvert.h>

#include <asm-generic/iomap.h>

#ifdef CONFIG_ATARI
#include <asm/atarihw.h>
#endif


/*
 * IO/MEM definitions for various ISA bridges
 */


#ifdef CONFIG_Q40

#define q40_isa_io_base  0xff400000
#define q40_isa_mem_base 0xff800000

#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+  4*((unsigned long)(ioaddr)))
#define Q40_ISA_MEM_B(madr)  (q40_isa_mem_base+1+4*((unsigned long)(madr)))
#define Q40_ISA_MEM_W(madr)  (q40_isa_mem_base+  4*((unsigned long)(madr)))

#define MULTI_ISA 0
#endif /* Q40 */

/* GG-II Zorro to ISA bridge */
#ifdef CONFIG_GG2

extern unsigned long gg2_isa_base;
#define GG2_ISA_IO_B(ioaddr) (gg2_isa_base+1+((unsigned long)(ioaddr)*4))
#define GG2_ISA_IO_W(ioaddr) (gg2_isa_base+  ((unsigned long)(ioaddr)*4))
#define GG2_ISA_MEM_B(madr)  (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff))
#define GG2_ISA_MEM_W(madr)  (gg2_isa_base+  (((unsigned long)(madr)*4) & 0xfffff))

#ifndef MULTI_ISA
#define MULTI_ISA 0
#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
#endif /* GG2 */

#ifdef CONFIG_AMIGA_PCMCIA
#include <asm/amigayle.h>

#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )

#ifndef MULTI_ISA
#define MULTI_ISA 0
#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
#endif /* AMIGA_PCMCIA */


#ifdef CONFIG_ISA

#if MULTI_ISA == 0
#undef MULTI_ISA
#endif

#define Q40_ISA (1)
#define GG2_ISA (2)
#define AG_ISA  (3)

#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
#define ISA_TYPE Q40_ISA
#define ISA_SEX  0
#endif
#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
#define ISA_TYPE AG_ISA
#define ISA_SEX  1
#endif
#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
#define ISA_TYPE GG2_ISA
#define ISA_SEX  0
#endif

#ifdef MULTI_ISA
extern int isa_type;
extern int isa_sex;

#define ISA_TYPE isa_type
#define ISA_SEX  isa_sex
#endif

/*
 * define inline addr translation functions. Normally only one variant will
 * be compiled in so the case statement will be optimised away
 */

static inline u8 __iomem *isa_itb(unsigned long addr)
{
  switch(ISA_TYPE)
    {
#ifdef CONFIG_Q40
    case Q40_ISA: return (u8 __iomem *)Q40_ISA_IO_B(addr);
#endif
#ifdef CONFIG_GG2
    case GG2_ISA: return (u8 __iomem *)GG2_ISA_IO_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
    case AG_ISA: return (u8 __iomem *)AG_ISA_IO_B(addr);
#endif
    default: return NULL; /* avoid warnings, just in case */
    }
}
static inline u16 __iomem *isa_itw(unsigned long addr)
{
  switch(ISA_TYPE)
    {
#ifdef CONFIG_Q40
    case Q40_ISA: return (u16 __iomem *)Q40_ISA_IO_W(addr);
#endif
#ifdef CONFIG_GG2
    case GG2_ISA: return (u16 __iomem *)GG2_ISA_IO_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
    case AG_ISA: return (u16 __iomem *)AG_ISA_IO_W(addr);
#endif
    default: return NULL; /* avoid warnings, just in case */
    }
}
static inline u32 __iomem *isa_itl(unsigned long addr)
{
  switch(ISA_TYPE)
    {
#ifdef CONFIG_AMIGA_PCMCIA
    case AG_ISA: return (u32 __iomem *)AG_ISA_IO_W(addr);
#endif
    default: return 0; /* avoid warnings, just in case */
    }
}
static inline u8 __iomem *isa_mtb(unsigned long addr)
{
  switch(ISA_TYPE)
    {
#ifdef CONFIG_Q40
    case Q40_ISA: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_GG2
    case GG2_ISA: return (u8 __iomem *)GG2_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
    case AG_ISA: return (u8 __iomem *)addr;
#endif
    default: return NULL; /* avoid warnings, just in case */
    }
}
static inline u16 __iomem *isa_mtw(unsigned long addr)
{
  switch(ISA_TYPE)
    {
#ifdef CONFIG_Q40
    case Q40_ISA: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_GG2
    case GG2_ISA: return (u16 __iomem *)GG2_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
    case AG_ISA: return (u16 __iomem *)addr;
#endif
    default: return NULL; /* avoid warnings, just in case */
    }
}


#define isa_inb(port)      in_8(isa_itb(port))
#define isa_inw(port)      (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
#define isa_inl(port)      (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
#define isa_outb(val,port) out_8(isa_itb(port),(val))
#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))

#define isa_readb(p)       in_8(isa_mtb((unsigned long)(p)))
#define isa_readw(p)       \
	(ISA_SEX ? in_be16(isa_mtw((unsigned long)(p)))	\
		 : in_le16(isa_mtw((unsigned long)(p))))
#define isa_writeb(val,p)  out_8(isa_mtb((unsigned long)(p)),(val))
#define isa_writew(val,p)  \
	(ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val))	\
		 : out_le16(isa_mtw((unsigned long)(p)),(val)))

static inline void isa_delay(void)
{
  switch(ISA_TYPE)
    {
#ifdef CONFIG_Q40
    case Q40_ISA: isa_outb(0,0x80); break;
#endif
#ifdef CONFIG_GG2
    case GG2_ISA: break;
#endif
#ifdef CONFIG_AMIGA_PCMCIA
    case AG_ISA: break;
#endif
    default: break; /* avoid warnings */
    }
}

#define isa_inb_p(p)      ({u8 v=isa_inb(p);isa_delay();v;})
#define isa_outb_p(v,p)   ({isa_outb((v),(p));isa_delay();})
#define isa_inw_p(p)      ({u16 v=isa_inw(p);isa_delay();v;})
#define isa_outw_p(v,p)   ({isa_outw((v),(p));isa_delay();})
#define isa_inl_p(p)      ({u32 v=isa_inl(p);isa_delay();v;})
#define isa_outl_p(v,p)   ({isa_outl((v),(p));isa_delay();})

#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))

#define isa_insw(port, buf, nr)     \
       (ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) :    \
                  raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))

#define isa_outsw(port, buf, nr)    \
       (ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) :  \
                  raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))

#define isa_insl(port, buf, nr)     \
       (ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) :    \
                  raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))

#define isa_outsl(port, buf, nr)    \
       (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) :  \
                  raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))

#endif  /* CONFIG_ISA */


#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
#define inb     isa_inb
#define inb_p   isa_inb_p
#define outb    isa_outb
#define outb_p  isa_outb_p
#define inw     isa_inw
#define inw_p   isa_inw_p
#define outw    isa_outw
#define outw_p  isa_outw_p
#define inl     isa_inl
#define inl_p   isa_inl_p
#define outl    isa_outl
#define outl_p  isa_outl_p
#define insb    isa_insb
#define insw    isa_insw
#define insl    isa_insl
#define outsb   isa_outsb
#define outsw   isa_outsw
#define outsl   isa_outsl
#define readb   isa_readb
#define readw   isa_readw
#define writeb  isa_writeb
#define writew  isa_writew
#endif /* CONFIG_ISA */

#if defined(CONFIG_PCI)

#define readl(addr)      in_le32(addr)
#define writel(val,addr) out_le32((addr),(val))

/* those can be defined for both ISA and PCI - it won't work though */
#define readb(addr)       in_8(addr)
#define readw(addr)       in_le16(addr)
#define writeb(val,addr)  out_8((addr),(val))
#define writew(val,addr)  out_le16((addr),(val))

#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)

#ifndef CONFIG_ISA
#define inb(port)      in_8(port)
#define outb(val,port) out_8((port),(val))
#define inw(port)      in_le16(port)
#define outw(val,port) out_le16((port),(val))
#define inl(port)      in_le32(port)
#define outl(val,port) out_le32((port),(val))

#else
/*
 * kernel with both ISA and PCI compiled in, those have
 * conflicting defs for in/out. Simply consider port < 1024
 * ISA and everything else PCI. read,write not defined
 * in this case
 */
#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
#define inw(port) ((port)<1024 ? isa_inw(port) : in_le16(port))
#define inw_p(port) ((port)<1024 ? isa_inw_p(port) : in_le16(port))
#define inl(port) ((port)<1024 ? isa_inl(port) : in_le32(port))
#define inl_p(port) ((port)<1024 ? isa_inl_p(port) : in_le32(port))

#define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
#define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
#define outw(val,port) ((port)<1024 ? isa_outw((val),(port)) : out_le16((port),(val)))
#define outw_p(val,port) ((port)<1024 ? isa_outw_p((val),(port)) : out_le16((port),(val)))
#define outl(val,port) ((port)<1024 ? isa_outl((val),(port)) : out_le32((port),(val)))
#define outl_p(val,port) ((port)<1024 ? isa_outl_p((val),(port)) : out_le32((port),(val)))
#endif
#endif /* CONFIG_PCI */

#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI)
/*
 * We need to define dummy functions for GENERIC_IOMAP support.
 */
#define inb(port)          0xff
#define inb_p(port)        0xff
#define outb(val,port)     ((void)0)
#define outb_p(val,port)   ((void)0)
#define inw(port)          0xffff
#define outw(val,port)     ((void)0)
#define inl(port)          0xffffffffUL
#define outl(val,port)     ((void)0)

#define insb(port,buf,nr)  ((void)0)
#define outsb(port,buf,nr) ((void)0)
#define insw(port,buf,nr)  ((void)0)
#define outsw(port,buf,nr) ((void)0)
#define insl(port,buf,nr)  ((void)0)
#define outsl(port,buf,nr) ((void)0)

/*
 * These should be valid on any ioremap()ed region
 */
#define readb(addr)      in_8(addr)
#define writeb(val,addr) out_8((addr),(val))
#define readw(addr)      in_le16(addr)
#define writew(val,addr) out_le16((addr),(val))
#endif
#if !defined(CONFIG_PCI)
#define readl(addr)      in_le32(addr)
#define writel(val,addr) out_le32((addr),(val))
#endif

#define mmiowb()

static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
					 unsigned long size)
{
	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
				      unsigned long size)
{
	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}

static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
	__builtin_memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
	__builtin_memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
	__builtin_memcpy((void __force *) dst, src, count);
}

#ifndef CONFIG_SUN3
#define IO_SPACE_LIMIT 0xffff
#else
#define IO_SPACE_LIMIT 0x0fffffff
#endif

#endif /* __KERNEL__ */

#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED		1

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#endif /* _IO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/include/asm-m68k/io.h
	3	*
	4	* 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
	5	* IO access
	6	* - added Q40 support
	7	* - added skeleton for GG-II and Amiga PCMCIA
	8	* 2/3/01 RZ: - moved a few more defs into raw_io.h
	9	*
	10	* inX/outX/readX/writeX should not be used by any driver unless it does
	11	* ISA or PCI access. Other drivers should use function defined in raw_io.h
	12	* or define its own macros on top of these.
	13	*
	14	* inX(),outX() are for PCI and ISA I/O
	15	* readX(),writeX() are for PCI memory
	16	* isa_readX(),isa_writeX() are for ISA memory
	17	*
	18	* moved mem{cpy,set}_*io inside CONFIG_PCI
	19	*/
	20
	21	#ifndef _IO_H
	22	#define _IO_H
	23
	24	#ifdef __KERNEL__
	25
ad9ec4f8	26	#include <linux/compiler.h>
1da177e4 LT	27	#include <asm/raw_io.h>
	28	#include <asm/virtconvert.h>
	29
f9569e1d	30	#include <asm-generic/iomap.h>
1da177e4 LT	31
	32	#ifdef CONFIG_ATARI
	33	#include <asm/atarihw.h>
	34	#endif
	35
	36
	37	/*
	38	* IO/MEM definitions for various ISA bridges
	39	*/
	40
	41
	42	#ifdef CONFIG_Q40
	43
	44	#define q40_isa_io_base 0xff400000
	45	#define q40_isa_mem_base 0xff800000
	46
	47	#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
	48	#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
	49	#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
	50	#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
	51
	52	#define MULTI_ISA 0
	53	#endif /* Q40 */
	54
	55	/* GG-II Zorro to ISA bridge */
	56	#ifdef CONFIG_GG2
	57
	58	extern unsigned long gg2_isa_base;
	59	#define GG2_ISA_IO_B(ioaddr) (gg2_isa_base+1+((unsigned long)(ioaddr)*4))
	60	#define GG2_ISA_IO_W(ioaddr) (gg2_isa_base+ ((unsigned long)(ioaddr)*4))
	61	#define GG2_ISA_MEM_B(madr) (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff))
	62	#define GG2_ISA_MEM_W(madr) (gg2_isa_base+ (((unsigned long)(madr)*4) & 0xfffff))
	63
	64	#ifndef MULTI_ISA
	65	#define MULTI_ISA 0
	66	#else
	67	#undef MULTI_ISA
	68	#define MULTI_ISA 1
	69	#endif
	70	#endif /* GG2 */
	71
	72	#ifdef CONFIG_AMIGA_PCMCIA
	73	#include <asm/amigayle.h>
	74
	75	#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
	76	#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
	77
	78	#ifndef MULTI_ISA
	79	#define MULTI_ISA 0
	80	#else
	81	#undef MULTI_ISA
	82	#define MULTI_ISA 1
	83	#endif
	84	#endif /* AMIGA_PCMCIA */
	85
	86
	87
	88	#ifdef CONFIG_ISA
	89
	90	#if MULTI_ISA == 0
	91	#undef MULTI_ISA
	92	#endif
	93
	94	#define Q40_ISA (1)
95	#define GG2_ISA (2)
96	#define AG_ISA (3)
97
98	#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
99	#define ISA_TYPE Q40_ISA
100	#define ISA_SEX 0
101	#endif
102	#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
103	#define ISA_TYPE AG_ISA
104	#define ISA_SEX 1
105	#endif
106	#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
107	#define ISA_TYPE GG2_ISA
108	#define ISA_SEX 0
109	#endif
110
111	#ifdef MULTI_ISA
112	extern int isa_type;
113	extern int isa_sex;
114
115	#define ISA_TYPE isa_type
116	#define ISA_SEX isa_sex
117	#endif
118
119	/*
120	* define inline addr translation functions. Normally only one variant will
121	* be compiled in so the case statement will be optimised away
122	*/
123
ad9ec4f8	124	static inline u8 __iomem *isa_itb(unsigned long addr)
1da177e4 LT	125	{
	126	switch(ISA_TYPE)
	127	{
	128	#ifdef CONFIG_Q40
ad9ec4f8	129	case Q40_ISA: return (u8 __iomem *)Q40_ISA_IO_B(addr);
1da177e4 LT	130	#endif
1da177e4 LT	131	#ifdef CONFIG_GG2
ad9ec4f8	132	case GG2_ISA: return (u8 __iomem *)GG2_ISA_IO_B(addr);
1da177e4 LT	133	#endif
1da177e4 LT	134	#ifdef CONFIG_AMIGA_PCMCIA
ad9ec4f8	135	case AG_ISA: return (u8 __iomem *)AG_ISA_IO_B(addr);
1da177e4	136	#endif
ad9ec4f8	137	default: return NULL; /* avoid warnings, just in case */
1da177e4 LT	138	}
1da177e4 LT	139	}
ad9ec4f8	140	static inline u16 __iomem *isa_itw(unsigned long addr)
1da177e4 LT	141	{
	142	switch(ISA_TYPE)
	143	{
	144	#ifdef CONFIG_Q40
ad9ec4f8	145	case Q40_ISA: return (u16 __iomem *)Q40_ISA_IO_W(addr);
1da177e4 LT	146	#endif
1da177e4 LT	147	#ifdef CONFIG_GG2
ad9ec4f8	148	case GG2_ISA: return (u16 __iomem *)GG2_ISA_IO_W(addr);
1da177e4 LT	149	#endif
1da177e4 LT	150	#ifdef CONFIG_AMIGA_PCMCIA
ad9ec4f8	151	case AG_ISA: return (u16 __iomem *)AG_ISA_IO_W(addr);
1da177e4	152	#endif
ad9ec4f8	153	default: return NULL; /* avoid warnings, just in case */
1da177e4 LT	154	}
1da177e4 LT	155	}
f9569e1d AV	156	static inline u32 __iomem *isa_itl(unsigned long addr)
	157	{
	158	switch(ISA_TYPE)
	159	{
	160	#ifdef CONFIG_AMIGA_PCMCIA
	161	case AG_ISA: return (u32 __iomem *)AG_ISA_IO_W(addr);
	162	#endif
	163	default: return 0; /* avoid warnings, just in case */
	164	}
	165	}
ad9ec4f8	166	static inline u8 __iomem *isa_mtb(unsigned long addr)
1da177e4 LT	167	{
	168	switch(ISA_TYPE)
	169	{
	170	#ifdef CONFIG_Q40
ad9ec4f8	171	case Q40_ISA: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
1da177e4 LT	172	#endif
1da177e4 LT	173	#ifdef CONFIG_GG2
ad9ec4f8	174	case GG2_ISA: return (u8 __iomem *)GG2_ISA_MEM_B(addr);
1da177e4 LT	175	#endif
1da177e4 LT	176	#ifdef CONFIG_AMIGA_PCMCIA
ad9ec4f8	177	case AG_ISA: return (u8 __iomem *)addr;
1da177e4	178	#endif
ad9ec4f8	179	default: return NULL; /* avoid warnings, just in case */
1da177e4 LT	180	}
1da177e4 LT	181	}
ad9ec4f8	182	static inline u16 __iomem *isa_mtw(unsigned long addr)
1da177e4 LT	183	{
	184	switch(ISA_TYPE)
	185	{
	186	#ifdef CONFIG_Q40
ad9ec4f8	187	case Q40_ISA: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
1da177e4 LT	188	#endif
1da177e4 LT	189	#ifdef CONFIG_GG2
ad9ec4f8	190	case GG2_ISA: return (u16 __iomem *)GG2_ISA_MEM_W(addr);
1da177e4 LT	191	#endif
1da177e4 LT	192	#ifdef CONFIG_AMIGA_PCMCIA
ad9ec4f8	193	case AG_ISA: return (u16 __iomem *)addr;
1da177e4	194	#endif
ad9ec4f8	195	default: return NULL; /* avoid warnings, just in case */
1da177e4 LT	196	}
	197	}
	198
	199
	200	#define isa_inb(port) in_8(isa_itb(port))
	201	#define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
f9569e1d	202	#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
1da177e4 LT	203	#define isa_outb(val,port) out_8(isa_itb(port),(val))
1da177e4 LT	204	#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
f9569e1d	205	#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
1da177e4 LT	206
	207	#define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
	208	#define isa_readw(p) \
	209	(ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
	210	: in_le16(isa_mtw((unsigned long)(p))))
	211	#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
	212	#define isa_writew(val,p) \
	213	(ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
	214	: out_le16(isa_mtw((unsigned long)(p)),(val)))
	215
	216	static inline void isa_delay(void)
	217	{
	218	switch(ISA_TYPE)
	219	{
	220	#ifdef CONFIG_Q40
	221	case Q40_ISA: isa_outb(0,0x80); break;
	222	#endif
	223	#ifdef CONFIG_GG2
	224	case GG2_ISA: break;
	225	#endif
	226	#ifdef CONFIG_AMIGA_PCMCIA
	227	case AG_ISA: break;
	228	#endif
	229	default: break; /* avoid warnings */
	230	}
	231	}
	232
	233	#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
	234	#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
	235	#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
	236	#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
	237	#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
	238	#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
	239
	240	#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
	241	#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))
	242
	243	#define isa_insw(port, buf, nr) \
	244	(ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
	245	raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
	246
	247	#define isa_outsw(port, buf, nr) \
	248	(ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
	249	raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
f9569e1d AV	250
	251	#define isa_insl(port, buf, nr) \
	252	(ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \
	253	raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
	254
	255	#define isa_outsl(port, buf, nr) \
	256	(ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
	257	raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
	258
1da177e4 LT	259	#endif /* CONFIG_ISA */
	260
	261
	262	#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
	263	#define inb isa_inb
	264	#define inb_p isa_inb_p
	265	#define outb isa_outb
	266	#define outb_p isa_outb_p
	267	#define inw isa_inw
	268	#define inw_p isa_inw_p
	269	#define outw isa_outw
	270	#define outw_p isa_outw_p
f9569e1d AV	271	#define inl isa_inl
	272	#define inl_p isa_inl_p
	273	#define outl isa_outl
	274	#define outl_p isa_outl_p
1da177e4 LT	275	#define insb isa_insb
1da177e4 LT	276	#define insw isa_insw
f9569e1d	277	#define insl isa_insl
1da177e4 LT	278	#define outsb isa_outsb
1da177e4 LT	279	#define outsw isa_outsw
f9569e1d	280	#define outsl isa_outsl
1da177e4 LT	281	#define readb isa_readb
	282	#define readw isa_readw
	283	#define writeb isa_writeb
	284	#define writew isa_writew
	285	#endif /* CONFIG_ISA */
	286
	287	#if defined(CONFIG_PCI)
	288
1da177e4 LT	289	#define readl(addr) in_le32(addr)
	290	#define writel(val,addr) out_le32((addr),(val))
	291
	292	/* those can be defined for both ISA and PCI - it won't work though */
	293	#define readb(addr) in_8(addr)
	294	#define readw(addr) in_le16(addr)
	295	#define writeb(val,addr) out_8((addr),(val))
	296	#define writew(val,addr) out_le16((addr),(val))
	297
	298	#define readb_relaxed(addr) readb(addr)
	299	#define readw_relaxed(addr) readw(addr)
	300	#define readl_relaxed(addr) readl(addr)
	301
	302	#ifndef CONFIG_ISA
	303	#define inb(port) in_8(port)
	304	#define outb(val,port) out_8((port),(val))
	305	#define inw(port) in_le16(port)
	306	#define outw(val,port) out_le16((port),(val))
f9569e1d AV	307	#define inl(port) in_le32(port)
f9569e1d AV	308	#define outl(val,port) out_le32((port),(val))
1da177e4 LT	309
	310	#else
	311	/*
	312	* kernel with both ISA and PCI compiled in, those have
	313	* conflicting defs for in/out. Simply consider port < 1024
	314	* ISA and everything else PCI. read,write not defined
	315	* in this case
	316	*/
	317	#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
	318	#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
	319	#define inw(port) ((port)<1024 ? isa_inw(port) : in_le16(port))
	320	#define inw_p(port) ((port)<1024 ? isa_inw_p(port) : in_le16(port))
	321	#define inl(port) ((port)<1024 ? isa_inl(port) : in_le32(port))
	322	#define inl_p(port) ((port)<1024 ? isa_inl_p(port) : in_le32(port))
	323
	324	#define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
	325	#define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
	326	#define outw(val,port) ((port)<1024 ? isa_outw((val),(port)) : out_le16((port),(val)))
	327	#define outw_p(val,port) ((port)<1024 ? isa_outw_p((val),(port)) : out_le16((port),(val)))
	328	#define outl(val,port) ((port)<1024 ? isa_outl((val),(port)) : out_le32((port),(val)))
	329	#define outl_p(val,port) ((port)<1024 ? isa_outl_p((val),(port)) : out_le32((port),(val)))
	330	#endif
	331	#endif /* CONFIG_PCI */
	332
f9569e1d	333	#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI)
1da177e4	334	/*
f9569e1d	335	* We need to define dummy functions for GENERIC_IOMAP support.
1da177e4	336	*/
f9569e1d AV	337	#define inb(port) 0xff
	338	#define inb_p(port) 0xff
	339	#define outb(val,port) ((void)0)
	340	#define outb_p(val,port) ((void)0)
	341	#define inw(port) 0xffff
	342	#define outw(val,port) ((void)0)
	343	#define inl(port) 0xffffffffUL
	344	#define outl(val,port) ((void)0)
	345
	346	#define insb(port,buf,nr) ((void)0)
	347	#define outsb(port,buf,nr) ((void)0)
	348	#define insw(port,buf,nr) ((void)0)
	349	#define outsw(port,buf,nr) ((void)0)
	350	#define insl(port,buf,nr) ((void)0)
	351	#define outsl(port,buf,nr) ((void)0)
1da177e4 LT	352
	353	/*
	354	* These should be valid on any ioremap()ed region
	355	*/
	356	#define readb(addr) in_8(addr)
	357	#define writeb(val,addr) out_8((addr),(val))
f9569e1d AV	358	#define readw(addr) in_le16(addr)
	359	#define writew(val,addr) out_le16((addr),(val))
	360	#endif
	361	#if !defined(CONFIG_PCI)
1da177e4 LT	362	#define readl(addr) in_le32(addr)
	363	#define writel(val,addr) out_le32((addr),(val))
	364	#endif
	365
	366	#define mmiowb()
	367
ad9ec4f8	368	static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
1da177e4 LT	369	{
	370	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
	371	}
ad9ec4f8	372	static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
1da177e4 LT	373	{
	374	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
	375	}
ad9ec4f8	376	static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
1da177e4 LT	377	unsigned long size)
	378	{
	379	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
	380	}
ad9ec4f8	381	static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
1da177e4 LT	382	unsigned long size)
	383	{
	384	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
	385	}
	386
f9569e1d AV	387	static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
	388	{
	389	__builtin_memset((void __force *) addr, val, count);
	390	}
	391	static inline void memcpy_fromio(void dst, const volatile void __iomem src, int count)
	392	{
	393	__builtin_memcpy(dst, (void __force *) src, count);
	394	}
	395	static inline void memcpy_toio(volatile void __iomem dst, const void src, int count)
	396	{
	397	__builtin_memcpy((void __force *) dst, src, count);
	398	}
1da177e4 LT	399
	400	#ifndef CONFIG_SUN3
	401	#define IO_SPACE_LIMIT 0xffff
	402	#else
	403	#define IO_SPACE_LIMIT 0x0fffffff
	404	#endif
	405
	406	#endif /* __KERNEL__ */
	407
	408	#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
	409
	410	/*
	411	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	412	* access
	413	*/
	414	#define xlate_dev_mem_ptr(p) __va(p)
	415
	416	/*
	417	* Convert a virtual cached pointer to an uncached pointer
	418	*/
	419	#define xlate_dev_kmem_ptr(p) p
	420
	421	#endif /* _IO_H */