projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 2003 Ralf Baechle | |
| 7 | */ | |
| 8 | #ifndef _ASM_ASMMACRO_H | |
| 9 | #define _ASM_ASMMACRO_H | |
| 42a3b4f2 | 10 | |
| 1da177e4 | 11 | #include <asm/hazards.h> |
| 42a3b4f2 | 12 | |
| 875d43e7 | 13 | #ifdef CONFIG_32BIT |
| 1da177e4 LT |
14 | #include <asm/asmmacro-32.h> |
| 15 | #endif | |
| 875d43e7 | 16 | #ifdef CONFIG_64BIT |
| 1da177e4 LT |
17 | #include <asm/asmmacro-64.h> |
| 18 | #endif | |
| 41c594ab RB |
19 | #ifdef CONFIG_MIPS_MT_SMTC |
| 20 | #include <asm/mipsmtregs.h> | |
| 21 | #endif | |
| 1da177e4 | 22 | |
| 41c594ab RB |
23 | #ifdef CONFIG_MIPS_MT_SMTC |
| 24 | .macro local_irq_enable reg=t0 | |
| 25 | mfc0 \reg, CP0_TCSTATUS | |
| 26 | ori \reg, \reg, TCSTATUS_IXMT | |
| 27 | xori \reg, \reg, TCSTATUS_IXMT | |
| 28 | mtc0 \reg, CP0_TCSTATUS | |
| 4277ff5e | 29 | _ehb |
| 41c594ab RB |
30 | .endm |
| 31 | ||
| 32 | .macro local_irq_disable reg=t0 | |
| 33 | mfc0 \reg, CP0_TCSTATUS | |
| 34 | ori \reg, \reg, TCSTATUS_IXMT | |
| 35 | mtc0 \reg, CP0_TCSTATUS | |
| 4277ff5e | 36 | _ehb |
| 41c594ab RB |
37 | .endm |
| 38 | #else | |
| 1da177e4 LT |
39 | .macro local_irq_enable reg=t0 |
| 40 | mfc0 \reg, CP0_STATUS | |
| 41 | ori \reg, \reg, 1 | |
| 42 | mtc0 \reg, CP0_STATUS | |
| 43 | irq_enable_hazard | |
| 44 | .endm | |
| 45 | ||
| 46 | .macro local_irq_disable reg=t0 | |
| 47 | mfc0 \reg, CP0_STATUS | |
| 48 | ori \reg, \reg, 1 | |
| 49 | xori \reg, \reg, 1 | |
| 50 | mtc0 \reg, CP0_STATUS | |
| 51 | irq_disable_hazard | |
| 52 | .endm | |
| 41c594ab | 53 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 1da177e4 LT |
54 | |
| 55 | #ifdef CONFIG_CPU_SB1 | |
| 56 | .macro fpu_enable_hazard | |
| 57 | .set push | |
| 58 | .set noreorder | |
| 59 | .set mips2 | |
| 60 | SSNOP | |
| 61 | bnezl $0, .+4 | |
| 62 | SSNOP | |
| 63 | .set pop | |
| 64 | .endm | |
| 65 | #else | |
| 66 | .macro fpu_enable_hazard | |
| 67 | .endm | |
| 68 | #endif | |
| 69 | ||
| 41c594ab RB |
70 | /* |
| 71 | * Temporary until all gas have MT ASE support | |
| 72 | */ | |
| 73 | .macro DMT reg=0 | |
| 74 | .word (0x41600bc1 | (\reg << 16)) | |
| 75 | .endm | |
| 76 | ||
| 77 | .macro EMT reg=0 | |
| 78 | .word (0x41600be1 | (\reg << 16)) | |
| 79 | .endm | |
| 80 | ||
| 81 | .macro DVPE reg=0 | |
| 82 | .word (0x41600001 | (\reg << 16)) | |
| 83 | .endm | |
| 84 | ||
| 85 | .macro EVPE reg=0 | |
| 86 | .word (0x41600021 | (\reg << 16)) | |
| 87 | .endm | |
| 88 | ||
| 89 | .macro MFTR rt=0, rd=0, u=0, sel=0 | |
| 90 | .word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) | |
| 91 | .endm | |
| 92 | ||
| 93 | .macro MTTR rt=0, rd=0, u=0, sel=0 | |
| 94 | .word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)) | |
| 95 | .endm | |
| 96 | ||
| 1da177e4 | 97 | #endif /* _ASM_ASMMACRO_H */ |