projects / mirror_ubuntu-artful-kernel.git / blame
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|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 2003, 2004 Ralf Baechle | |
| 4194318c | 7 | * Copyright (C) 2004 Maciej W. Rozycki |
| 1da177e4 LT |
8 | */ |
| 9 | #ifndef __ASM_CPU_FEATURES_H | |
| 10 | #define __ASM_CPU_FEATURES_H | |
| 11 | ||
| 12 | #include <linux/config.h> | |
| 13 | ||
| 14 | #include <asm/cpu.h> | |
| 15 | #include <asm/cpu-info.h> | |
| 16 | #include <cpu-feature-overrides.h> | |
| 17 | ||
| 18 | /* | |
| 19 | * SMP assumption: Options of CPU 0 are a superset of all processors. | |
| 20 | * This is true for all known MIPS systems. | |
| 21 | */ | |
| 22 | #ifndef cpu_has_tlb | |
| 23 | #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) | |
| 24 | #endif | |
| 25 | #ifndef cpu_has_4kex | |
| 26 | #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) | |
| 27 | #endif | |
| 28 | #ifndef cpu_has_4ktlb | |
| 29 | #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) | |
| 30 | #endif | |
| 31 | #ifndef cpu_has_fpu | |
| 32 | #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) | |
| 33 | #endif | |
| 34 | #ifndef cpu_has_32fpr | |
| 35 | #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) | |
| 36 | #endif | |
| 37 | #ifndef cpu_has_counter | |
| 38 | #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) | |
| 39 | #endif | |
| 40 | #ifndef cpu_has_watch | |
| 41 | #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) | |
| 42 | #endif | |
| 1da177e4 LT |
43 | #ifndef cpu_has_divec |
| 44 | #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) | |
| 45 | #endif | |
| 46 | #ifndef cpu_has_vce | |
| 47 | #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) | |
| 48 | #endif | |
| 49 | #ifndef cpu_has_cache_cdex_p | |
| 50 | #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) | |
| 51 | #endif | |
| 52 | #ifndef cpu_has_cache_cdex_s | |
| 53 | #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) | |
| 54 | #endif | |
| 55 | #ifndef cpu_has_prefetch | |
| 56 | #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) | |
| 57 | #endif | |
| 58 | #ifndef cpu_has_mcheck | |
| 59 | #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) | |
| 60 | #endif | |
| 61 | #ifndef cpu_has_ejtag | |
| 62 | #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) | |
| 63 | #endif | |
| 64 | #ifndef cpu_has_llsc | |
| 65 | #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) | |
| 66 | #endif | |
| 4194318c RB |
67 | #ifndef cpu_has_mips16 |
| 68 | #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) | |
| 69 | #endif | |
| 70 | #ifndef cpu_has_mdmx | |
| 71 | #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) | |
| 72 | #endif | |
| 73 | #ifndef cpu_has_mips3d | |
| 74 | #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) | |
| 75 | #endif | |
| 76 | #ifndef cpu_has_smartmips | |
| 77 | #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) | |
| 78 | #endif | |
| 1da177e4 LT |
79 | #ifndef cpu_has_vtag_icache |
| 80 | #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) | |
| 81 | #endif | |
| 82 | #ifndef cpu_has_dc_aliases | |
| 83 | #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) | |
| 84 | #endif | |
| 85 | #ifndef cpu_has_ic_fills_f_dc | |
| 86 | #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) | |
| 87 | #endif | |
| 88 | ||
| 89 | /* | |
| 90 | * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors | |
| 91 | * such as the R10000 have I-Caches that snoop local stores; the embedded ones | |
| 92 | * don't. For maintaining I-cache coherency this means we need to flush the | |
| 93 | * D-cache all the way back to whever the I-cache does refills from, so the | |
| 94 | * I-cache has a chance to see the new data at all. Then we have to flush the | |
| 95 | * I-cache also. | |
| 96 | * Note we may have been rescheduled and may no longer be running on the CPU | |
| 97 | * that did the store so we can't optimize this into only doing the flush on | |
| 98 | * the local CPU. | |
| 99 | */ | |
| 100 | #ifndef cpu_icache_snoops_remote_store | |
| 101 | #ifdef CONFIG_SMP | |
| 102 | #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) | |
| 103 | #else | |
| 104 | #define cpu_icache_snoops_remote_store 1 | |
| 105 | #endif | |
| 106 | #endif | |
| 107 | ||
| 108 | /* | |
| 109 | * Certain CPUs may throw bizarre exceptions if not the whole cacheline | |
| 110 | * contains valid instructions. For these we ensure proper alignment of | |
| 111 | * signal trampolines and pad them to the size of a full cache lines with | |
| 112 | * nops. This is also used in structure definitions so can't be a test macro | |
| 113 | * like the others. | |
| 114 | */ | |
| 115 | #ifndef PLAT_TRAMPOLINE_STUFF_LINE | |
| 116 | #define PLAT_TRAMPOLINE_STUFF_LINE 0UL | |
| 117 | #endif | |
| 118 | ||
| 875d43e7 | 119 | #ifdef CONFIG_32BIT |
| 1da177e4 LT |
120 | # ifndef cpu_has_nofpuex |
| 121 | # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) | |
| 122 | # endif | |
| 123 | # ifndef cpu_has_64bits | |
| 124 | # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) | |
| 125 | # endif | |
| 126 | # ifndef cpu_has_64bit_zero_reg | |
| 127 | # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) | |
| 128 | # endif | |
| 129 | # ifndef cpu_has_64bit_gp_regs | |
| 130 | # define cpu_has_64bit_gp_regs 0 | |
| 131 | # endif | |
| 132 | # ifndef cpu_has_64bit_addresses | |
| 133 | # define cpu_has_64bit_addresses 0 | |
| 134 | # endif | |
| 135 | #endif | |
| 136 | ||
| 875d43e7 | 137 | #ifdef CONFIG_64BIT |
| 1da177e4 LT |
138 | # ifndef cpu_has_nofpuex |
| 139 | # define cpu_has_nofpuex 0 | |
| 140 | # endif | |
| 141 | # ifndef cpu_has_64bits | |
| 142 | # define cpu_has_64bits 1 | |
| 143 | # endif | |
| 144 | # ifndef cpu_has_64bit_zero_reg | |
| 145 | # define cpu_has_64bit_zero_reg 1 | |
| 146 | # endif | |
| 147 | # ifndef cpu_has_64bit_gp_regs | |
| 148 | # define cpu_has_64bit_gp_regs 1 | |
| 149 | # endif | |
| 150 | # ifndef cpu_has_64bit_addresses | |
| 151 | # define cpu_has_64bit_addresses 1 | |
| 152 | # endif | |
| 153 | #endif | |
| 154 | ||
| 155 | #ifndef cpu_has_subset_pcaches | |
| 156 | #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) | |
| 157 | #endif | |
| 158 | ||
| 159 | #ifndef cpu_dcache_line_size | |
| 160 | #define cpu_dcache_line_size() current_cpu_data.dcache.linesz | |
| 161 | #endif | |
| 162 | #ifndef cpu_icache_line_size | |
| 163 | #define cpu_icache_line_size() current_cpu_data.icache.linesz | |
| 164 | #endif | |
| 165 | #ifndef cpu_scache_line_size | |
| 166 | #define cpu_scache_line_size() current_cpu_data.scache.linesz | |
| 167 | #endif | |
| 168 | ||
| 169 | #endif /* __ASM_CPU_FEATURES_H */ |