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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 Waldorf GMBH | |
7 | * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle | |
8 | * Copyright (C) 1996 Paul M. Antoine | |
9 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
4194318c | 10 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 LT |
11 | */ |
12 | #ifndef __ASM_CPU_INFO_H | |
13 | #define __ASM_CPU_INFO_H | |
14 | ||
1da177e4 LT |
15 | #include <asm/cache.h> |
16 | ||
1da177e4 LT |
17 | /* |
18 | * Descriptor for a cache | |
19 | */ | |
20 | struct cache_desc { | |
1da177e4 | 21 | unsigned int waysize; /* Bytes per way */ |
6f2c3fa0 RB |
22 | unsigned short sets; /* Number of lines per set */ |
23 | unsigned char ways; /* Number of ways */ | |
24 | unsigned char linesz; /* Size of line in bytes */ | |
25 | unsigned char waybit; /* Bits to select in a cache set */ | |
26 | unsigned char flags; /* Flags describing cache properties */ | |
1da177e4 LT |
27 | }; |
28 | ||
29 | /* | |
30 | * Flag definitions | |
31 | */ | |
32 | #define MIPS_CACHE_NOT_PRESENT 0x00000001 | |
33 | #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ | |
34 | #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ | |
35 | #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ | |
36 | #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ | |
de62893b | 37 | #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ |
1da177e4 LT |
38 | |
39 | struct cpuinfo_mips { | |
40 | unsigned long udelay_val; | |
41 | unsigned long asid_cache; | |
1da177e4 LT |
42 | |
43 | /* | |
44 | * Capability and feature descriptor structure for MIPS CPU | |
45 | */ | |
46 | unsigned long options; | |
4194318c | 47 | unsigned long ases; |
1da177e4 LT |
48 | unsigned int processor_id; |
49 | unsigned int fpu_id; | |
50 | unsigned int cputype; | |
51 | int isa_level; | |
52 | int tlbsize; | |
53 | struct cache_desc icache; /* Primary I-cache */ | |
54 | struct cache_desc dcache; /* Primary D or combined I/D cache */ | |
55 | struct cache_desc scache; /* Secondary cache */ | |
56 | struct cache_desc tcache; /* Tertiary/split secondary cache */ | |
41c594ab RB |
57 | #if defined(CONFIG_MIPS_MT_SMTC) |
58 | /* | |
59 | * In the MIPS MT "SMTC" model, each TC is considered | |
60 | * to be a "CPU" for the purposes of scheduling, but | |
61 | * exception resources, ASID spaces, etc, are common | |
62 | * to all TCs within the same VPE. | |
63 | */ | |
64 | int vpe_id; /* Virtual Processor number */ | |
65 | int tc_id; /* Thread Context number */ | |
66 | #endif /* CONFIG_MIPS_MT */ | |
1da177e4 LT |
67 | void *data; /* Additional data */ |
68 | } __attribute__((aligned(SMP_CACHE_BYTES))); | |
69 | ||
70 | extern struct cpuinfo_mips cpu_data[]; | |
71 | #define current_cpu_data cpu_data[smp_processor_id()] | |
53dc8028 | 72 | #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] |
1da177e4 LT |
73 | |
74 | extern void cpu_probe(void); | |
75 | extern void cpu_report(void); | |
76 | ||
9966db25 RB |
77 | extern const char *__cpu_name[]; |
78 | #define cpu_name_string() __cpu_name[smp_processor_id()] | |
79 | ||
1da177e4 | 80 | #endif /* __ASM_CPU_INFO_H */ |