[mirror_ubuntu-bionic-kernel.git] / include / asm-mips / irqflags.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Copyright (C) 2000 MIPS Technologies, Inc.
 */
#ifndef _ASM_IRQFLAGS_H
#define _ASM_IRQFLAGS_H

#ifndef __ASSEMBLY__

#include <linux/compiler.h>
#include <asm/hazards.h>

__asm__ (
	"	.macro	raw_local_irq_enable				\n"
	"	.set	push						\n"
	"	.set	reorder						\n"
	"	.set	noat						\n"
#ifdef CONFIG_MIPS_MT_SMTC
	"	mfc0	$1, $2, 1	# SMTC - clear TCStatus.IXMT	\n"
	"	ori	$1, 0x400					\n"
	"	xori	$1, 0x400					\n"
	"	mtc0	$1, $2, 1					\n"
#elif defined(CONFIG_CPU_MIPSR2)
	"	ei							\n"
#else
	"	mfc0	$1,$12						\n"
	"	ori	$1,0x1f						\n"
	"	xori	$1,0x1e						\n"
	"	mtc0	$1,$12						\n"
#endif
	"	irq_enable_hazard					\n"
	"	.set	pop						\n"
	"	.endm");

static inline void raw_local_irq_enable(void)
{
	__asm__ __volatile__(
		"raw_local_irq_enable"
		: /* no outputs */
		: /* no inputs */
		: "memory");
}

/*
 * For cli() we have to insert nops to make sure that the new value
 * has actually arrived in the status register before the end of this
 * macro.
 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
 * no nops at all.
 */
/*
 * For TX49, operating only IE bit is not enough.
 *
 * If mfc0 $12 follows store and the mfc0 is last instruction of a
 * page and fetching the next instruction causes TLB miss, the result
 * of the mfc0 might wrongly contain EXL bit.
 *
 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
 *
 * Workaround: mask EXL bit of the result or place a nop before mfc0.
 */
__asm__ (
	"	.macro	raw_local_irq_disable\n"
	"	.set	push						\n"
	"	.set	noat						\n"
#ifdef CONFIG_MIPS_MT_SMTC
	"	mfc0	$1, $2, 1					\n"
	"	ori	$1, 0x400					\n"
	"	.set	noreorder					\n"
	"	mtc0	$1, $2, 1					\n"
#elif defined(CONFIG_CPU_MIPSR2)
	"	di							\n"
#else
	"	mfc0	$1,$12						\n"
	"	ori	$1,0x1f						\n"
	"	xori	$1,0x1f						\n"
	"	.set	noreorder					\n"
	"	mtc0	$1,$12						\n"
#endif
	"	irq_disable_hazard					\n"
	"	.set	pop						\n"
	"	.endm							\n");

static inline void raw_local_irq_disable(void)
{
	__asm__ __volatile__(
		"raw_local_irq_disable"
		: /* no outputs */
		: /* no inputs */
		: "memory");
}

__asm__ (
	"	.macro	raw_local_save_flags flags			\n"
	"	.set	push						\n"
	"	.set	reorder						\n"
#ifdef CONFIG_MIPS_MT_SMTC
	"	mfc0	\\flags, $2, 1					\n"
#else
	"	mfc0	\\flags, $12					\n"
#endif
	"	.set	pop						\n"
	"	.endm							\n");

#define raw_local_save_flags(x)						\
__asm__ __volatile__(							\
	"raw_local_save_flags %0"					\
	: "=r" (x))

__asm__ (
	"	.macro	raw_local_irq_save result			\n"
	"	.set	push						\n"
	"	.set	reorder						\n"
	"	.set	noat						\n"
#ifdef CONFIG_MIPS_MT_SMTC
	"	mfc0	\\result, $2, 1					\n"
	"	ori	$1, \\result, 0x400				\n"
	"	.set	noreorder					\n"
	"	mtc0	$1, $2, 1					\n"
	"	andi	\\result, \\result, 0x400			\n"
#elif defined(CONFIG_CPU_MIPSR2)
	"	di	\\result					\n"
	"	andi	\\result, 1					\n"
#else
	"	mfc0	\\result, $12					\n"
	"	ori	$1, \\result, 0x1f				\n"
	"	xori	$1, 0x1f					\n"
	"	.set	noreorder					\n"
	"	mtc0	$1, $12						\n"
#endif
	"	irq_disable_hazard					\n"
	"	.set	pop						\n"
	"	.endm							\n");

#define raw_local_irq_save(x)						\
__asm__ __volatile__(							\
	"raw_local_irq_save\t%0"					\
	: "=r" (x)							\
	: /* no inputs */						\
	: "memory")

__asm__ (
	"	.macro	raw_local_irq_restore flags			\n"
	"	.set	push						\n"
	"	.set	noreorder					\n"
	"	.set	noat						\n"
#ifdef CONFIG_MIPS_MT_SMTC
	"mfc0	$1, $2, 1						\n"
	"andi	\\flags, 0x400						\n"
	"ori	$1, 0x400						\n"
	"xori	$1, 0x400						\n"
	"or	\\flags, $1						\n"
	"mtc0	\\flags, $2, 1						\n"
#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
	/*
	 * Slow, but doesn't suffer from a relativly unlikely race
	 * condition we're having since days 1.
	 */
	"	beqz	\\flags, 1f					\n"
	"	 di							\n"
	"	ei							\n"
	"1:								\n"
#elif defined(CONFIG_CPU_MIPSR2)
	/*
	 * Fast, dangerous.  Life is fun, life is good.
	 */
	"	mfc0	$1, $12						\n"
	"	ins	$1, \\flags, 0, 1				\n"
	"	mtc0	$1, $12						\n"
#else
	"	mfc0	$1, $12						\n"
	"	andi	\\flags, 1					\n"
	"	ori	$1, 0x1f					\n"
	"	xori	$1, 0x1f					\n"
	"	or	\\flags, $1					\n"
	"	mtc0	\\flags, $12					\n"
#endif
	"	irq_disable_hazard					\n"
	"	.set	pop						\n"
	"	.endm							\n");

extern void smtc_ipi_replay(void);

static inline void raw_local_irq_restore(unsigned long flags)
{
	unsigned long __tmp1;

#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
	/*
	 * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
	 * IPIs, at the cost of branch and call overhead on each
	 * local_irq_restore()
	 */
	if (unlikely(!(flags & 0x0400)))
		smtc_ipi_replay();
#endif

	__asm__ __volatile__(
		"raw_local_irq_restore\t%0"
		: "=r" (__tmp1)
		: "0" (flags)
		: "memory");
}

static inline int raw_irqs_disabled_flags(unsigned long flags)
{
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
	 */
	return flags & 0x400;
#else
	return !(flags & 1);
#endif
}

#endif

/*
 * Do the CPU's IRQ-state tracing from assembly code.
 */
#ifdef CONFIG_TRACE_IRQFLAGS
/* Reload some registers clobbered by trace_hardirqs_on */
#ifdef CONFIG_64BIT
# define TRACE_IRQS_RELOAD_REGS						\
	LONG_L	$11, PT_R11(sp);					\
	LONG_L	$10, PT_R10(sp);					\
	LONG_L	$9, PT_R9(sp);						\
	LONG_L	$8, PT_R8(sp);						\
	LONG_L	$7, PT_R7(sp);						\
	LONG_L	$6, PT_R6(sp);						\
	LONG_L	$5, PT_R5(sp);						\
	LONG_L	$4, PT_R4(sp);						\
	LONG_L	$2, PT_R2(sp)
#else
# define TRACE_IRQS_RELOAD_REGS						\
	LONG_L	$7, PT_R7(sp);						\
	LONG_L	$6, PT_R6(sp);						\
	LONG_L	$5, PT_R5(sp);						\
	LONG_L	$4, PT_R4(sp);						\
	LONG_L	$2, PT_R2(sp)
#endif
# define TRACE_IRQS_ON							\
	CLI;	/* make sure trace_hardirqs_on() is called in kernel level */ \
	jal	trace_hardirqs_on
# define TRACE_IRQS_ON_RELOAD						\
	TRACE_IRQS_ON;							\
	TRACE_IRQS_RELOAD_REGS
# define TRACE_IRQS_OFF							\
	jal	trace_hardirqs_off
#else
# define TRACE_IRQS_ON
# define TRACE_IRQS_ON_RELOAD
# define TRACE_IRQS_OFF
#endif

#endif /* _ASM_IRQFLAGS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
	7	* Copyright (C) 1996 by Paul M. Antoine
	8	* Copyright (C) 1999 Silicon Graphics
	9	* Copyright (C) 2000 MIPS Technologies, Inc.
	10	*/
192ef366 RB	11	#ifndef _ASM_IRQFLAGS_H
	12	#define _ASM_IRQFLAGS_H
	13
	14	#ifndef __ASSEMBLY__
1da177e4	15
8a1e97ee	16	#include <linux/compiler.h>
1da177e4 LT	17	#include <asm/hazards.h>
	18
	19	__asm__ (
192ef366	20	" .macro raw_local_irq_enable \n"
ff88f8a3 RB	21	" .set push \n"
	22	" .set reorder \n"
	23	" .set noat \n"
41c594ab RB	24	#ifdef CONFIG_MIPS_MT_SMTC
	25	" mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
	26	" ori $1, 0x400 \n"
	27	" xori $1, 0x400 \n"
	28	" mtc0 $1, $2, 1 \n"
	29	#elif defined(CONFIG_CPU_MIPSR2)
ff88f8a3 RB	30	" ei \n"
	31	#else
	32	" mfc0 $1,$12 \n"
	33	" ori $1,0x1f \n"
	34	" xori $1,0x1e \n"
	35	" mtc0 $1,$12 \n"
	36	#endif
	37	" irq_enable_hazard \n"
	38	" .set pop \n"
	39	" .endm");
1da177e4	40
192ef366	41	static inline void raw_local_irq_enable(void)
1da177e4 LT	42	{
1da177e4 LT	43	__asm__ __volatile__(
192ef366	44	"raw_local_irq_enable"
1da177e4 LT	45	: /* no outputs */
	46	: /* no inputs */
	47	: "memory");
	48	}
	49
	50	/*
	51	* For cli() we have to insert nops to make sure that the new value
	52	* has actually arrived in the status register before the end of this
	53	* macro.
	54	* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
	55	* no nops at all.
	56	*/
c226f260 AN	57	/*
	58	* For TX49, operating only IE bit is not enough.
	59	*
	60	* If mfc0 $12 follows store and the mfc0 is last instruction of a
	61	* page and fetching the next instruction causes TLB miss, the result
	62	* of the mfc0 might wrongly contain EXL bit.
	63	*
	64	* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
	65	*
	66	* Workaround: mask EXL bit of the result or place a nop before mfc0.
	67	*/
1da177e4	68	__asm__ (
192ef366	69	" .macro raw_local_irq_disable\n"
ff88f8a3 RB	70	" .set push \n"
ff88f8a3 RB	71	" .set noat \n"
41c594ab RB	72	#ifdef CONFIG_MIPS_MT_SMTC
	73	" mfc0 $1, $2, 1 \n"
	74	" ori $1, 0x400 \n"
	75	" .set noreorder \n"
	76	" mtc0 $1, $2, 1 \n"
	77	#elif defined(CONFIG_CPU_MIPSR2)
ff88f8a3 RB	78	" di \n"
	79	#else
	80	" mfc0 $1,$12 \n"
c226f260 AN	81	" ori $1,0x1f \n"
c226f260 AN	82	" xori $1,0x1f \n"
ff88f8a3 RB	83	" .set noreorder \n"
	84	" mtc0 $1,$12 \n"
	85	#endif
	86	" irq_disable_hazard \n"
	87	" .set pop \n"
	88	" .endm \n");
1da177e4	89
192ef366	90	static inline void raw_local_irq_disable(void)
1da177e4 LT	91	{
1da177e4 LT	92	__asm__ __volatile__(
192ef366	93	"raw_local_irq_disable"
1da177e4 LT	94	: /* no outputs */
	95	: /* no inputs */
	96	: "memory");
	97	}
	98
	99	__asm__ (
192ef366	100	" .macro raw_local_save_flags flags \n"
ff88f8a3 RB	101	" .set push \n"
ff88f8a3 RB	102	" .set reorder \n"
41c594ab RB	103	#ifdef CONFIG_MIPS_MT_SMTC
	104	" mfc0 \\flags, $2, 1 \n"
	105	#else
ff88f8a3	106	" mfc0 \\flags, $12 \n"
41c594ab	107	#endif
ff88f8a3 RB	108	" .set pop \n"
ff88f8a3 RB	109	" .endm \n");
1da177e4	110
192ef366	111	#define raw_local_save_flags(x) \
1da177e4	112	__asm__ __volatile__( \
192ef366	113	"raw_local_save_flags %0" \
1da177e4 LT	114	: "=r" (x))
	115
	116	__asm__ (
192ef366	117	" .macro raw_local_irq_save result \n"
ff88f8a3 RB	118	" .set push \n"
	119	" .set reorder \n"
	120	" .set noat \n"
41c594ab RB	121	#ifdef CONFIG_MIPS_MT_SMTC
	122	" mfc0 \\result, $2, 1 \n"
	123	" ori $1, \\result, 0x400 \n"
	124	" .set noreorder \n"
	125	" mtc0 $1, $2, 1 \n"
	126	" andi \\result, \\result, 0x400 \n"
	127	#elif defined(CONFIG_CPU_MIPSR2)
ff88f8a3	128	" di \\result \n"
15265251	129	" andi \\result, 1 \n"
ff88f8a3 RB	130	#else
ff88f8a3 RB	131	" mfc0 \\result, $12 \n"
c226f260 AN	132	" ori $1, \\result, 0x1f \n"
c226f260 AN	133	" xori $1, 0x1f \n"
ff88f8a3 RB	134	" .set noreorder \n"
	135	" mtc0 $1, $12 \n"
	136	#endif
	137	" irq_disable_hazard \n"
	138	" .set pop \n"
	139	" .endm \n");
1da177e4	140
192ef366	141	#define raw_local_irq_save(x) \
1da177e4	142	__asm__ __volatile__( \
192ef366	143	"raw_local_irq_save\t%0" \
1da177e4 LT	144	: "=r" (x) \
	145	: /* no inputs */ \
	146	: "memory")
	147
	148	__asm__ (
192ef366	149	" .macro raw_local_irq_restore flags \n"
2e66fe24	150	" .set push \n"
ff88f8a3 RB	151	" .set noreorder \n"
ff88f8a3 RB	152	" .set noat \n"
41c594ab RB	153	#ifdef CONFIG_MIPS_MT_SMTC
	154	"mfc0 $1, $2, 1 \n"
	155	"andi \\flags, 0x400 \n"
	156	"ori $1, 0x400 \n"
	157	"xori $1, 0x400 \n"
	158	"or \\flags, $1 \n"
	159	"mtc0 \\flags, $2, 1 \n"
	160	#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
ff88f8a3 RB	161	/*
	162	* Slow, but doesn't suffer from a relativly unlikely race
	163	* condition we're having since days 1.
	164	*/
	165	" beqz \\flags, 1f \n"
	166	" di \n"
	167	" ei \n"
	168	"1: \n"
ec917c2c	169	#elif defined(CONFIG_CPU_MIPSR2)
ff88f8a3 RB	170	/*
	171	* Fast, dangerous. Life is fun, life is good.
	172	*/
	173	" mfc0 $1, $12 \n"
	174	" ins $1, \\flags, 0, 1 \n"
	175	" mtc0 $1, $12 \n"
	176	#else
	177	" mfc0 $1, $12 \n"
	178	" andi \\flags, 1 \n"
c226f260 AN	179	" ori $1, 0x1f \n"
c226f260 AN	180	" xori $1, 0x1f \n"
ff88f8a3 RB	181	" or \\flags, $1 \n"
	182	" mtc0 \\flags, $12 \n"
	183	#endif
	184	" irq_disable_hazard \n"
2e66fe24	185	" .set pop \n"
ff88f8a3	186	" .endm \n");
1da177e4	187
8a1e97ee RB	188	extern void smtc_ipi_replay(void);
	189
	190	static inline void raw_local_irq_restore(unsigned long flags)
	191	{
	192	unsigned long __tmp1;
	193
	194	#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
	195	/*
	196	* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
	197	* IPIs, at the cost of branch and call overhead on each
	198	* local_irq_restore()
	199	*/
	200	if (unlikely(!(flags & 0x0400)))
	201	smtc_ipi_replay();
	202	#endif
	203
	204	__asm__ __volatile__(
	205	"raw_local_irq_restore\t%0"
	206	: "=r" (__tmp1)
	207	: "0" (flags)
	208	: "memory");
	209	}
1da177e4	210
192ef366	211	static inline int raw_irqs_disabled_flags(unsigned long flags)
41c594ab RB	212	{
	213	#ifdef CONFIG_MIPS_MT_SMTC
	214	/*
	215	* SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
	216	*/
192ef366	217	return flags & 0x400;
41c594ab	218	#else
41c594ab RB	219	return !(flags & 1);
	220	#endif
	221	}
1da177e4	222
192ef366 RB	223	#endif
	224
	225	/*
	226	* Do the CPU's IRQ-state tracing from assembly code.
	227	*/
	228	#ifdef CONFIG_TRACE_IRQFLAGS
eae6c0da AN	229	/* Reload some registers clobbered by trace_hardirqs_on */
	230	#ifdef CONFIG_64BIT
	231	# define TRACE_IRQS_RELOAD_REGS \
	232	LONG_L $11, PT_R11(sp); \
	233	LONG_L $10, PT_R10(sp); \
	234	LONG_L $9, PT_R9(sp); \
	235	LONG_L $8, PT_R8(sp); \
	236	LONG_L $7, PT_R7(sp); \
	237	LONG_L $6, PT_R6(sp); \
	238	LONG_L $5, PT_R5(sp); \
	239	LONG_L $4, PT_R4(sp); \
	240	LONG_L $2, PT_R2(sp)
	241	#else
	242	# define TRACE_IRQS_RELOAD_REGS \
	243	LONG_L $7, PT_R7(sp); \
	244	LONG_L $6, PT_R6(sp); \
	245	LONG_L $5, PT_R5(sp); \
	246	LONG_L $4, PT_R4(sp); \
	247	LONG_L $2, PT_R2(sp)
	248	#endif
192ef366	249	# define TRACE_IRQS_ON \
eae6c0da	250	CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
192ef366	251	jal trace_hardirqs_on
eae6c0da AN	252	# define TRACE_IRQS_ON_RELOAD \
	253	TRACE_IRQS_ON; \
	254	TRACE_IRQS_RELOAD_REGS
192ef366 RB	255	# define TRACE_IRQS_OFF \
	256	jal trace_hardirqs_off
	257	#else
	258	# define TRACE_IRQS_ON
eae6c0da	259	# define TRACE_IRQS_ON_RELOAD
192ef366 RB	260	# define TRACE_IRQS_OFF
	261	#endif
	262
	263	#endif /* _ASM_IRQFLAGS_H */