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1da177e4 LT |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * Include file for Alchemy Semiconductor's Au1k CPU. | |
5 | * | |
6 | * Copyright 2000,2001 MontaVista Software Inc. | |
7 | * Author: MontaVista Software, Inc. | |
8 | * ppopov@mvista.com or source@mvista.com | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License along | |
27 | * with this program; if not, write to the Free Software Foundation, Inc., | |
28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | */ | |
30 | ||
31 | /* | |
32 | * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp | |
33 | */ | |
34 | ||
35 | #ifndef _AU1000_H_ | |
36 | #define _AU1000_H_ | |
37 | ||
38 | #include <linux/config.h> | |
39 | ||
40 | #ifndef _LANGUAGE_ASSEMBLY | |
41 | ||
42 | #include <linux/delay.h> | |
43 | #include <asm/io.h> | |
44 | ||
45 | /* cpu pipeline flush */ | |
46 | void static inline au_sync(void) | |
47 | { | |
48 | __asm__ volatile ("sync"); | |
49 | } | |
50 | ||
51 | void static inline au_sync_udelay(int us) | |
52 | { | |
53 | __asm__ volatile ("sync"); | |
54 | udelay(us); | |
55 | } | |
56 | ||
57 | void static inline au_sync_delay(int ms) | |
58 | { | |
59 | __asm__ volatile ("sync"); | |
60 | mdelay(ms); | |
61 | } | |
62 | ||
63 | void static inline au_writeb(u8 val, int reg) | |
64 | { | |
65 | *(volatile u8 *)(reg) = val; | |
66 | } | |
67 | ||
68 | void static inline au_writew(u16 val, int reg) | |
69 | { | |
70 | *(volatile u16 *)(reg) = val; | |
71 | } | |
72 | ||
73 | void static inline au_writel(u32 val, int reg) | |
74 | { | |
75 | *(volatile u32 *)(reg) = val; | |
76 | } | |
77 | ||
78 | static inline u8 au_readb(unsigned long port) | |
79 | { | |
80 | return (*(volatile u8 *)port); | |
81 | } | |
82 | ||
83 | static inline u16 au_readw(unsigned long port) | |
84 | { | |
85 | return (*(volatile u16 *)port); | |
86 | } | |
87 | ||
88 | static inline u32 au_readl(unsigned long port) | |
89 | { | |
90 | return (*(volatile u32 *)port); | |
91 | } | |
92 | ||
93 | /* These next three functions should be a generic part of the MIPS | |
94 | * kernel (with the 'au_' removed from the name) and selected for | |
95 | * processors that support the instructions. | |
96 | * Taken from PPC tree. -- Dan | |
97 | */ | |
98 | /* Return the bit position of the most significant 1 bit in a word */ | |
99 | static __inline__ int __ilog2(unsigned int x) | |
100 | { | |
101 | int lz; | |
102 | ||
103 | asm volatile ( | |
104 | ".set\tnoreorder\n\t" | |
105 | ".set\tnoat\n\t" | |
106 | ".set\tmips32\n\t" | |
107 | "clz\t%0,%1\n\t" | |
108 | ".set\tmips0\n\t" | |
109 | ".set\tat\n\t" | |
110 | ".set\treorder" | |
111 | : "=r" (lz) | |
112 | : "r" (x)); | |
113 | ||
114 | return 31 - lz; | |
115 | } | |
116 | ||
117 | static __inline__ int au_ffz(unsigned int x) | |
118 | { | |
119 | if ((x = ~x) == 0) | |
120 | return 32; | |
121 | return __ilog2(x & -x); | |
122 | } | |
123 | ||
124 | /* | |
125 | * ffs: find first bit set. This is defined the same way as | |
126 | * the libc and compiler builtin ffs routines, therefore | |
127 | * differs in spirit from the above ffz (man ffs). | |
128 | */ | |
129 | static __inline__ int au_ffs(int x) | |
130 | { | |
131 | return __ilog2(x & -x) + 1; | |
132 | } | |
133 | ||
134 | /* arch/mips/au1000/common/clocks.c */ | |
135 | extern void set_au1x00_speed(unsigned int new_freq); | |
136 | extern unsigned int get_au1x00_speed(void); | |
137 | extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); | |
138 | extern unsigned long get_au1x00_uart_baud_base(void); | |
139 | extern void set_au1x00_lcd_clock(void); | |
140 | extern unsigned int get_au1x00_lcd_clock(void); | |
141 | ||
142 | /* | |
143 | * Every board describes its IRQ mapping with this table. | |
144 | */ | |
145 | typedef struct au1xxx_irqmap { | |
146 | int im_irq; | |
147 | int im_type; | |
148 | int im_request; | |
149 | } au1xxx_irq_map_t; | |
150 | ||
151 | /* | |
152 | * init_IRQ looks for a table with this name. | |
153 | */ | |
154 | extern au1xxx_irq_map_t au1xxx_irq_map[]; | |
155 | ||
156 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | |
157 | ||
158 | #ifdef CONFIG_PM | |
159 | /* no CP0 timer irq */ | |
160 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) | |
161 | #else | |
162 | #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) | |
163 | #endif | |
164 | ||
165 | /* SDRAM Controller */ | |
166 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) | |
167 | #define MEM_SDMODE0 0xB4000000 | |
168 | #define MEM_SDMODE1 0xB4000004 | |
169 | #define MEM_SDMODE2 0xB4000008 | |
170 | ||
171 | #define MEM_SDADDR0 0xB400000C | |
172 | #define MEM_SDADDR1 0xB4000010 | |
173 | #define MEM_SDADDR2 0xB4000014 | |
174 | ||
175 | #define MEM_SDREFCFG 0xB4000018 | |
176 | #define MEM_SDPRECMD 0xB400001C | |
177 | #define MEM_SDAUTOREF 0xB4000020 | |
178 | ||
179 | #define MEM_SDWRMD0 0xB4000024 | |
180 | #define MEM_SDWRMD1 0xB4000028 | |
181 | #define MEM_SDWRMD2 0xB400002C | |
182 | ||
183 | #define MEM_SDSLEEP 0xB4000030 | |
184 | #define MEM_SDSMCKE 0xB4000034 | |
185 | #endif | |
186 | ||
187 | /* Static Bus Controller */ | |
188 | #define MEM_STCFG0 0xB4001000 | |
189 | #define MEM_STTIME0 0xB4001004 | |
190 | #define MEM_STADDR0 0xB4001008 | |
191 | ||
192 | #define MEM_STCFG1 0xB4001010 | |
193 | #define MEM_STTIME1 0xB4001014 | |
194 | #define MEM_STADDR1 0xB4001018 | |
195 | ||
196 | #define MEM_STCFG2 0xB4001020 | |
197 | #define MEM_STTIME2 0xB4001024 | |
198 | #define MEM_STADDR2 0xB4001028 | |
199 | ||
200 | #define MEM_STCFG3 0xB4001030 | |
201 | #define MEM_STTIME3 0xB4001034 | |
202 | #define MEM_STADDR3 0xB4001038 | |
203 | ||
204 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | |
205 | #define MEM_STNDCTL 0xB4001100 | |
206 | #define MEM_STSTAT 0xB4001104 | |
207 | ||
208 | #define MEM_STNAND_CMD (0x0) | |
209 | #define MEM_STNAND_ADDR (0x4) | |
210 | #define MEM_STNAND_DATA (0x20) | |
211 | #endif | |
212 | ||
213 | /* Interrupt Controller 0 */ | |
214 | #define IC0_CFG0RD 0xB0400040 | |
215 | #define IC0_CFG0SET 0xB0400040 | |
216 | #define IC0_CFG0CLR 0xB0400044 | |
217 | ||
218 | #define IC0_CFG1RD 0xB0400048 | |
219 | #define IC0_CFG1SET 0xB0400048 | |
220 | #define IC0_CFG1CLR 0xB040004C | |
221 | ||
222 | #define IC0_CFG2RD 0xB0400050 | |
223 | #define IC0_CFG2SET 0xB0400050 | |
224 | #define IC0_CFG2CLR 0xB0400054 | |
225 | ||
226 | #define IC0_REQ0INT 0xB0400054 | |
227 | #define IC0_SRCRD 0xB0400058 | |
228 | #define IC0_SRCSET 0xB0400058 | |
229 | #define IC0_SRCCLR 0xB040005C | |
230 | #define IC0_REQ1INT 0xB040005C | |
231 | ||
232 | #define IC0_ASSIGNRD 0xB0400060 | |
233 | #define IC0_ASSIGNSET 0xB0400060 | |
234 | #define IC0_ASSIGNCLR 0xB0400064 | |
235 | ||
236 | #define IC0_WAKERD 0xB0400068 | |
237 | #define IC0_WAKESET 0xB0400068 | |
238 | #define IC0_WAKECLR 0xB040006C | |
239 | ||
240 | #define IC0_MASKRD 0xB0400070 | |
241 | #define IC0_MASKSET 0xB0400070 | |
242 | #define IC0_MASKCLR 0xB0400074 | |
243 | ||
244 | #define IC0_RISINGRD 0xB0400078 | |
245 | #define IC0_RISINGCLR 0xB0400078 | |
246 | #define IC0_FALLINGRD 0xB040007C | |
247 | #define IC0_FALLINGCLR 0xB040007C | |
248 | ||
249 | #define IC0_TESTBIT 0xB0400080 | |
250 | ||
251 | /* Interrupt Controller 1 */ | |
252 | #define IC1_CFG0RD 0xB1800040 | |
253 | #define IC1_CFG0SET 0xB1800040 | |
254 | #define IC1_CFG0CLR 0xB1800044 | |
255 | ||
256 | #define IC1_CFG1RD 0xB1800048 | |
257 | #define IC1_CFG1SET 0xB1800048 | |
258 | #define IC1_CFG1CLR 0xB180004C | |
259 | ||
260 | #define IC1_CFG2RD 0xB1800050 | |
261 | #define IC1_CFG2SET 0xB1800050 | |
262 | #define IC1_CFG2CLR 0xB1800054 | |
263 | ||
264 | #define IC1_REQ0INT 0xB1800054 | |
265 | #define IC1_SRCRD 0xB1800058 | |
266 | #define IC1_SRCSET 0xB1800058 | |
267 | #define IC1_SRCCLR 0xB180005C | |
268 | #define IC1_REQ1INT 0xB180005C | |
269 | ||
270 | #define IC1_ASSIGNRD 0xB1800060 | |
271 | #define IC1_ASSIGNSET 0xB1800060 | |
272 | #define IC1_ASSIGNCLR 0xB1800064 | |
273 | ||
274 | #define IC1_WAKERD 0xB1800068 | |
275 | #define IC1_WAKESET 0xB1800068 | |
276 | #define IC1_WAKECLR 0xB180006C | |
277 | ||
278 | #define IC1_MASKRD 0xB1800070 | |
279 | #define IC1_MASKSET 0xB1800070 | |
280 | #define IC1_MASKCLR 0xB1800074 | |
281 | ||
282 | #define IC1_RISINGRD 0xB1800078 | |
283 | #define IC1_RISINGCLR 0xB1800078 | |
284 | #define IC1_FALLINGRD 0xB180007C | |
285 | #define IC1_FALLINGCLR 0xB180007C | |
286 | ||
287 | #define IC1_TESTBIT 0xB1800080 | |
288 | ||
289 | /* Interrupt Configuration Modes */ | |
290 | #define INTC_INT_DISABLED 0 | |
291 | #define INTC_INT_RISE_EDGE 0x1 | |
292 | #define INTC_INT_FALL_EDGE 0x2 | |
293 | #define INTC_INT_RISE_AND_FALL_EDGE 0x3 | |
294 | #define INTC_INT_HIGH_LEVEL 0x5 | |
295 | #define INTC_INT_LOW_LEVEL 0x6 | |
296 | #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 | |
297 | ||
298 | /* Interrupt Numbers */ | |
299 | /* Au1000 */ | |
300 | #ifdef CONFIG_SOC_AU1000 | |
301 | #define AU1000_UART0_INT 0 | |
302 | #define AU1000_UART1_INT 1 /* au1000 */ | |
303 | #define AU1000_UART2_INT 2 /* au1000 */ | |
304 | #define AU1000_UART3_INT 3 | |
305 | #define AU1000_SSI0_INT 4 /* au1000 */ | |
306 | #define AU1000_SSI1_INT 5 /* au1000 */ | |
307 | #define AU1000_DMA_INT_BASE 6 | |
308 | #define AU1000_TOY_INT 14 | |
309 | #define AU1000_TOY_MATCH0_INT 15 | |
310 | #define AU1000_TOY_MATCH1_INT 16 | |
311 | #define AU1000_TOY_MATCH2_INT 17 | |
312 | #define AU1000_RTC_INT 18 | |
313 | #define AU1000_RTC_MATCH0_INT 19 | |
314 | #define AU1000_RTC_MATCH1_INT 20 | |
315 | #define AU1000_RTC_MATCH2_INT 21 | |
316 | #define AU1000_IRDA_TX_INT 22 /* au1000 */ | |
317 | #define AU1000_IRDA_RX_INT 23 /* au1000 */ | |
318 | #define AU1000_USB_DEV_REQ_INT 24 | |
319 | #define AU1000_USB_DEV_SUS_INT 25 | |
320 | #define AU1000_USB_HOST_INT 26 | |
321 | #define AU1000_ACSYNC_INT 27 | |
322 | #define AU1000_MAC0_DMA_INT 28 | |
323 | #define AU1000_MAC1_DMA_INT 29 | |
324 | #define AU1000_I2S_UO_INT 30 /* au1000 */ | |
325 | #define AU1000_AC97C_INT 31 | |
326 | #define AU1000_GPIO_0 32 | |
327 | #define AU1000_GPIO_1 33 | |
328 | #define AU1000_GPIO_2 34 | |
329 | #define AU1000_GPIO_3 35 | |
330 | #define AU1000_GPIO_4 36 | |
331 | #define AU1000_GPIO_5 37 | |
332 | #define AU1000_GPIO_6 38 | |
333 | #define AU1000_GPIO_7 39 | |
334 | #define AU1000_GPIO_8 40 | |
335 | #define AU1000_GPIO_9 41 | |
336 | #define AU1000_GPIO_10 42 | |
337 | #define AU1000_GPIO_11 43 | |
338 | #define AU1000_GPIO_12 44 | |
339 | #define AU1000_GPIO_13 45 | |
340 | #define AU1000_GPIO_14 46 | |
341 | #define AU1000_GPIO_15 47 | |
342 | #define AU1000_GPIO_16 48 | |
343 | #define AU1000_GPIO_17 49 | |
344 | #define AU1000_GPIO_18 50 | |
345 | #define AU1000_GPIO_19 51 | |
346 | #define AU1000_GPIO_20 52 | |
347 | #define AU1000_GPIO_21 53 | |
348 | #define AU1000_GPIO_22 54 | |
349 | #define AU1000_GPIO_23 55 | |
350 | #define AU1000_GPIO_24 56 | |
351 | #define AU1000_GPIO_25 57 | |
352 | #define AU1000_GPIO_26 58 | |
353 | #define AU1000_GPIO_27 59 | |
354 | #define AU1000_GPIO_28 60 | |
355 | #define AU1000_GPIO_29 61 | |
356 | #define AU1000_GPIO_30 62 | |
357 | #define AU1000_GPIO_31 63 | |
358 | ||
359 | #define UART0_ADDR 0xB1100000 | |
360 | #define UART1_ADDR 0xB1200000 | |
361 | #define UART2_ADDR 0xB1300000 | |
362 | #define UART3_ADDR 0xB1400000 | |
363 | ||
364 | #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap | |
365 | #define USB_HOST_CONFIG 0xB017fffc | |
366 | ||
367 | #define AU1000_ETH0_BASE 0xB0500000 | |
368 | #define AU1000_ETH1_BASE 0xB0510000 | |
369 | #define AU1000_MAC0_ENABLE 0xB0520000 | |
370 | #define AU1000_MAC1_ENABLE 0xB0520004 | |
371 | #define NUM_ETH_INTERFACES 2 | |
372 | #endif // CONFIG_SOC_AU1000 | |
373 | ||
374 | /* Au1500 */ | |
375 | #ifdef CONFIG_SOC_AU1500 | |
376 | #define AU1500_UART0_INT 0 | |
377 | #define AU1000_PCI_INTA 1 /* au1500 */ | |
378 | #define AU1000_PCI_INTB 2 /* au1500 */ | |
379 | #define AU1500_UART3_INT 3 | |
380 | #define AU1000_PCI_INTC 4 /* au1500 */ | |
381 | #define AU1000_PCI_INTD 5 /* au1500 */ | |
382 | #define AU1000_DMA_INT_BASE 6 | |
383 | #define AU1000_TOY_INT 14 | |
384 | #define AU1000_TOY_MATCH0_INT 15 | |
385 | #define AU1000_TOY_MATCH1_INT 16 | |
386 | #define AU1000_TOY_MATCH2_INT 17 | |
387 | #define AU1000_RTC_INT 18 | |
388 | #define AU1000_RTC_MATCH0_INT 19 | |
389 | #define AU1000_RTC_MATCH1_INT 20 | |
390 | #define AU1000_RTC_MATCH2_INT 21 | |
391 | #define AU1500_PCI_ERR_INT 22 | |
392 | #define AU1000_USB_DEV_REQ_INT 24 | |
393 | #define AU1000_USB_DEV_SUS_INT 25 | |
394 | #define AU1000_USB_HOST_INT 26 | |
395 | #define AU1000_ACSYNC_INT 27 | |
396 | #define AU1500_MAC0_DMA_INT 28 | |
397 | #define AU1500_MAC1_DMA_INT 29 | |
398 | #define AU1000_AC97C_INT 31 | |
399 | #define AU1000_GPIO_0 32 | |
400 | #define AU1000_GPIO_1 33 | |
401 | #define AU1000_GPIO_2 34 | |
402 | #define AU1000_GPIO_3 35 | |
403 | #define AU1000_GPIO_4 36 | |
404 | #define AU1000_GPIO_5 37 | |
405 | #define AU1000_GPIO_6 38 | |
406 | #define AU1000_GPIO_7 39 | |
407 | #define AU1000_GPIO_8 40 | |
408 | #define AU1000_GPIO_9 41 | |
409 | #define AU1000_GPIO_10 42 | |
410 | #define AU1000_GPIO_11 43 | |
411 | #define AU1000_GPIO_12 44 | |
412 | #define AU1000_GPIO_13 45 | |
413 | #define AU1000_GPIO_14 46 | |
414 | #define AU1000_GPIO_15 47 | |
415 | #define AU1500_GPIO_200 48 | |
416 | #define AU1500_GPIO_201 49 | |
417 | #define AU1500_GPIO_202 50 | |
418 | #define AU1500_GPIO_203 51 | |
419 | #define AU1500_GPIO_20 52 | |
420 | #define AU1500_GPIO_204 53 | |
421 | #define AU1500_GPIO_205 54 | |
422 | #define AU1500_GPIO_23 55 | |
423 | #define AU1500_GPIO_24 56 | |
424 | #define AU1500_GPIO_25 57 | |
425 | #define AU1500_GPIO_26 58 | |
426 | #define AU1500_GPIO_27 59 | |
427 | #define AU1500_GPIO_28 60 | |
428 | #define AU1500_GPIO_206 61 | |
429 | #define AU1500_GPIO_207 62 | |
430 | #define AU1500_GPIO_208_215 63 | |
431 | ||
432 | #define UART0_ADDR 0xB1100000 | |
433 | #define UART3_ADDR 0xB1400000 | |
434 | ||
435 | #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap | |
436 | #define USB_HOST_CONFIG 0xB017fffc | |
437 | ||
438 | #define AU1500_ETH0_BASE 0xB1500000 | |
439 | #define AU1500_ETH1_BASE 0xB1510000 | |
440 | #define AU1500_MAC0_ENABLE 0xB1520000 | |
441 | #define AU1500_MAC1_ENABLE 0xB1520004 | |
442 | #define NUM_ETH_INTERFACES 2 | |
443 | #endif // CONFIG_SOC_AU1500 | |
444 | ||
445 | /* Au1100 */ | |
446 | #ifdef CONFIG_SOC_AU1100 | |
447 | #define AU1100_UART0_INT 0 | |
448 | #define AU1100_UART1_INT 1 | |
449 | #define AU1100_SD_INT 2 | |
450 | #define AU1100_UART3_INT 3 | |
451 | #define AU1000_SSI0_INT 4 | |
452 | #define AU1000_SSI1_INT 5 | |
453 | #define AU1000_DMA_INT_BASE 6 | |
454 | #define AU1000_TOY_INT 14 | |
455 | #define AU1000_TOY_MATCH0_INT 15 | |
456 | #define AU1000_TOY_MATCH1_INT 16 | |
457 | #define AU1000_TOY_MATCH2_INT 17 | |
458 | #define AU1000_RTC_INT 18 | |
459 | #define AU1000_RTC_MATCH0_INT 19 | |
460 | #define AU1000_RTC_MATCH1_INT 20 | |
461 | #define AU1000_RTC_MATCH2_INT 21 | |
462 | #define AU1000_IRDA_TX_INT 22 | |
463 | #define AU1000_IRDA_RX_INT 23 | |
464 | #define AU1000_USB_DEV_REQ_INT 24 | |
465 | #define AU1000_USB_DEV_SUS_INT 25 | |
466 | #define AU1000_USB_HOST_INT 26 | |
467 | #define AU1000_ACSYNC_INT 27 | |
468 | #define AU1100_MAC0_DMA_INT 28 | |
469 | #define AU1100_GPIO_208_215 29 | |
470 | #define AU1100_LCD_INT 30 | |
471 | #define AU1000_AC97C_INT 31 | |
472 | #define AU1000_GPIO_0 32 | |
473 | #define AU1000_GPIO_1 33 | |
474 | #define AU1000_GPIO_2 34 | |
475 | #define AU1000_GPIO_3 35 | |
476 | #define AU1000_GPIO_4 36 | |
477 | #define AU1000_GPIO_5 37 | |
478 | #define AU1000_GPIO_6 38 | |
479 | #define AU1000_GPIO_7 39 | |
480 | #define AU1000_GPIO_8 40 | |
481 | #define AU1000_GPIO_9 41 | |
482 | #define AU1000_GPIO_10 42 | |
483 | #define AU1000_GPIO_11 43 | |
484 | #define AU1000_GPIO_12 44 | |
485 | #define AU1000_GPIO_13 45 | |
486 | #define AU1000_GPIO_14 46 | |
487 | #define AU1000_GPIO_15 47 | |
488 | ||
489 | #define UART0_ADDR 0xB1100000 | |
490 | #define UART1_ADDR 0xB1200000 | |
491 | #define UART3_ADDR 0xB1400000 | |
492 | ||
493 | #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap | |
494 | #define USB_HOST_CONFIG 0xB017fffc | |
495 | ||
496 | #define AU1100_ETH0_BASE 0xB0500000 | |
497 | #define AU1100_MAC0_ENABLE 0xB0520000 | |
498 | #define NUM_ETH_INTERFACES 1 | |
499 | #endif // CONFIG_SOC_AU1100 | |
500 | ||
501 | #ifdef CONFIG_SOC_AU1550 | |
502 | #define AU1550_UART0_INT 0 | |
503 | #define AU1550_PCI_INTA 1 | |
504 | #define AU1550_PCI_INTB 2 | |
505 | #define AU1550_DDMA_INT 3 | |
506 | #define AU1550_CRYPTO_INT 4 | |
507 | #define AU1550_PCI_INTC 5 | |
508 | #define AU1550_PCI_INTD 6 | |
509 | #define AU1550_PCI_RST_INT 7 | |
510 | #define AU1550_UART1_INT 8 | |
511 | #define AU1550_UART3_INT 9 | |
512 | #define AU1550_PSC0_INT 10 | |
513 | #define AU1550_PSC1_INT 11 | |
514 | #define AU1550_PSC2_INT 12 | |
515 | #define AU1550_PSC3_INT 13 | |
516 | #define AU1550_TOY_INT 14 | |
517 | #define AU1550_TOY_MATCH0_INT 15 | |
518 | #define AU1550_TOY_MATCH1_INT 16 | |
519 | #define AU1550_TOY_MATCH2_INT 17 | |
520 | #define AU1550_RTC_INT 18 | |
521 | #define AU1550_RTC_MATCH0_INT 19 | |
522 | #define AU1550_RTC_MATCH1_INT 20 | |
523 | #define AU1550_RTC_MATCH2_INT 21 | |
524 | #define AU1550_NAND_INT 23 | |
525 | #define AU1550_USB_DEV_REQ_INT 24 | |
526 | #define AU1550_USB_DEV_SUS_INT 25 | |
527 | #define AU1550_USB_HOST_INT 26 | |
528 | #define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT | |
529 | #define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT | |
530 | #define AU1000_USB_HOST_INT AU1550_USB_HOST_INT | |
531 | #define AU1550_MAC0_DMA_INT 27 | |
532 | #define AU1550_MAC1_DMA_INT 28 | |
533 | #define AU1000_GPIO_0 32 | |
534 | #define AU1000_GPIO_1 33 | |
535 | #define AU1000_GPIO_2 34 | |
536 | #define AU1000_GPIO_3 35 | |
537 | #define AU1000_GPIO_4 36 | |
538 | #define AU1000_GPIO_5 37 | |
539 | #define AU1000_GPIO_6 38 | |
540 | #define AU1000_GPIO_7 39 | |
541 | #define AU1000_GPIO_8 40 | |
542 | #define AU1000_GPIO_9 41 | |
543 | #define AU1000_GPIO_10 42 | |
544 | #define AU1000_GPIO_11 43 | |
545 | #define AU1000_GPIO_12 44 | |
546 | #define AU1000_GPIO_13 45 | |
547 | #define AU1000_GPIO_14 46 | |
548 | #define AU1000_GPIO_15 47 | |
549 | #define AU1550_GPIO_200 48 | |
550 | #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205 | |
551 | #define AU1500_GPIO_16 50 | |
552 | #define AU1500_GPIO_17 51 | |
553 | #define AU1500_GPIO_20 52 | |
554 | #define AU1500_GPIO_21 53 | |
555 | #define AU1500_GPIO_22 54 | |
556 | #define AU1500_GPIO_23 55 | |
557 | #define AU1500_GPIO_24 56 | |
558 | #define AU1500_GPIO_25 57 | |
559 | #define AU1500_GPIO_26 58 | |
560 | #define AU1500_GPIO_27 59 | |
561 | #define AU1500_GPIO_28 60 | |
562 | #define AU1500_GPIO_206 61 | |
563 | #define AU1500_GPIO_207 62 | |
564 | #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 | |
565 | ||
566 | #define UART0_ADDR 0xB1100000 | |
567 | #define UART1_ADDR 0xB1200000 | |
568 | #define UART3_ADDR 0xB1400000 | |
569 | ||
570 | #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap | |
571 | #define USB_HOST_CONFIG 0xB4027ffc | |
572 | ||
573 | #define AU1550_ETH0_BASE 0xB0500000 | |
574 | #define AU1550_ETH1_BASE 0xB0510000 | |
575 | #define AU1550_MAC0_ENABLE 0xB0520000 | |
576 | #define AU1550_MAC1_ENABLE 0xB0520004 | |
577 | #define NUM_ETH_INTERFACES 2 | |
578 | #endif // CONFIG_SOC_AU1550 | |
579 | ||
580 | #ifdef CONFIG_SOC_AU1200 | |
581 | #define AU1200_UART0_INT 0 | |
582 | #define AU1200_SWT_INT 1 | |
583 | #define AU1200_SD_INT 2 | |
584 | #define AU1200_DDMA_INT 3 | |
585 | #define AU1200_MAE_BE_INT 4 | |
586 | #define AU1200_GPIO_200 5 | |
587 | #define AU1200_GPIO_201 6 | |
588 | #define AU1200_GPIO_202 7 | |
589 | #define AU1200_UART1_INT 8 | |
590 | #define AU1200_MAE_FE_INT 9 | |
591 | #define AU1200_PSC0_INT 10 | |
592 | #define AU1200_PSC1_INT 11 | |
593 | #define AU1200_AES_INT 12 | |
594 | #define AU1200_CAMERA_INT 13 | |
595 | #define AU1200_TOY_INT 14 | |
596 | #define AU1200_TOY_MATCH0_INT 15 | |
597 | #define AU1200_TOY_MATCH1_INT 16 | |
598 | #define AU1200_TOY_MATCH2_INT 17 | |
599 | #define AU1200_RTC_INT 18 | |
600 | #define AU1200_RTC_MATCH0_INT 19 | |
601 | #define AU1200_RTC_MATCH1_INT 20 | |
602 | #define AU1200_RTC_MATCH2_INT 21 | |
603 | #define AU1200_NAND_INT 23 | |
604 | #define AU1200_GPIO_204 24 | |
605 | #define AU1200_GPIO_205 25 | |
606 | #define AU1200_GPIO_206 26 | |
607 | #define AU1200_GPIO_207 27 | |
608 | #define AU1200_GPIO_208_215 28 // Logical OR of 208:215 | |
609 | #define AU1200_USB_INT 29 | |
610 | #define AU1200_LCD_INT 30 | |
611 | #define AU1200_MAE_BOTH_INT 31 | |
612 | #define AU1000_GPIO_0 32 | |
613 | #define AU1000_GPIO_1 33 | |
614 | #define AU1000_GPIO_2 34 | |
615 | #define AU1000_GPIO_3 35 | |
616 | #define AU1000_GPIO_4 36 | |
617 | #define AU1000_GPIO_5 37 | |
618 | #define AU1000_GPIO_6 38 | |
619 | #define AU1000_GPIO_7 39 | |
620 | #define AU1000_GPIO_8 40 | |
621 | #define AU1000_GPIO_9 41 | |
622 | #define AU1000_GPIO_10 42 | |
623 | #define AU1000_GPIO_11 43 | |
624 | #define AU1000_GPIO_12 44 | |
625 | #define AU1000_GPIO_13 45 | |
626 | #define AU1000_GPIO_14 46 | |
627 | #define AU1000_GPIO_15 47 | |
628 | #define AU1000_GPIO_16 48 | |
629 | #define AU1000_GPIO_17 49 | |
630 | #define AU1000_GPIO_18 50 | |
631 | #define AU1000_GPIO_19 51 | |
632 | #define AU1000_GPIO_20 52 | |
633 | #define AU1000_GPIO_21 53 | |
634 | #define AU1000_GPIO_22 54 | |
635 | #define AU1000_GPIO_23 55 | |
636 | #define AU1000_GPIO_24 56 | |
637 | #define AU1000_GPIO_25 57 | |
638 | #define AU1000_GPIO_26 58 | |
639 | #define AU1000_GPIO_27 59 | |
640 | #define AU1000_GPIO_28 60 | |
641 | #define AU1000_GPIO_29 61 | |
642 | #define AU1000_GPIO_30 62 | |
643 | #define AU1000_GPIO_31 63 | |
644 | ||
645 | #define UART0_ADDR 0xB1100000 | |
646 | #define UART1_ADDR 0xB1200000 | |
647 | ||
648 | #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap | |
649 | #define USB_HOST_CONFIG 0xB4027ffc | |
650 | ||
651 | // these are here for prototyping on au1550 (do not exist on au1200) | |
652 | #define AU1200_ETH0_BASE 0xB0500000 | |
653 | #define AU1200_ETH1_BASE 0xB0510000 | |
654 | #define AU1200_MAC0_ENABLE 0xB0520000 | |
655 | #define AU1200_MAC1_ENABLE 0xB0520004 | |
656 | #define NUM_ETH_INTERFACES 2 | |
657 | #endif // CONFIG_SOC_AU1200 | |
658 | ||
659 | #define AU1000_LAST_INTC0_INT 31 | |
660 | #define AU1000_MAX_INTR 63 | |
661 | ||
662 | ||
663 | /* Programmable Counters 0 and 1 */ | |
664 | #define SYS_BASE 0xB1900000 | |
665 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | |
666 | #define SYS_CNTRL_E1S (1<<23) | |
667 | #define SYS_CNTRL_T1S (1<<20) | |
668 | #define SYS_CNTRL_M21 (1<<19) | |
669 | #define SYS_CNTRL_M11 (1<<18) | |
670 | #define SYS_CNTRL_M01 (1<<17) | |
671 | #define SYS_CNTRL_C1S (1<<16) | |
672 | #define SYS_CNTRL_BP (1<<14) | |
673 | #define SYS_CNTRL_EN1 (1<<13) | |
674 | #define SYS_CNTRL_BT1 (1<<12) | |
675 | #define SYS_CNTRL_EN0 (1<<11) | |
676 | #define SYS_CNTRL_BT0 (1<<10) | |
677 | #define SYS_CNTRL_E0 (1<<8) | |
678 | #define SYS_CNTRL_E0S (1<<7) | |
679 | #define SYS_CNTRL_32S (1<<5) | |
680 | #define SYS_CNTRL_T0S (1<<4) | |
681 | #define SYS_CNTRL_M20 (1<<3) | |
682 | #define SYS_CNTRL_M10 (1<<2) | |
683 | #define SYS_CNTRL_M00 (1<<1) | |
684 | #define SYS_CNTRL_C0S (1<<0) | |
685 | ||
686 | /* Programmable Counter 0 Registers */ | |
687 | #define SYS_TOYTRIM (SYS_BASE + 0) | |
688 | #define SYS_TOYWRITE (SYS_BASE + 4) | |
689 | #define SYS_TOYMATCH0 (SYS_BASE + 8) | |
690 | #define SYS_TOYMATCH1 (SYS_BASE + 0xC) | |
691 | #define SYS_TOYMATCH2 (SYS_BASE + 0x10) | |
692 | #define SYS_TOYREAD (SYS_BASE + 0x40) | |
693 | ||
694 | /* Programmable Counter 1 Registers */ | |
695 | #define SYS_RTCTRIM (SYS_BASE + 0x44) | |
696 | #define SYS_RTCWRITE (SYS_BASE + 0x48) | |
697 | #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) | |
698 | #define SYS_RTCMATCH1 (SYS_BASE + 0x50) | |
699 | #define SYS_RTCMATCH2 (SYS_BASE + 0x54) | |
700 | #define SYS_RTCREAD (SYS_BASE + 0x58) | |
701 | ||
702 | /* I2S Controller */ | |
703 | #define I2S_DATA 0xB1000000 | |
704 | #define I2S_DATA_MASK (0xffffff) | |
705 | #define I2S_CONFIG 0xB1000004 | |
706 | #define I2S_CONFIG_XU (1<<25) | |
707 | #define I2S_CONFIG_XO (1<<24) | |
708 | #define I2S_CONFIG_RU (1<<23) | |
709 | #define I2S_CONFIG_RO (1<<22) | |
710 | #define I2S_CONFIG_TR (1<<21) | |
711 | #define I2S_CONFIG_TE (1<<20) | |
712 | #define I2S_CONFIG_TF (1<<19) | |
713 | #define I2S_CONFIG_RR (1<<18) | |
714 | #define I2S_CONFIG_RE (1<<17) | |
715 | #define I2S_CONFIG_RF (1<<16) | |
716 | #define I2S_CONFIG_PD (1<<11) | |
717 | #define I2S_CONFIG_LB (1<<10) | |
718 | #define I2S_CONFIG_IC (1<<9) | |
719 | #define I2S_CONFIG_FM_BIT 7 | |
720 | #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) | |
721 | #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) | |
722 | #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) | |
723 | #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) | |
724 | #define I2S_CONFIG_TN (1<<6) | |
725 | #define I2S_CONFIG_RN (1<<5) | |
726 | #define I2S_CONFIG_SZ_BIT 0 | |
727 | #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) | |
728 | ||
729 | #define I2S_CONTROL 0xB1000008 | |
730 | #define I2S_CONTROL_D (1<<1) | |
731 | #define I2S_CONTROL_CE (1<<0) | |
732 | ||
733 | /* USB Host Controller */ | |
734 | #define USB_OHCI_LEN 0x00100000 | |
735 | ||
736 | /* USB Device Controller */ | |
737 | #define USBD_EP0RD 0xB0200000 | |
738 | #define USBD_EP0WR 0xB0200004 | |
739 | #define USBD_EP2WR 0xB0200008 | |
740 | #define USBD_EP3WR 0xB020000C | |
741 | #define USBD_EP4RD 0xB0200010 | |
742 | #define USBD_EP5RD 0xB0200014 | |
743 | #define USBD_INTEN 0xB0200018 | |
744 | #define USBD_INTSTAT 0xB020001C | |
745 | #define USBDEV_INT_SOF (1<<12) | |
746 | #define USBDEV_INT_HF_BIT 6 | |
747 | #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) | |
748 | #define USBDEV_INT_CMPLT_BIT 0 | |
749 | #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) | |
750 | #define USBD_CONFIG 0xB0200020 | |
751 | #define USBD_EP0CS 0xB0200024 | |
752 | #define USBD_EP2CS 0xB0200028 | |
753 | #define USBD_EP3CS 0xB020002C | |
754 | #define USBD_EP4CS 0xB0200030 | |
755 | #define USBD_EP5CS 0xB0200034 | |
756 | #define USBDEV_CS_SU (1<<14) | |
757 | #define USBDEV_CS_NAK (1<<13) | |
758 | #define USBDEV_CS_ACK (1<<12) | |
759 | #define USBDEV_CS_BUSY (1<<11) | |
760 | #define USBDEV_CS_TSIZE_BIT 1 | |
761 | #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) | |
762 | #define USBDEV_CS_STALL (1<<0) | |
763 | #define USBD_EP0RDSTAT 0xB0200040 | |
764 | #define USBD_EP0WRSTAT 0xB0200044 | |
765 | #define USBD_EP2WRSTAT 0xB0200048 | |
766 | #define USBD_EP3WRSTAT 0xB020004C | |
767 | #define USBD_EP4RDSTAT 0xB0200050 | |
768 | #define USBD_EP5RDSTAT 0xB0200054 | |
769 | #define USBDEV_FSTAT_FLUSH (1<<6) | |
770 | #define USBDEV_FSTAT_UF (1<<5) | |
771 | #define USBDEV_FSTAT_OF (1<<4) | |
772 | #define USBDEV_FSTAT_FCNT_BIT 0 | |
773 | #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) | |
774 | #define USBD_ENABLE 0xB0200058 | |
775 | #define USBDEV_ENABLE (1<<1) | |
776 | #define USBDEV_CE (1<<0) | |
777 | ||
778 | /* Ethernet Controllers */ | |
779 | ||
780 | /* 4 byte offsets from AU1000_ETH_BASE */ | |
781 | #define MAC_CONTROL 0x0 | |
782 | #define MAC_RX_ENABLE (1<<2) | |
783 | #define MAC_TX_ENABLE (1<<3) | |
784 | #define MAC_DEF_CHECK (1<<5) | |
785 | #define MAC_SET_BL(X) (((X)&0x3)<<6) | |
786 | #define MAC_AUTO_PAD (1<<8) | |
787 | #define MAC_DISABLE_RETRY (1<<10) | |
788 | #define MAC_DISABLE_BCAST (1<<11) | |
789 | #define MAC_LATE_COL (1<<12) | |
790 | #define MAC_HASH_MODE (1<<13) | |
791 | #define MAC_HASH_ONLY (1<<15) | |
792 | #define MAC_PASS_ALL (1<<16) | |
793 | #define MAC_INVERSE_FILTER (1<<17) | |
794 | #define MAC_PROMISCUOUS (1<<18) | |
795 | #define MAC_PASS_ALL_MULTI (1<<19) | |
796 | #define MAC_FULL_DUPLEX (1<<20) | |
797 | #define MAC_NORMAL_MODE 0 | |
798 | #define MAC_INT_LOOPBACK (1<<21) | |
799 | #define MAC_EXT_LOOPBACK (1<<22) | |
800 | #define MAC_DISABLE_RX_OWN (1<<23) | |
801 | #define MAC_BIG_ENDIAN (1<<30) | |
802 | #define MAC_RX_ALL (1<<31) | |
803 | #define MAC_ADDRESS_HIGH 0x4 | |
804 | #define MAC_ADDRESS_LOW 0x8 | |
805 | #define MAC_MCAST_HIGH 0xC | |
806 | #define MAC_MCAST_LOW 0x10 | |
807 | #define MAC_MII_CNTRL 0x14 | |
808 | #define MAC_MII_BUSY (1<<0) | |
809 | #define MAC_MII_READ 0 | |
810 | #define MAC_MII_WRITE (1<<1) | |
811 | #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) | |
812 | #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) | |
813 | #define MAC_MII_DATA 0x18 | |
814 | #define MAC_FLOW_CNTRL 0x1C | |
815 | #define MAC_FLOW_CNTRL_BUSY (1<<0) | |
816 | #define MAC_FLOW_CNTRL_ENABLE (1<<1) | |
817 | #define MAC_PASS_CONTROL (1<<2) | |
818 | #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) | |
819 | #define MAC_VLAN1_TAG 0x20 | |
820 | #define MAC_VLAN2_TAG 0x24 | |
821 | ||
822 | /* Ethernet Controller Enable */ | |
823 | ||
824 | #define MAC_EN_CLOCK_ENABLE (1<<0) | |
825 | #define MAC_EN_RESET0 (1<<1) | |
826 | #define MAC_EN_TOSS (0<<2) | |
827 | #define MAC_EN_CACHEABLE (1<<3) | |
828 | #define MAC_EN_RESET1 (1<<4) | |
829 | #define MAC_EN_RESET2 (1<<5) | |
830 | #define MAC_DMA_RESET (1<<6) | |
831 | ||
832 | /* Ethernet Controller DMA Channels */ | |
833 | ||
834 | #define MAC0_TX_DMA_ADDR 0xB4004000 | |
835 | #define MAC1_TX_DMA_ADDR 0xB4004200 | |
836 | /* offsets from MAC_TX_RING_ADDR address */ | |
837 | #define MAC_TX_BUFF0_STATUS 0x0 | |
838 | #define TX_FRAME_ABORTED (1<<0) | |
839 | #define TX_JAB_TIMEOUT (1<<1) | |
840 | #define TX_NO_CARRIER (1<<2) | |
841 | #define TX_LOSS_CARRIER (1<<3) | |
842 | #define TX_EXC_DEF (1<<4) | |
843 | #define TX_LATE_COLL_ABORT (1<<5) | |
844 | #define TX_EXC_COLL (1<<6) | |
845 | #define TX_UNDERRUN (1<<7) | |
846 | #define TX_DEFERRED (1<<8) | |
847 | #define TX_LATE_COLL (1<<9) | |
848 | #define TX_COLL_CNT_MASK (0xF<<10) | |
849 | #define TX_PKT_RETRY (1<<31) | |
850 | #define MAC_TX_BUFF0_ADDR 0x4 | |
851 | #define TX_DMA_ENABLE (1<<0) | |
852 | #define TX_T_DONE (1<<1) | |
853 | #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) | |
854 | #define MAC_TX_BUFF0_LEN 0x8 | |
855 | #define MAC_TX_BUFF1_STATUS 0x10 | |
856 | #define MAC_TX_BUFF1_ADDR 0x14 | |
857 | #define MAC_TX_BUFF1_LEN 0x18 | |
858 | #define MAC_TX_BUFF2_STATUS 0x20 | |
859 | #define MAC_TX_BUFF2_ADDR 0x24 | |
860 | #define MAC_TX_BUFF2_LEN 0x28 | |
861 | #define MAC_TX_BUFF3_STATUS 0x30 | |
862 | #define MAC_TX_BUFF3_ADDR 0x34 | |
863 | #define MAC_TX_BUFF3_LEN 0x38 | |
864 | ||
865 | #define MAC0_RX_DMA_ADDR 0xB4004100 | |
866 | #define MAC1_RX_DMA_ADDR 0xB4004300 | |
867 | /* offsets from MAC_RX_RING_ADDR */ | |
868 | #define MAC_RX_BUFF0_STATUS 0x0 | |
869 | #define RX_FRAME_LEN_MASK 0x3fff | |
870 | #define RX_WDOG_TIMER (1<<14) | |
871 | #define RX_RUNT (1<<15) | |
872 | #define RX_OVERLEN (1<<16) | |
873 | #define RX_COLL (1<<17) | |
874 | #define RX_ETHER (1<<18) | |
875 | #define RX_MII_ERROR (1<<19) | |
876 | #define RX_DRIBBLING (1<<20) | |
877 | #define RX_CRC_ERROR (1<<21) | |
878 | #define RX_VLAN1 (1<<22) | |
879 | #define RX_VLAN2 (1<<23) | |
880 | #define RX_LEN_ERROR (1<<24) | |
881 | #define RX_CNTRL_FRAME (1<<25) | |
882 | #define RX_U_CNTRL_FRAME (1<<26) | |
883 | #define RX_MCAST_FRAME (1<<27) | |
884 | #define RX_BCAST_FRAME (1<<28) | |
885 | #define RX_FILTER_FAIL (1<<29) | |
886 | #define RX_PACKET_FILTER (1<<30) | |
887 | #define RX_MISSED_FRAME (1<<31) | |
888 | ||
889 | #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | |
890 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ | |
891 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | |
892 | #define MAC_RX_BUFF0_ADDR 0x4 | |
893 | #define RX_DMA_ENABLE (1<<0) | |
894 | #define RX_T_DONE (1<<1) | |
895 | #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) | |
896 | #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) | |
897 | #define MAC_RX_BUFF1_STATUS 0x10 | |
898 | #define MAC_RX_BUFF1_ADDR 0x14 | |
899 | #define MAC_RX_BUFF2_STATUS 0x20 | |
900 | #define MAC_RX_BUFF2_ADDR 0x24 | |
901 | #define MAC_RX_BUFF3_STATUS 0x30 | |
902 | #define MAC_RX_BUFF3_ADDR 0x34 | |
903 | ||
904 | ||
905 | /* UARTS 0-3 */ | |
906 | #define UART_BASE UART0_ADDR | |
907 | #define UART_DEBUG_BASE UART3_ADDR | |
908 | ||
909 | #define UART_RX 0 /* Receive buffer */ | |
910 | #define UART_TX 4 /* Transmit buffer */ | |
911 | #define UART_IER 8 /* Interrupt Enable Register */ | |
912 | #define UART_IIR 0xC /* Interrupt ID Register */ | |
913 | #define UART_FCR 0x10 /* FIFO Control Register */ | |
914 | #define UART_LCR 0x14 /* Line Control Register */ | |
915 | #define UART_MCR 0x18 /* Modem Control Register */ | |
916 | #define UART_LSR 0x1C /* Line Status Register */ | |
917 | #define UART_MSR 0x20 /* Modem Status Register */ | |
918 | #define UART_CLK 0x28 /* Baud Rate Clock Divider */ | |
919 | #define UART_MOD_CNTRL 0x100 /* Module Control */ | |
920 | ||
921 | #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ | |
922 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ | |
923 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ | |
924 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ | |
925 | #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ | |
926 | #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ | |
927 | #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ | |
928 | #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ | |
929 | #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ | |
930 | #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ | |
931 | #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ | |
932 | #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ | |
933 | #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ | |
934 | ||
935 | /* | |
936 | * These are the definitions for the Line Control Register | |
937 | */ | |
938 | #define UART_LCR_SBC 0x40 /* Set break control */ | |
939 | #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ | |
940 | #define UART_LCR_EPAR 0x10 /* Even parity select */ | |
941 | #define UART_LCR_PARITY 0x08 /* Parity Enable */ | |
942 | #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ | |
943 | #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ | |
944 | #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ | |
945 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ | |
946 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ | |
947 | ||
948 | /* | |
949 | * These are the definitions for the Line Status Register | |
950 | */ | |
951 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
952 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
953 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
954 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
955 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
956 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
957 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
958 | ||
959 | /* | |
960 | * These are the definitions for the Interrupt Identification Register | |
961 | */ | |
962 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
963 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
964 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
965 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
966 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
967 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
968 | ||
969 | /* | |
970 | * These are the definitions for the Interrupt Enable Register | |
971 | */ | |
972 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
973 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
974 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
975 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
976 | ||
977 | /* | |
978 | * These are the definitions for the Modem Control Register | |
979 | */ | |
980 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
981 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
982 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
983 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
984 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
985 | ||
986 | /* | |
987 | * These are the definitions for the Modem Status Register | |
988 | */ | |
989 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
990 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
991 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
992 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
993 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
994 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
995 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
996 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
997 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
998 | ||
999 | ||
1000 | ||
1001 | /* SSIO */ | |
1002 | #define SSI0_STATUS 0xB1600000 | |
1003 | #define SSI_STATUS_BF (1<<4) | |
1004 | #define SSI_STATUS_OF (1<<3) | |
1005 | #define SSI_STATUS_UF (1<<2) | |
1006 | #define SSI_STATUS_D (1<<1) | |
1007 | #define SSI_STATUS_B (1<<0) | |
1008 | #define SSI0_INT 0xB1600004 | |
1009 | #define SSI_INT_OI (1<<3) | |
1010 | #define SSI_INT_UI (1<<2) | |
1011 | #define SSI_INT_DI (1<<1) | |
1012 | #define SSI0_INT_ENABLE 0xB1600008 | |
1013 | #define SSI_INTE_OIE (1<<3) | |
1014 | #define SSI_INTE_UIE (1<<2) | |
1015 | #define SSI_INTE_DIE (1<<1) | |
1016 | #define SSI0_CONFIG 0xB1600020 | |
1017 | #define SSI_CONFIG_AO (1<<24) | |
1018 | #define SSI_CONFIG_DO (1<<23) | |
1019 | #define SSI_CONFIG_ALEN_BIT 20 | |
1020 | #define SSI_CONFIG_ALEN_MASK (0x7<<20) | |
1021 | #define SSI_CONFIG_DLEN_BIT 16 | |
1022 | #define SSI_CONFIG_DLEN_MASK (0x7<<16) | |
1023 | #define SSI_CONFIG_DD (1<<11) | |
1024 | #define SSI_CONFIG_AD (1<<10) | |
1025 | #define SSI_CONFIG_BM_BIT 8 | |
1026 | #define SSI_CONFIG_BM_MASK (0x3<<8) | |
1027 | #define SSI_CONFIG_CE (1<<7) | |
1028 | #define SSI_CONFIG_DP (1<<6) | |
1029 | #define SSI_CONFIG_DL (1<<5) | |
1030 | #define SSI_CONFIG_EP (1<<4) | |
1031 | #define SSI0_ADATA 0xB1600024 | |
1032 | #define SSI_AD_D (1<<24) | |
1033 | #define SSI_AD_ADDR_BIT 16 | |
1034 | #define SSI_AD_ADDR_MASK (0xff<<16) | |
1035 | #define SSI_AD_DATA_BIT 0 | |
1036 | #define SSI_AD_DATA_MASK (0xfff<<0) | |
1037 | #define SSI0_CLKDIV 0xB1600028 | |
1038 | #define SSI0_CONTROL 0xB1600100 | |
1039 | #define SSI_CONTROL_CD (1<<1) | |
1040 | #define SSI_CONTROL_E (1<<0) | |
1041 | ||
1042 | /* SSI1 */ | |
1043 | #define SSI1_STATUS 0xB1680000 | |
1044 | #define SSI1_INT 0xB1680004 | |
1045 | #define SSI1_INT_ENABLE 0xB1680008 | |
1046 | #define SSI1_CONFIG 0xB1680020 | |
1047 | #define SSI1_ADATA 0xB1680024 | |
1048 | #define SSI1_CLKDIV 0xB1680028 | |
1049 | #define SSI1_ENABLE 0xB1680100 | |
1050 | ||
1051 | /* | |
1052 | * Register content definitions | |
1053 | */ | |
1054 | #define SSI_STATUS_BF (1<<4) | |
1055 | #define SSI_STATUS_OF (1<<3) | |
1056 | #define SSI_STATUS_UF (1<<2) | |
1057 | #define SSI_STATUS_D (1<<1) | |
1058 | #define SSI_STATUS_B (1<<0) | |
1059 | ||
1060 | /* SSI_INT */ | |
1061 | #define SSI_INT_OI (1<<3) | |
1062 | #define SSI_INT_UI (1<<2) | |
1063 | #define SSI_INT_DI (1<<1) | |
1064 | ||
1065 | /* SSI_INTEN */ | |
1066 | #define SSI_INTEN_OIE (1<<3) | |
1067 | #define SSI_INTEN_UIE (1<<2) | |
1068 | #define SSI_INTEN_DIE (1<<1) | |
1069 | ||
1070 | #define SSI_CONFIG_AO (1<<24) | |
1071 | #define SSI_CONFIG_DO (1<<23) | |
1072 | #define SSI_CONFIG_ALEN (7<<20) | |
1073 | #define SSI_CONFIG_DLEN (15<<16) | |
1074 | #define SSI_CONFIG_DD (1<<11) | |
1075 | #define SSI_CONFIG_AD (1<<10) | |
1076 | #define SSI_CONFIG_BM (3<<8) | |
1077 | #define SSI_CONFIG_CE (1<<7) | |
1078 | #define SSI_CONFIG_DP (1<<6) | |
1079 | #define SSI_CONFIG_DL (1<<5) | |
1080 | #define SSI_CONFIG_EP (1<<4) | |
1081 | #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) | |
1082 | #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) | |
1083 | #define SSI_CONFIG_BM_HI (0<<8) | |
1084 | #define SSI_CONFIG_BM_LO (1<<8) | |
1085 | #define SSI_CONFIG_BM_CY (2<<8) | |
1086 | ||
1087 | #define SSI_ADATA_D (1<<24) | |
1088 | #define SSI_ADATA_ADDR (0xFF<<16) | |
1089 | #define SSI_ADATA_DATA (0x0FFF) | |
1090 | #define SSI_ADATA_ADDR_N(N) (N<<16) | |
1091 | ||
1092 | #define SSI_ENABLE_CD (1<<1) | |
1093 | #define SSI_ENABLE_E (1<<0) | |
1094 | ||
1095 | ||
1096 | /* IrDA Controller */ | |
1097 | #define IRDA_BASE 0xB0300000 | |
1098 | #define IR_RING_PTR_STATUS (IRDA_BASE+0x00) | |
1099 | #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) | |
1100 | #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) | |
1101 | #define IR_RING_SIZE (IRDA_BASE+0x0C) | |
1102 | #define IR_RING_PROMPT (IRDA_BASE+0x10) | |
1103 | #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) | |
1104 | #define IR_INT_CLEAR (IRDA_BASE+0x18) | |
1105 | #define IR_CONFIG_1 (IRDA_BASE+0x20) | |
1106 | #define IR_RX_INVERT_LED (1<<0) | |
1107 | #define IR_TX_INVERT_LED (1<<1) | |
1108 | #define IR_ST (1<<2) | |
1109 | #define IR_SF (1<<3) | |
1110 | #define IR_SIR (1<<4) | |
1111 | #define IR_MIR (1<<5) | |
1112 | #define IR_FIR (1<<6) | |
1113 | #define IR_16CRC (1<<7) | |
1114 | #define IR_TD (1<<8) | |
1115 | #define IR_RX_ALL (1<<9) | |
1116 | #define IR_DMA_ENABLE (1<<10) | |
1117 | #define IR_RX_ENABLE (1<<11) | |
1118 | #define IR_TX_ENABLE (1<<12) | |
1119 | #define IR_LOOPBACK (1<<14) | |
1120 | #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ | |
1121 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) | |
1122 | #define IR_SIR_FLAGS (IRDA_BASE+0x24) | |
1123 | #define IR_ENABLE (IRDA_BASE+0x28) | |
1124 | #define IR_RX_STATUS (1<<9) | |
1125 | #define IR_TX_STATUS (1<<10) | |
1126 | #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) | |
1127 | #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) | |
1128 | #define IR_MAX_PKT_LEN (IRDA_BASE+0x34) | |
1129 | #define IR_RX_BYTE_CNT (IRDA_BASE+0x38) | |
1130 | #define IR_CONFIG_2 (IRDA_BASE+0x3C) | |
1131 | #define IR_MODE_INV (1<<0) | |
1132 | #define IR_ONE_PIN (1<<1) | |
1133 | #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) | |
1134 | ||
1135 | /* GPIO */ | |
1136 | #define SYS_PINFUNC 0xB190002C | |
1137 | #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ | |
1138 | #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ | |
1139 | #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ | |
1140 | #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ | |
1141 | #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ | |
1142 | #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ | |
1143 | #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ | |
1144 | #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ | |
1145 | #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ | |
1146 | #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ | |
1147 | #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ | |
1148 | #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ | |
1149 | #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ | |
1150 | #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ | |
1151 | #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ | |
1152 | #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ | |
1153 | ||
1154 | /* Au1100 Only */ | |
1155 | #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ | |
1156 | #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ | |
1157 | #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ | |
1158 | #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ | |
1159 | ||
1160 | /* Au1550 Only. Redefines lots of pins */ | |
1161 | #define SYS_PF_PSC2_MASK (7 << 17) | |
1162 | #define SYS_PF_PSC2_AC97 (0) | |
1163 | #define SYS_PF_PSC2_SPI (0) | |
1164 | #define SYS_PF_PSC2_I2S (1 << 17) | |
1165 | #define SYS_PF_PSC2_SMBUS (3 << 17) | |
1166 | #define SYS_PF_PSC2_GPIO (7 << 17) | |
1167 | #define SYS_PF_PSC3_MASK (7 << 20) | |
1168 | #define SYS_PF_PSC3_AC97 (0) | |
1169 | #define SYS_PF_PSC3_SPI (0) | |
1170 | #define SYS_PF_PSC3_I2S (1 << 20) | |
1171 | #define SYS_PF_PSC3_SMBUS (3 << 20) | |
1172 | #define SYS_PF_PSC3_GPIO (7 << 20) | |
1173 | #define SYS_PF_PSC1_S1 (1 << 1) | |
1174 | #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | |
1175 | ||
1176 | #define SYS_TRIOUTRD 0xB1900100 | |
1177 | #define SYS_TRIOUTCLR 0xB1900100 | |
1178 | #define SYS_OUTPUTRD 0xB1900108 | |
1179 | #define SYS_OUTPUTSET 0xB1900108 | |
1180 | #define SYS_OUTPUTCLR 0xB190010C | |
1181 | #define SYS_PINSTATERD 0xB1900110 | |
1182 | #define SYS_PININPUTEN 0xB1900110 | |
1183 | ||
1184 | /* GPIO2, Au1500, Au1550 only */ | |
1185 | #define GPIO2_BASE 0xB1700000 | |
1186 | #define GPIO2_DIR (GPIO2_BASE + 0) | |
1187 | #define GPIO2_OUTPUT (GPIO2_BASE + 8) | |
1188 | #define GPIO2_PINSTATE (GPIO2_BASE + 0xC) | |
1189 | #define GPIO2_INTENABLE (GPIO2_BASE + 0x10) | |
1190 | #define GPIO2_ENABLE (GPIO2_BASE + 0x14) | |
1191 | ||
1192 | /* Power Management */ | |
1193 | #define SYS_SCRATCH0 0xB1900018 | |
1194 | #define SYS_SCRATCH1 0xB190001C | |
1195 | #define SYS_WAKEMSK 0xB1900034 | |
1196 | #define SYS_ENDIAN 0xB1900038 | |
1197 | #define SYS_POWERCTRL 0xB190003C | |
1198 | #define SYS_WAKESRC 0xB190005C | |
1199 | #define SYS_SLPPWR 0xB1900078 | |
1200 | #define SYS_SLEEP 0xB190007C | |
1201 | ||
1202 | /* Clock Controller */ | |
1203 | #define SYS_FREQCTRL0 0xB1900020 | |
1204 | #define SYS_FC_FRDIV2_BIT 22 | |
1205 | #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) | |
1206 | #define SYS_FC_FE2 (1<<21) | |
1207 | #define SYS_FC_FS2 (1<<20) | |
1208 | #define SYS_FC_FRDIV1_BIT 12 | |
1209 | #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) | |
1210 | #define SYS_FC_FE1 (1<<11) | |
1211 | #define SYS_FC_FS1 (1<<10) | |
1212 | #define SYS_FC_FRDIV0_BIT 2 | |
1213 | #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) | |
1214 | #define SYS_FC_FE0 (1<<1) | |
1215 | #define SYS_FC_FS0 (1<<0) | |
1216 | #define SYS_FREQCTRL1 0xB1900024 | |
1217 | #define SYS_FC_FRDIV5_BIT 22 | |
1218 | #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) | |
1219 | #define SYS_FC_FE5 (1<<21) | |
1220 | #define SYS_FC_FS5 (1<<20) | |
1221 | #define SYS_FC_FRDIV4_BIT 12 | |
1222 | #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) | |
1223 | #define SYS_FC_FE4 (1<<11) | |
1224 | #define SYS_FC_FS4 (1<<10) | |
1225 | #define SYS_FC_FRDIV3_BIT 2 | |
1226 | #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) | |
1227 | #define SYS_FC_FE3 (1<<1) | |
1228 | #define SYS_FC_FS3 (1<<0) | |
1229 | #define SYS_CLKSRC 0xB1900028 | |
1230 | #define SYS_CS_ME1_BIT 27 | |
1231 | #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) | |
1232 | #define SYS_CS_DE1 (1<<26) | |
1233 | #define SYS_CS_CE1 (1<<25) | |
1234 | #define SYS_CS_ME0_BIT 22 | |
1235 | #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) | |
1236 | #define SYS_CS_DE0 (1<<21) | |
1237 | #define SYS_CS_CE0 (1<<20) | |
1238 | #define SYS_CS_MI2_BIT 17 | |
1239 | #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) | |
1240 | #define SYS_CS_DI2 (1<<16) | |
1241 | #define SYS_CS_CI2 (1<<15) | |
1242 | #define SYS_CS_MUH_BIT 12 | |
1243 | #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) | |
1244 | #define SYS_CS_DUH (1<<11) | |
1245 | #define SYS_CS_CUH (1<<10) | |
1246 | #define SYS_CS_MUD_BIT 7 | |
1247 | #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) | |
1248 | #define SYS_CS_DUD (1<<6) | |
1249 | #define SYS_CS_CUD (1<<5) | |
1250 | #define SYS_CS_MIR_BIT 2 | |
1251 | #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) | |
1252 | #define SYS_CS_DIR (1<<1) | |
1253 | #define SYS_CS_CIR (1<<0) | |
1254 | ||
1255 | #define SYS_CS_MUX_AUX 0x1 | |
1256 | #define SYS_CS_MUX_FQ0 0x2 | |
1257 | #define SYS_CS_MUX_FQ1 0x3 | |
1258 | #define SYS_CS_MUX_FQ2 0x4 | |
1259 | #define SYS_CS_MUX_FQ3 0x5 | |
1260 | #define SYS_CS_MUX_FQ4 0x6 | |
1261 | #define SYS_CS_MUX_FQ5 0x7 | |
1262 | #define SYS_CPUPLL 0xB1900060 | |
1263 | #define SYS_AUXPLL 0xB1900064 | |
1264 | ||
1265 | /* AC97 Controller */ | |
1266 | #define AC97C_CONFIG 0xB0000000 | |
1267 | #define AC97C_RECV_SLOTS_BIT 13 | |
1268 | #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) | |
1269 | #define AC97C_XMIT_SLOTS_BIT 3 | |
1270 | #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) | |
1271 | #define AC97C_SG (1<<2) | |
1272 | #define AC97C_SYNC (1<<1) | |
1273 | #define AC97C_RESET (1<<0) | |
1274 | #define AC97C_STATUS 0xB0000004 | |
1275 | #define AC97C_XU (1<<11) | |
1276 | #define AC97C_XO (1<<10) | |
1277 | #define AC97C_RU (1<<9) | |
1278 | #define AC97C_RO (1<<8) | |
1279 | #define AC97C_READY (1<<7) | |
1280 | #define AC97C_CP (1<<6) | |
1281 | #define AC97C_TR (1<<5) | |
1282 | #define AC97C_TE (1<<4) | |
1283 | #define AC97C_TF (1<<3) | |
1284 | #define AC97C_RR (1<<2) | |
1285 | #define AC97C_RE (1<<1) | |
1286 | #define AC97C_RF (1<<0) | |
1287 | #define AC97C_DATA 0xB0000008 | |
1288 | #define AC97C_CMD 0xB000000C | |
1289 | #define AC97C_WD_BIT 16 | |
1290 | #define AC97C_READ (1<<7) | |
1291 | #define AC97C_INDEX_MASK 0x7f | |
1292 | #define AC97C_CNTRL 0xB0000010 | |
1293 | #define AC97C_RS (1<<1) | |
1294 | #define AC97C_CE (1<<0) | |
1295 | ||
1296 | ||
1297 | /* Secure Digital (SD) Controller */ | |
1298 | #define SD0_XMIT_FIFO 0xB0600000 | |
1299 | #define SD0_RECV_FIFO 0xB0600004 | |
1300 | #define SD1_XMIT_FIFO 0xB0680000 | |
1301 | #define SD1_RECV_FIFO 0xB0680004 | |
1302 | ||
1303 | ||
1304 | #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) | |
1305 | /* Au1500 PCI Controller */ | |
1306 | #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr | |
1307 | #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) | |
1308 | #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) | |
1309 | #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) | |
1310 | #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) | |
1311 | #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) | |
1312 | #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) | |
1313 | #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) | |
1314 | #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) | |
1315 | #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) | |
1316 | #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) | |
1317 | #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) | |
1318 | #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) | |
1319 | #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) | |
1320 | #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) | |
1321 | #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) | |
1322 | ||
1323 | #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr | |
1324 | ||
1325 | /* All of our structures, like pci resource, have 32 bit members. | |
1326 | * Drivers are expected to do an ioremap on the PCI MEM resource, but it's | |
1327 | * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch | |
1328 | * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and | |
1329 | * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM | |
1330 | * addresses. For PCI IO, it's simpler because we get to do the ioremap | |
1331 | * ourselves and then adjust the device's resources. | |
1332 | */ | |
1333 | #define Au1500_EXT_CFG 0x600000000ULL | |
1334 | #define Au1500_EXT_CFG_TYPE1 0x680000000ULL | |
1335 | #define Au1500_PCI_IO_START 0x500000000ULL | |
1336 | #define Au1500_PCI_IO_END 0x5000FFFFFULL | |
1337 | #define Au1500_PCI_MEM_START 0x440000000ULL | |
1338 | #define Au1500_PCI_MEM_END 0x44FFFFFFFULL | |
1339 | ||
1340 | #define PCI_IO_START (Au1500_PCI_IO_START + 0x1000) | |
1341 | #define PCI_IO_END (Au1500_PCI_IO_END) | |
1342 | #define PCI_MEM_START (Au1500_PCI_MEM_START) | |
1343 | #define PCI_MEM_END (Au1500_PCI_MEM_END) | |
1344 | #define PCI_FIRST_DEVFN (0<<3) | |
1345 | #define PCI_LAST_DEVFN (19<<3) | |
1346 | ||
1347 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ | |
1348 | #define IOPORT_RESOURCE_END 0xffffffff | |
1349 | #define IOMEM_RESOURCE_START 0x10000000 | |
1350 | #define IOMEM_RESOURCE_END 0xffffffff | |
1351 | ||
1352 | /* | |
1353 | * Borrowed from the PPC arch: | |
1354 | * The following macro is used to lookup irqs in a standard table | |
1355 | * format for those PPC systems that do not already have PCI | |
1356 | * interrupts properly routed. | |
1357 | */ | |
1358 | /* FIXME - double check this from asm-ppc/pci-bridge.h */ | |
1359 | #define PCI_IRQ_TABLE_LOOKUP \ | |
1360 | ({ long _ctl_ = -1; \ | |
1361 | if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ | |
1362 | _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ | |
1363 | _ctl_; }) | |
1364 | ||
1365 | ||
1366 | #else /* Au1000 and Au1100 */ | |
1367 | ||
1368 | /* don't allow any legacy ports probing */ | |
1369 | #define IOPORT_RESOURCE_START 0x10000000; | |
1370 | #define IOPORT_RESOURCE_END 0xffffffff | |
1371 | #define IOMEM_RESOURCE_START 0x10000000 | |
1372 | #define IOMEM_RESOURCE_END 0xffffffff | |
1373 | ||
1374 | #ifdef CONFIG_MIPS_PB1000 | |
1375 | #define PCI_IO_START 0x10000000 | |
1376 | #define PCI_IO_END 0x1000ffff | |
1377 | #define PCI_MEM_START 0x18000000 | |
1378 | #define PCI_MEM_END 0x18ffffff | |
1379 | #define PCI_FIRST_DEVFN 0 | |
1380 | #define PCI_LAST_DEVFN 1 | |
1381 | #else | |
1382 | /* no PCI bus controller */ | |
1383 | #define PCI_IO_START 0 | |
1384 | #define PCI_IO_END 0 | |
1385 | #define PCI_MEM_START 0 | |
42a3b4f2 | 1386 | #define PCI_MEM_END 0 |
1da177e4 LT |
1387 | #define PCI_FIRST_DEVFN 0 |
1388 | #define PCI_LAST_DEVFN 0 | |
1389 | #endif | |
1390 | ||
1391 | #endif | |
1392 | ||
1393 | /* Processor information base on prid. | |
1394 | * Copied from PowerPC. | |
1395 | */ | |
1396 | struct cpu_spec { | |
1397 | /* CPU is matched via (PRID & prid_mask) == prid_value */ | |
1398 | unsigned int prid_mask; | |
1399 | unsigned int prid_value; | |
1400 | ||
1401 | char *cpu_name; | |
1402 | unsigned char cpu_od; /* Set Config[OD] */ | |
1403 | unsigned char cpu_bclk; /* Enable BCLK switching */ | |
1404 | }; | |
1405 | ||
1406 | extern struct cpu_spec cpu_specs[]; | |
1407 | extern struct cpu_spec *cur_cpu_spec[]; | |
1408 | #endif |