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07119621 RB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org) | |
7 | */ | |
8 | #ifndef __ASM_QEMU_H | |
9 | #define __ASM_QEMU_H | |
10 | ||
11 | /* | |
12 | * Interrupt numbers | |
13 | */ | |
14 | #define Q_PIC_IRQ_BASE 0 | |
7bcf7717 | 15 | #define Q_COUNT_COMPARE_IRQ 23 |
07119621 RB |
16 | |
17 | /* | |
18 | * Qemu clock rate. Unlike on real MIPS this has no relation to the | |
19 | * instruction issue rate, so the choosen value is pure fiction, just needs | |
20 | * to match the value in Qemu itself. | |
21 | */ | |
22 | #define QEMU_C0_COUNTER_CLOCK 100000000 | |
23 | ||
c583122c TS |
24 | /* |
25 | * Magic qemu system control location. | |
26 | */ | |
27 | #define QEMU_RESTART_REG 0xBFBF0000 | |
28 | #define QEMU_HALT_REG 0xBFBF0004 | |
29 | ||
07119621 | 30 | #endif /* __ASM_QEMU_H */ |