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1da177e4 LT |
1 | /* ********************************************************************* |
2 | * SB1250 Board Support Package | |
42a3b4f2 | 3 | * |
1da177e4 | 4 | * UART Constants File: sb1250_uart.h |
42a3b4f2 RB |
5 | * |
6 | * This module contains constants and macros useful for | |
1da177e4 LT |
7 | * manipulating the SB1250's UARTs |
8 | * | |
9 | * SB1250 specification level: User's manual 1/02/02 | |
42a3b4f2 | 10 | * |
1da177e4 | 11 | * Author: Mitch Lichtenberg |
42a3b4f2 RB |
12 | * |
13 | ********************************************************************* | |
1da177e4 LT |
14 | * |
15 | * Copyright 2000,2001,2002,2003 | |
16 | * Broadcom Corporation. All rights reserved. | |
42a3b4f2 RB |
17 | * |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License as | |
20 | * published by the Free Software Foundation; either version 2 of | |
1da177e4 LT |
21 | * the License, or (at your option) any later version. |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
42a3b4f2 | 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
1da177e4 LT |
31 | * MA 02111-1307 USA |
32 | ********************************************************************* */ | |
33 | ||
34 | ||
35 | #ifndef _SB1250_UART_H | |
36 | #define _SB1250_UART_H | |
37 | ||
38 | #include "sb1250_defs.h" | |
39 | ||
42a3b4f2 | 40 | /* ********************************************************************** |
1da177e4 LT |
41 | * DUART Registers |
42 | ********************************************************************** */ | |
43 | ||
44 | /* | |
45 | * DUART Mode Register #1 (Table 10-3) | |
46 | * Register: DUART_MODE_REG_1_A | |
47 | * Register: DUART_MODE_REG_1_B | |
48 | */ | |
49 | ||
50 | #define S_DUART_BITS_PER_CHAR 0 | |
51 | #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) | |
52 | #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) | |
53 | ||
54 | #define K_DUART_BITS_PER_CHAR_RSV0 0 | |
55 | #define K_DUART_BITS_PER_CHAR_RSV1 1 | |
56 | #define K_DUART_BITS_PER_CHAR_7 2 | |
57 | #define K_DUART_BITS_PER_CHAR_8 3 | |
58 | ||
59 | #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) | |
60 | #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) | |
61 | #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) | |
62 | #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) | |
63 | ||
64 | ||
65 | #define M_DUART_PARITY_TYPE_EVEN 0x00 | |
66 | #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) | |
67 | ||
68 | #define S_DUART_PARITY_MODE 3 | |
69 | #define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) | |
70 | #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) | |
71 | ||
72 | #define K_DUART_PARITY_MODE_ADD 0 | |
73 | #define K_DUART_PARITY_MODE_ADD_FIXED 1 | |
74 | #define K_DUART_PARITY_MODE_NONE 2 | |
75 | ||
76 | #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) | |
77 | #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) | |
78 | #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) | |
79 | ||
80 | #define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ | |
81 | ||
82 | #define M_DUART_RX_IRQ_SEL_RXRDY 0 | |
83 | #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) | |
84 | ||
85 | #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) | |
86 | ||
87 | /* | |
88 | * DUART Mode Register #2 (Table 10-4) | |
89 | * Register: DUART_MODE_REG_2_A | |
90 | * Register: DUART_MODE_REG_2_B | |
91 | */ | |
92 | ||
93 | #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ | |
94 | ||
95 | #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) | |
96 | #define M_DUART_STOP_BIT_LEN_1 0 | |
97 | ||
98 | #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) | |
99 | ||
100 | ||
101 | #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ | |
102 | ||
103 | #define S_DUART_CHAN_MODE 6 | |
104 | #define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) | |
105 | #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) | |
106 | ||
107 | #define K_DUART_CHAN_MODE_NORMAL 0 | |
108 | #define K_DUART_CHAN_MODE_LCL_LOOP 2 | |
109 | #define K_DUART_CHAN_MODE_REM_LOOP 3 | |
110 | ||
111 | #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) | |
112 | #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) | |
113 | #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) | |
114 | ||
115 | /* | |
116 | * DUART Command Register (Table 10-5) | |
117 | * Register: DUART_CMD_A | |
118 | * Register: DUART_CMD_B | |
119 | */ | |
120 | ||
121 | #define M_DUART_RX_EN _SB_MAKEMASK1(0) | |
122 | #define M_DUART_RX_DIS _SB_MAKEMASK1(1) | |
123 | #define M_DUART_TX_EN _SB_MAKEMASK1(2) | |
124 | #define M_DUART_TX_DIS _SB_MAKEMASK1(3) | |
125 | ||
126 | #define S_DUART_MISC_CMD 4 | |
127 | #define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) | |
128 | #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) | |
129 | ||
130 | #define K_DUART_MISC_CMD_NOACTION0 0 | |
131 | #define K_DUART_MISC_CMD_NOACTION1 1 | |
132 | #define K_DUART_MISC_CMD_RESET_RX 2 | |
133 | #define K_DUART_MISC_CMD_RESET_TX 3 | |
134 | #define K_DUART_MISC_CMD_NOACTION4 4 | |
135 | #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 | |
136 | #define K_DUART_MISC_CMD_START_BREAK 6 | |
137 | #define K_DUART_MISC_CMD_STOP_BREAK 7 | |
138 | ||
139 | #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) | |
140 | #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) | |
141 | #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) | |
142 | #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) | |
143 | #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) | |
144 | #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) | |
145 | #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) | |
146 | #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) | |
147 | ||
42a3b4f2 | 148 | #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) |
1da177e4 LT |
149 | |
150 | /* | |
151 | * DUART Status Register (Table 10-6) | |
152 | * Register: DUART_STATUS_A | |
153 | * Register: DUART_STATUS_B | |
154 | * READ-ONLY | |
155 | */ | |
156 | ||
157 | #define M_DUART_RX_RDY _SB_MAKEMASK1(0) | |
158 | #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) | |
159 | #define M_DUART_TX_RDY _SB_MAKEMASK1(2) | |
160 | #define M_DUART_TX_EMT _SB_MAKEMASK1(3) | |
161 | #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) | |
162 | #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) | |
163 | #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) | |
164 | #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) | |
165 | ||
166 | /* | |
167 | * DUART Baud Rate Register (Table 10-7) | |
42a3b4f2 | 168 | * Register: DUART_CLK_SEL_A |
1da177e4 LT |
169 | * Register: DUART_CLK_SEL_B |
170 | */ | |
171 | ||
172 | #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) | |
173 | #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) | |
174 | ||
175 | /* | |
176 | * DUART Data Registers (Table 10-8 and 10-9) | |
177 | * Register: DUART_RX_HOLD_A | |
178 | * Register: DUART_RX_HOLD_B | |
179 | * Register: DUART_TX_HOLD_A | |
180 | * Register: DUART_TX_HOLD_B | |
181 | */ | |
182 | ||
183 | #define M_DUART_RX_DATA _SB_MAKEMASK(8,0) | |
184 | #define M_DUART_TX_DATA _SB_MAKEMASK(8,0) | |
185 | ||
186 | /* | |
187 | * DUART Input Port Register (Table 10-10) | |
188 | * Register: DUART_IN_PORT | |
189 | */ | |
190 | ||
191 | #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) | |
192 | #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) | |
193 | #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) | |
194 | #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) | |
195 | #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) | |
196 | #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) | |
197 | #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) | |
198 | #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) | |
199 | ||
200 | /* | |
201 | * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) | |
202 | * Register: DUART_INPORT_CHNG | |
203 | */ | |
204 | ||
205 | #define S_DUART_IN_PIN_VAL 0 | |
206 | #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) | |
207 | ||
208 | #define S_DUART_IN_PIN_CHNG 4 | |
209 | #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) | |
210 | ||
211 | ||
212 | /* | |
213 | * DUART Output port control register (Table 10-14) | |
214 | * Register: DUART_OPCR | |
215 | */ | |
216 | ||
217 | #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ | |
218 | #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) | |
219 | #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ | |
220 | #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) | |
221 | #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ | |
222 | ||
223 | /* | |
224 | * DUART Aux Control Register (Table 10-15) | |
225 | * Register: DUART_AUX_CTRL | |
226 | */ | |
227 | ||
228 | #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) | |
229 | #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) | |
230 | #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) | |
231 | #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) | |
232 | #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) | |
233 | ||
234 | #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) | |
235 | #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) | |
236 | ||
237 | /* | |
238 | * DUART Interrupt Status Register (Table 10-16) | |
239 | * Register: DUART_ISR | |
240 | */ | |
241 | ||
242 | #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) | |
243 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) | |
244 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) | |
245 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) | |
246 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) | |
247 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) | |
248 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) | |
249 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) | |
250 | ||
251 | /* | |
252 | * DUART Channel A Interrupt Status Register (Table 10-17) | |
253 | * DUART Channel B Interrupt Status Register (Table 10-18) | |
254 | * Register: DUART_ISR_A | |
255 | * Register: DUART_ISR_B | |
256 | */ | |
257 | ||
258 | #define M_DUART_ISR_TX _SB_MAKEMASK1(0) | |
259 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) | |
260 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) | |
261 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) | |
262 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) | |
263 | ||
264 | /* | |
265 | * DUART Interrupt Mask Register (Table 10-19) | |
266 | * Register: DUART_IMR | |
267 | */ | |
268 | ||
269 | #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) | |
270 | #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) | |
271 | #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) | |
272 | #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) | |
273 | #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) | |
274 | ||
275 | #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) | |
276 | #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) | |
277 | #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) | |
278 | #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) | |
279 | #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) | |
280 | ||
281 | /* | |
282 | * DUART Channel A Interrupt Mask Register (Table 10-20) | |
283 | * DUART Channel B Interrupt Mask Register (Table 10-21) | |
284 | * Register: DUART_IMR_A | |
285 | * Register: DUART_IMR_B | |
286 | */ | |
287 | ||
288 | #define M_DUART_IMR_TX _SB_MAKEMASK1(0) | |
289 | #define M_DUART_IMR_RX _SB_MAKEMASK1(1) | |
290 | #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) | |
291 | #define M_DUART_IMR_IN _SB_MAKEMASK1(3) | |
292 | #define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) | |
293 | #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) | |
294 | ||
295 | ||
296 | /* | |
297 | * DUART Output Port Set Register (Table 10-22) | |
298 | * Register: DUART_SET_OPR | |
299 | */ | |
300 | ||
301 | #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) | |
302 | #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) | |
303 | #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) | |
304 | #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) | |
305 | #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) | |
306 | ||
307 | /* | |
308 | * DUART Output Port Clear Register (Table 10-23) | |
309 | * Register: DUART_CLEAR_OPR | |
310 | */ | |
311 | ||
312 | #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) | |
313 | #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) | |
314 | #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) | |
315 | #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) | |
316 | #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) | |
317 | ||
318 | /* | |
319 | * DUART Output Port RTS Register (Table 10-24) | |
320 | * Register: DUART_OUT_PORT | |
321 | */ | |
322 | ||
323 | #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) | |
324 | #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) | |
325 | #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) | |
326 | #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) | |
327 | #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) | |
328 | ||
329 | #define M_DUART_OUT_PIN_SET(chan) \ | |
330 | (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) | |
331 | #define M_DUART_OUT_PIN_CLR(chan) \ | |
332 | (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) | |
333 | ||
334 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
42a3b4f2 | 335 | /* |
1da177e4 LT |
336 | * Full Interrupt Control Register |
337 | */ | |
338 | ||
339 | #define S_DUART_SIG_FULL _SB_MAKE64(0) | |
340 | #define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) | |
341 | #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) | |
342 | #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) | |
343 | ||
344 | #define S_DUART_INT_TIME _SB_MAKE64(4) | |
345 | #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) | |
346 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) | |
347 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) | |
348 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
349 | ||
350 | ||
351 | /* ********************************************************************** */ | |
352 | ||
353 | ||
354 | #endif |