projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Author: MontaVista Software, Inc. | |
| 3 | * source@mvista.com | |
| 4 | * | |
| 5 | * Copyright 2001-2002 MontaVista Software Inc. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify it | |
| 8 | * under the terms of the GNU General Public License as published by the | |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 10 | * option) any later version. | |
| 11 | * | |
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | |
| 15 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
| 17 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS | |
| 18 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| 19 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR | |
| 20 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE | |
| 21 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 22 | * | |
| 23 | * You should have received a copy of the GNU General Public License along | |
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | |
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 26 | */ | |
| 22b1d707 AN |
27 | #ifndef __ASM_TXX9_RBTX4927_H |
| 28 | #define __ASM_TXX9_RBTX4927_H | |
| 1da177e4 | 29 | |
| 22b1d707 | 30 | #include <asm/txx9/tx4927.h> |
| 1da177e4 | 31 | |
| 89d63fe1 AN |
32 | #define RBTX4927_PCIMEM 0x08000000 |
| 33 | #define RBTX4927_PCIMEM_SIZE 0x08000000 | |
| 34 | #define RBTX4927_PCIIO 0x16000000 | |
| 35 | #define RBTX4927_PCIIO_SIZE 0x01000000 | |
| 36 | ||
| 94a4c329 AN |
37 | #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) |
| 38 | #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) | |
| f96a3383 | 39 | #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) |
| 94a4c329 AN |
40 | #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) |
| 41 | #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) | |
| 42 | #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) | |
| 43 | #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) | |
| 44 | #define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) | |
| 45 | ||
| 46 | /* Ethernet port address */ | |
| 47 | #define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280) | |
| 48 | ||
| 49 | #define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR) | |
| 50 | #define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR) | |
| f96a3383 | 51 | #define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR) |
| 94a4c329 AN |
52 | #define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR) |
| 53 | #define rbtx4927_softresetlock_addr \ | |
| 54 | ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR) | |
| 55 | #define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR) | |
| 89d63fe1 AN |
56 | |
| 57 | /* bits for ISTAT/IMASK/IMSTAT */ | |
| 58 | #define RBTX4927_INTB_PCID 0 | |
| 59 | #define RBTX4927_INTB_PCIC 1 | |
| 60 | #define RBTX4927_INTB_PCIB 2 | |
| 61 | #define RBTX4927_INTB_PCIA 3 | |
| 62 | #define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID) | |
| 63 | #define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC) | |
| 64 | #define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB) | |
| 65 | #define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA) | |
| 66 | ||
| edcaf1a6 AN |
67 | #define RBTX4927_NR_IRQ_IOC 8 /* IOC */ |
| 68 | ||
| 69 | #define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR) | |
| 89d63fe1 AN |
70 | #define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID) |
| 71 | #define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC) | |
| 72 | #define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB) | |
| 73 | #define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA) | |
| 74 | ||
| edcaf1a6 AN |
75 | #define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1)) |
| 76 | ||
| 1da177e4 | 77 | #ifdef CONFIG_PCI |
| 89d63fe1 | 78 | #define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO |
| 1da177e4 | 79 | #else |
| 89d63fe1 | 80 | #define RBTX4927_ISA_IO_OFFSET 0 |
| 1da177e4 LT |
81 | #endif |
| 82 | ||
| 94a4c329 | 83 | #define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base) |
| edcaf1a6 | 84 | #define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3)) |
| 1da177e4 | 85 | |
| edcaf1a6 AN |
86 | void rbtx4927_prom_init(void); |
| 87 | void rbtx4927_irq_setup(void); | |
| 88 | struct pci_dev; | |
| 89 | int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); | |
| d4414cc4 | 90 | |
| 22b1d707 | 91 | #endif /* __ASM_TXX9_RBTX4927_H */ |