]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef __ASM_PARISC_PCI_H |
2 | #define __ASM_PARISC_PCI_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | #include <asm/scatterlist.h> | |
6 | ||
7 | ||
8 | ||
9 | /* | |
10 | ** HP PCI platforms generally support multiple bus adapters. | |
11 | ** (workstations 1-~4, servers 2-~32) | |
12 | ** | |
13 | ** Newer platforms number the busses across PCI bus adapters *sparsely*. | |
14 | ** E.g. 0, 8, 16, ... | |
15 | ** | |
16 | ** Under a PCI bus, most HP platforms support PPBs up to two or three | |
17 | ** levels deep. See "Bit3" product line. | |
18 | */ | |
19 | #define PCI_MAX_BUSSES 256 | |
20 | ||
21 | /* | |
22 | ** pci_hba_data (aka H2P_OBJECT in HP/UX) | |
23 | ** | |
24 | ** This is the "common" or "base" data structure which HBA drivers | |
25 | ** (eg Dino or LBA) are required to place at the top of their own | |
26 | ** platform_data structure. I've heard this called "C inheritance" too. | |
27 | ** | |
28 | ** Data needed by pcibios layer belongs here. | |
29 | */ | |
30 | struct pci_hba_data { | |
31 | void __iomem *base_addr; /* aka Host Physical Address */ | |
32 | const struct parisc_device *dev; /* device from PA bus walk */ | |
33 | struct pci_bus *hba_bus; /* primary PCI bus below HBA */ | |
34 | int hba_num; /* I/O port space access "key" */ | |
35 | struct resource bus_num; /* PCI bus numbers */ | |
36 | struct resource io_space; /* PIOP */ | |
37 | struct resource lmmio_space; /* bus addresses < 4Gb */ | |
38 | struct resource elmmio_space; /* additional bus addresses < 4Gb */ | |
39 | struct resource gmmio_space; /* bus addresses > 4Gb */ | |
40 | ||
41 | /* NOTE: Dino code assumes it can use *all* of the lmmio_space, | |
42 | * elmmio_space and gmmio_space as a contiguous array of | |
43 | * resources. This #define represents the array size */ | |
44 | #define DINO_MAX_LMMIO_RESOURCES 3 | |
45 | ||
46 | unsigned long lmmio_space_offset; /* CPU view - PCI view */ | |
47 | void * iommu; /* IOMMU this device is under */ | |
48 | /* REVISIT - spinlock to protect resources? */ | |
49 | ||
50 | #define HBA_NAME_SIZE 16 | |
51 | char io_name[HBA_NAME_SIZE]; | |
52 | char lmmio_name[HBA_NAME_SIZE]; | |
53 | char elmmio_name[HBA_NAME_SIZE]; | |
54 | char gmmio_name[HBA_NAME_SIZE]; | |
55 | }; | |
56 | ||
57 | #define HBA_DATA(d) ((struct pci_hba_data *) (d)) | |
58 | ||
59 | /* | |
60 | ** We support 2^16 I/O ports per HBA. These are set up in the form | |
61 | ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port | |
62 | ** space address. | |
63 | */ | |
64 | #define HBA_PORT_SPACE_BITS 16 | |
65 | ||
66 | #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) | |
67 | #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) | |
68 | ||
69 | #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) | |
70 | #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) | |
71 | ||
74d13f84 | 72 | #ifdef CONFIG_64BIT |
1da177e4 LT |
73 | #define PCI_F_EXTEND 0xffffffff00000000UL |
74 | #define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a) | |
75 | ||
76 | /* We need to know if an address is LMMMIO or GMMIO. | |
77 | * LMMIO requires mangling and GMMIO we must use as-is. | |
78 | */ | |
79 | static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a) | |
80 | { | |
81 | return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND); | |
82 | } | |
83 | ||
84 | /* | |
85 | ** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses. | |
86 | ** See pcibios.c for more conversions used by Generic PCI code. | |
87 | */ | |
88 | #define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \ | |
89 | ? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \ | |
90 | : (a)) /* GMMIO */ | |
91 | #define PCI_HOST_ADDR(hba,a) ((a) + hba->lmmio_space_offset) | |
92 | ||
93 | #else /* !CONFIG_64BIT */ | |
94 | ||
95 | #define PCI_BUS_ADDR(hba,a) (a) | |
96 | #define PCI_HOST_ADDR(hba,a) (a) | |
97 | #define PCI_F_EXTEND 0UL | |
98 | #define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */ | |
99 | ||
100 | #endif /* !CONFIG_64BIT */ | |
101 | ||
102 | /* | |
103 | ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus | |
104 | ** (This eliminates some of the warnings). | |
105 | */ | |
106 | struct pci_bus; | |
107 | struct pci_dev; | |
108 | ||
109 | /* | |
110 | * If the PCI device's view of memory is the same as the CPU's view of memory, | |
111 | * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use | |
112 | * this boolean for bounce buffer decisions. | |
113 | */ | |
114 | #ifdef CONFIG_PA20 | |
115 | /* All PA-2.0 machines have an IOMMU. */ | |
116 | #define PCI_DMA_BUS_IS_PHYS 0 | |
117 | #define parisc_has_iommu() do { } while (0) | |
118 | #else | |
119 | ||
120 | #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) | |
121 | extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ | |
122 | #define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys | |
123 | #define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) | |
124 | #else | |
125 | #define PCI_DMA_BUS_IS_PHYS 1 | |
126 | #define parisc_has_iommu() do { } while (0) | |
127 | #endif | |
128 | ||
129 | #endif /* !CONFIG_PA20 */ | |
130 | ||
131 | ||
132 | /* | |
133 | ** Most PCI devices (eg Tulip, NCR720) also export the same registers | |
134 | ** to both MMIO and I/O port space. Due to poor performance of I/O Port | |
135 | ** access under HP PCI bus adapters, strongly reccomend use of MMIO | |
136 | ** address space. | |
137 | ** | |
138 | ** While I'm at it more PA programming notes: | |
139 | ** | |
140 | ** 1) MMIO stores (writes) are posted operations. This means the processor | |
141 | ** gets an "ACK" before the write actually gets to the device. A read | |
142 | ** to the same device (or typically the bus adapter above it) will | |
143 | ** force in-flight write transaction(s) out to the targeted device | |
144 | ** before the read can complete. | |
145 | ** | |
146 | ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with | |
147 | ** respect to DMA on all platforms. Ie PIO data can reach the processor | |
148 | ** before in-flight DMA reaches memory. Since most SMP PA platforms | |
149 | ** are I/O coherent, it generally doesn't matter...but sometimes | |
150 | ** it does. | |
151 | ** | |
152 | ** I've helped device driver writers debug both types of problems. | |
153 | */ | |
154 | struct pci_port_ops { | |
155 | u8 (*inb) (struct pci_hba_data *hba, u16 port); | |
156 | u16 (*inw) (struct pci_hba_data *hba, u16 port); | |
157 | u32 (*inl) (struct pci_hba_data *hba, u16 port); | |
158 | void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); | |
159 | void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); | |
160 | void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); | |
161 | }; | |
162 | ||
163 | ||
164 | struct pci_bios_ops { | |
165 | void (*init)(void); | |
166 | void (*fixup_bus)(struct pci_bus *bus); | |
167 | }; | |
168 | ||
169 | /* pci_unmap_{single,page} is not a nop, thus... */ | |
170 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ | |
171 | dma_addr_t ADDR_NAME; | |
172 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ | |
173 | __u32 LEN_NAME; | |
174 | #define pci_unmap_addr(PTR, ADDR_NAME) \ | |
175 | ((PTR)->ADDR_NAME) | |
176 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ | |
177 | (((PTR)->ADDR_NAME) = (VAL)) | |
178 | #define pci_unmap_len(PTR, LEN_NAME) \ | |
179 | ((PTR)->LEN_NAME) | |
180 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ | |
181 | (((PTR)->LEN_NAME) = (VAL)) | |
182 | ||
183 | /* | |
184 | ** Stuff declared in arch/parisc/kernel/pci.c | |
185 | */ | |
186 | extern struct pci_port_ops *pci_port; | |
187 | extern struct pci_bios_ops *pci_bios; | |
188 | extern int pci_post_reset_delay; /* delay after de-asserting #RESET */ | |
189 | extern int pci_hba_count; | |
190 | extern struct pci_hba_data *parisc_pci_hba[]; | |
191 | ||
192 | #ifdef CONFIG_PCI | |
193 | extern void pcibios_register_hba(struct pci_hba_data *); | |
194 | extern void pcibios_set_master(struct pci_dev *); | |
195 | #else | |
196 | extern inline void pcibios_register_hba(struct pci_hba_data *x) | |
197 | { | |
198 | } | |
199 | #endif | |
200 | ||
201 | /* | |
202 | * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() | |
203 | * 0 == check if bridge is numbered before re-numbering. | |
204 | * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. | |
205 | * | |
206 | * We *should* set this to zero for "legacy" platforms and one | |
207 | * for PAT platforms. | |
208 | * | |
209 | * But legacy platforms also need to renumber the busses below a Host | |
210 | * Bus controller. Adding a 4-port Tulip card on the first PCI root | |
211 | * bus of a C200 resulted in the secondary bus being numbered as 1. | |
212 | * The second PCI host bus controller's root bus had already been | |
213 | * assigned bus number 1 by firmware and sysfs complained. | |
214 | * | |
215 | * Firmware isn't doing anything wrong here since each controller | |
216 | * is its own PCI domain. It's simpler and easier for us to renumber | |
217 | * the busses rather than treat each Dino as a separate PCI domain. | |
218 | * Eventually, we may want to introduce PCI domains for Superdome or | |
219 | * rp7420/8420 boxes and then revisit this issue. | |
220 | */ | |
221 | #define pcibios_assign_all_busses() (1) | |
222 | #define pcibios_scan_all_fns(a, b) (0) | |
223 | ||
224 | #define PCIBIOS_MIN_IO 0x10 | |
225 | #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ | |
226 | ||
227 | /* Don't support DAC yet. */ | |
228 | #define pci_dac_dma_supported(pci_dev, mask) (0) | |
229 | ||
230 | /* export the pci_ DMA API in terms of the dma_ one */ | |
231 | #include <asm-generic/pci-dma-compat.h> | |
232 | ||
bb4a61b6 | 233 | #ifdef CONFIG_PCI |
e24c2d96 DM |
234 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
235 | enum pci_dma_burst_strategy *strat, | |
236 | unsigned long *strategy_parameter) | |
237 | { | |
238 | unsigned long cacheline_size; | |
239 | u8 byte; | |
240 | ||
241 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); | |
242 | if (byte == 0) | |
243 | cacheline_size = 1024; | |
244 | else | |
245 | cacheline_size = (int) byte * 4; | |
246 | ||
247 | *strat = PCI_DMA_BURST_MULTIPLE; | |
248 | *strategy_parameter = cacheline_size; | |
249 | } | |
bb4a61b6 | 250 | #endif |
e24c2d96 | 251 | |
1da177e4 LT |
252 | extern void |
253 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
254 | struct resource *res); | |
255 | ||
43c34735 DB |
256 | extern void |
257 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
258 | struct pci_bus_region *region); | |
259 | ||
085ae41f DM |
260 | static inline struct resource * |
261 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) | |
262 | { | |
263 | struct resource *root = NULL; | |
264 | ||
265 | if (res->flags & IORESOURCE_IO) | |
266 | root = &ioport_resource; | |
267 | if (res->flags & IORESOURCE_MEM) | |
268 | root = &iomem_resource; | |
269 | ||
270 | return root; | |
271 | } | |
272 | ||
1da177e4 LT |
273 | static inline void pcibios_add_platform_entries(struct pci_dev *dev) |
274 | { | |
275 | } | |
276 | ||
277 | #endif /* __ASM_PARISC_PCI_H */ |