[mirror_ubuntu-bionic-kernel.git] / include / asm-parisc / pgtable.h

#ifndef _PARISC_PGTABLE_H
#define _PARISC_PGTABLE_H

#include <asm-generic/4level-fixup.h>

#include <linux/config.h>
#include <asm/fixmap.h>

#ifndef __ASSEMBLY__
/*
 * we simulate an x86-style page table for the linux mm code
 */

#include <linux/spinlock.h>
#include <linux/mm.h>		/* for vm_area_struct */
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/bitops.h>

/*
 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
 * memory.  For the return value to be meaningful, ADDR must be >=
 * PAGE_OFFSET.  This operation can be relatively expensive (e.g.,
 * require a hash-, or multi-level tree-lookup or something of that
 * sort) but it guarantees to return TRUE only if accessing the page
 * at that address does not cause an error.  Note that there may be
 * addresses for which kern_addr_valid() returns FALSE even though an
 * access would not cause an error (e.g., this is typically true for
 * memory mapped I/O regions.
 *
 * XXX Need to implement this for parisc.
 */
#define kern_addr_valid(addr)	(1)

/* Certain architectures need to do special things when PTEs
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
#define set_pte(pteptr, pteval)                                 \
        do{                                                     \
                *(pteptr) = (pteval);                           \
        } while(0)
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)

#endif /* !__ASSEMBLY__ */

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))

 /* Note: If you change ISTACK_SIZE, you need to change the corresponding
  * values in vmlinux.lds and vmlinux64.lds (init_istack section). Also,
  * the "order" and size need to agree.
  */

#define  ISTACK_SIZE  32768 /* Interrupt Stack Size */
#define  ISTACK_ORDER 3

/* This is the size of the initially mapped kernel memory (i.e. currently
 * 0 to 1<<23 == 8MB */
#ifdef CONFIG_64BIT
#define KERNEL_INITIAL_ORDER	24
#else
#define KERNEL_INITIAL_ORDER	23
#endif
#define KERNEL_INITIAL_SIZE	(1 << KERNEL_INITIAL_ORDER)

#ifdef CONFIG_64BIT
#define PT_NLEVELS	3
#define PGD_ORDER	1 /* Number of pages per pgd */
#define PMD_ORDER	1 /* Number of pages per pmd */
#define PGD_ALLOC_ORDER	2 /* first pgd contains pmd */
#else
#define PT_NLEVELS	2
#define PGD_ORDER	1 /* Number of pages per pgd */
#define PGD_ALLOC_ORDER	PGD_ORDER
#endif

/* Definitions for 3rd level (we use PLD here for Page Lower directory
 * because PTE_SHIFT is used lower down to mean shift that has to be
 * done to get usable bits out of the PTE) */
#define PLD_SHIFT	PAGE_SHIFT
#define PLD_SIZE	PAGE_SIZE
#define BITS_PER_PTE	(PAGE_SHIFT - BITS_PER_PTE_ENTRY)
#define PTRS_PER_PTE    (1UL << BITS_PER_PTE)

/* Definitions for 2nd level */
#define pgtable_cache_init()	do { } while (0)

#define PMD_SHIFT       (PLD_SHIFT + BITS_PER_PTE)
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))
#if PT_NLEVELS == 3
#define BITS_PER_PMD	(PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
#else
#define BITS_PER_PMD	0
#endif
#define PTRS_PER_PMD    (1UL << BITS_PER_PMD)

/* Definitions for 1st level */
#define PGDIR_SHIFT	(PMD_SHIFT + BITS_PER_PMD)
#define BITS_PER_PGD	(PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))
#define PTRS_PER_PGD    (1UL << BITS_PER_PGD)
#define USER_PTRS_PER_PGD       PTRS_PER_PGD

#define MAX_ADDRBITS	(PGDIR_SHIFT + BITS_PER_PGD)
#define MAX_ADDRESS	(1UL << MAX_ADDRBITS)

#define SPACEID_SHIFT (MAX_ADDRBITS - 32)

/* This calculates the number of initial pages we need for the initial
 * page tables */
#define PT_INITIAL	(1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))

/*
 * pgd entries used up by user/kernel:
 */

#define FIRST_USER_ADDRESS	0

#ifndef __ASSEMBLY__
extern  void *vmalloc_start;
#define PCXL_DMA_MAP_SIZE   (8*1024*1024)
#define VMALLOC_START   ((unsigned long)vmalloc_start)
/* this is a fixmap remnant, see fixmap.h */
#define VMALLOC_END	(KERNEL_MAP_END)
#endif

/* NB: The tlb miss handlers make certain assumptions about the order */
/*     of the following bits, so be careful (One example, bits 25-31  */
/*     are moved together in one instruction).                        */

#define _PAGE_READ_BIT     31   /* (0x001) read access allowed */
#define _PAGE_WRITE_BIT    30   /* (0x002) write access allowed */
#define _PAGE_EXEC_BIT     29   /* (0x004) execute access allowed */
#define _PAGE_GATEWAY_BIT  28   /* (0x008) privilege promotion allowed */
#define _PAGE_DMB_BIT      27   /* (0x010) Data Memory Break enable (B bit) */
#define _PAGE_DIRTY_BIT    26   /* (0x020) Page Dirty (D bit) */
#define _PAGE_FILE_BIT	_PAGE_DIRTY_BIT	/* overload this bit */
#define _PAGE_REFTRAP_BIT  25   /* (0x040) Page Ref. Trap enable (T bit) */
#define _PAGE_NO_CACHE_BIT 24   /* (0x080) Uncached Page (U bit) */
#define _PAGE_ACCESSED_BIT 23   /* (0x100) Software: Page Accessed */
#define _PAGE_PRESENT_BIT  22   /* (0x200) Software: translation valid */
#define _PAGE_FLUSH_BIT    21   /* (0x400) Software: translation valid */
				/*             for cache flushing only */
#define _PAGE_USER_BIT     20   /* (0x800) Software: User accessible page */

/* N.B. The bits are defined in terms of a 32 bit word above, so the */
/*      following macro is ok for both 32 and 64 bit.                */

#define xlate_pabit(x) (31 - x)

/* this defines the shift to the usable bits in the PTE it is set so
 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
 * to zero */
#define PTE_SHIFT	   	xlate_pabit(_PAGE_USER_BIT)

/* this is how many bits may be used by the file functions */
#define PTE_FILE_MAX_BITS	(BITS_PER_LONG - PTE_SHIFT)

#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
#define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })

#define _PAGE_READ     (1 << xlate_pabit(_PAGE_READ_BIT))
#define _PAGE_WRITE    (1 << xlate_pabit(_PAGE_WRITE_BIT))
#define _PAGE_RW       (_PAGE_READ | _PAGE_WRITE)
#define _PAGE_EXEC     (1 << xlate_pabit(_PAGE_EXEC_BIT))
#define _PAGE_GATEWAY  (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
#define _PAGE_DMB      (1 << xlate_pabit(_PAGE_DMB_BIT))
#define _PAGE_DIRTY    (1 << xlate_pabit(_PAGE_DIRTY_BIT))
#define _PAGE_REFTRAP  (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
#define _PAGE_PRESENT  (1 << xlate_pabit(_PAGE_PRESENT_BIT))
#define _PAGE_FLUSH    (1 << xlate_pabit(_PAGE_FLUSH_BIT))
#define _PAGE_USER     (1 << xlate_pabit(_PAGE_USER_BIT))
#define _PAGE_FILE     (1 << xlate_pabit(_PAGE_FILE_BIT))

#define _PAGE_TABLE	(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_ACCESSED)
#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_KERNEL	(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)

/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
 * for a few meta-information bits, so we shift the address to be
 * able to effectively address 40-bits of physical address space. */
#define _PxD_PRESENT_BIT   31
#define _PxD_ATTACHED_BIT  30
#define _PxD_VALID_BIT     29

#define PxD_FLAG_PRESENT  (1 << xlate_pabit(_PxD_PRESENT_BIT))
#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
#define PxD_FLAG_VALID    (1 << xlate_pabit(_PxD_VALID_BIT))
#define PxD_FLAG_MASK     (0xf)
#define PxD_FLAG_SHIFT    (4)
#define PxD_VALUE_SHIFT   (8)

#ifndef __ASSEMBLY__

#define PAGE_NONE	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
#define PAGE_SHARED	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
/* Others seem to make this executable, I don't know if that's correct
   or not.  The stack is mapped this way though so this is necessary
   in the short term - dhd@linuxcare.com, 2000-08-08 */
#define PAGE_READONLY	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
#define PAGE_WRITEONLY  __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
#define PAGE_EXECREAD   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
#define PAGE_COPY       PAGE_EXECREAD
#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
#define PAGE_KERNEL	__pgprot(_PAGE_KERNEL)
#define PAGE_KERNEL_RO	__pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
#define PAGE_KERNEL_UNC	__pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
#define PAGE_GATEWAY    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
#define PAGE_FLUSH      __pgprot(_PAGE_FLUSH)


/*
 * We could have an execute only page using "gateway - promote to priv
 * level 3", but that is kind of silly. So, the way things are defined
 * now, we must always have read permission for pages with execute
 * permission. For the fun of it we'll go ahead and support write only
 * pages.
 */

	 /*xwr*/
#define __P000  PAGE_NONE
#define __P001  PAGE_READONLY
#define __P010  __P000 /* copy on write */
#define __P011  __P001 /* copy on write */
#define __P100  PAGE_EXECREAD
#define __P101  PAGE_EXECREAD
#define __P110  __P100 /* copy on write */
#define __P111  __P101 /* copy on write */

#define __S000  PAGE_NONE
#define __S001  PAGE_READONLY
#define __S010  PAGE_WRITEONLY
#define __S011  PAGE_SHARED
#define __S100  PAGE_EXECREAD
#define __S101  PAGE_EXECREAD
#define __S110  PAGE_RWX
#define __S111  PAGE_RWX

extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */

/* initial page tables for 0-8MB for kernel */

extern pte_t pg0[];

/* zero page used for uninitialized stuff */

extern unsigned long *empty_zero_page;

/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */

#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

#define pte_none(x)     ((pte_val(x) == 0) || (pte_val(x) & _PAGE_FLUSH))
#define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
#define pte_clear(mm,addr,xp)	do { pte_val(*(xp)) = 0; } while (0)

#define pmd_flag(x)	(pmd_val(x) & PxD_FLAG_MASK)
#define pmd_address(x)	((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
#define pgd_flag(x)	(pgd_val(x) & PxD_FLAG_MASK)
#define pgd_address(x)	((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)

#ifdef CONFIG_64BIT
/* The first entry of the permanent pmd is not there if it contains
 * the gateway marker */
#define pmd_none(x)	(!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
#else
#define pmd_none(x)	(!pmd_val(x))
#endif
#define pmd_bad(x)	(!(pmd_flag(x) & PxD_FLAG_VALID))
#define pmd_present(x)	(pmd_flag(x) & PxD_FLAG_PRESENT)
static inline void pmd_clear(pmd_t *pmd) {
#ifdef CONFIG_64BIT
	if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
		/* This is the entry pointing to the permanent pmd
		 * attached to the pgd; cannot clear it */
		__pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
	else
#endif
		__pmd_val_set(*pmd,  0);
}


#if PT_NLEVELS == 3
#define pgd_page(pgd) ((unsigned long) __va(pgd_address(pgd)))

/* For 64 bit we have three level tables */

#define pgd_none(x)     (!pgd_val(x))
#define pgd_bad(x)      (!(pgd_flag(x) & PxD_FLAG_VALID))
#define pgd_present(x)  (pgd_flag(x) & PxD_FLAG_PRESENT)
static inline void pgd_clear(pgd_t *pgd) {
#ifdef CONFIG_64BIT
	if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
		/* This is the permanent pmd attached to the pgd; cannot
		 * free it */
		return;
#endif
	__pgd_val_set(*pgd, 0);
}
#else
/*
 * The "pgd_xxx()" functions here are trivial for a folded two-level
 * setup: the pgd is never bad, and a pmd always exists (as it's folded
 * into the pgd entry)
 */
extern inline int pgd_none(pgd_t pgd)		{ return 0; }
extern inline int pgd_bad(pgd_t pgd)		{ return 0; }
extern inline int pgd_present(pgd_t pgd)	{ return 1; }
extern inline void pgd_clear(pgd_t * pgdp)	{ }
#endif

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
extern inline int pte_read(pte_t pte)		{ return pte_val(pte) & _PAGE_READ; }
extern inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
extern inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }
extern inline int pte_write(pte_t pte)		{ return pte_val(pte) & _PAGE_WRITE; }
extern inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }
extern inline int pte_user(pte_t pte) 		{ return pte_val(pte) & _PAGE_USER; }

extern inline pte_t pte_rdprotect(pte_t pte)	{ pte_val(pte) &= ~_PAGE_READ; return pte; }
extern inline pte_t pte_mkclean(pte_t pte)	{ pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
extern inline pte_t pte_mkold(pte_t pte)	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
extern inline pte_t pte_wrprotect(pte_t pte)	{ pte_val(pte) &= ~_PAGE_WRITE; return pte; }
extern inline pte_t pte_mkread(pte_t pte)	{ pte_val(pte) |= _PAGE_READ; return pte; }
extern inline pte_t pte_mkdirty(pte_t pte)	{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
extern inline pte_t pte_mkyoung(pte_t pte)	{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
extern inline pte_t pte_mkwrite(pte_t pte)	{ pte_val(pte) |= _PAGE_WRITE; return pte; }

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
#define __mk_pte(addr,pgprot) \
({									\
	pte_t __pte;							\
									\
	pte_val(__pte) = ((addr)+pgprot_val(pgprot));			\
									\
	__pte;								\
})

#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))

static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
{
	pte_t pte;
	pte_val(pte) = (pfn << PAGE_SHIFT) | pgprot_val(pgprot);
	return pte;
}

/* This takes a physical page address that is used by the remapping functions */
#define mk_pte_phys(physpage, pgprot) \
({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })

extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }

/* Permanent address of a page.  On parisc we don't have highmem. */

#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)

#define pte_page(pte)		(pfn_to_page(pte_pfn(pte)))

#define pmd_page_kernel(pmd)	((unsigned long) __va(pmd_address(pmd)))

#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
#define pmd_page(pmd)	virt_to_page((void *)__pmd_page(pmd))

#define pgd_index(address) ((address) >> PGDIR_SHIFT)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, address) \
((mm)->pgd + ((address) >> PGDIR_SHIFT))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* Find an entry in the second-level page table.. */

#if PT_NLEVELS == 3
#define pmd_offset(dir,address) \
((pmd_t *) pgd_page(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
#else
#define pmd_offset(dir,addr) ((pmd_t *) dir)
#endif

/* Find an entry in the third-level page table.. */ 
#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
#define pte_offset_kernel(pmd, address) \
	((pte_t *) pmd_page_kernel(*(pmd)) + pte_index(address))
#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
#define pte_unmap(pte) do { } while (0)
#define pte_unmap_nested(pte) do { } while (0)

#define pte_unmap(pte)			do { } while (0)
#define pte_unmap_nested(pte)		do { } while (0)

extern void paging_init (void);

/* Used for deferring calls to flush_dcache_page() */

#define PG_dcache_dirty         PG_arch_1

extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);

/* Encode and de-code a swap entry */

#define __swp_type(x)                     ((x).val & 0x1f)
#define __swp_offset(x)                   ( (((x).val >> 6) &  0x7) | \
					  (((x).val >> 8) & ~0x7) )
#define __swp_entry(type, offset)         ((swp_entry_t) { (type) | \
					    ((offset &  0x7) << 6) | \
					    ((offset & ~0x7) << 8) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
{
#ifdef CONFIG_SMP
	if (!pte_young(*ptep))
		return 0;
	return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
#else
	pte_t pte = *ptep;
	if (!pte_young(pte))
		return 0;
	set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
	return 1;
#endif
}

static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
{
#ifdef CONFIG_SMP
	if (!pte_dirty(*ptep))
		return 0;
	return test_and_clear_bit(xlate_pabit(_PAGE_DIRTY_BIT), &pte_val(*ptep));
#else
	pte_t pte = *ptep;
	if (!pte_dirty(pte))
		return 0;
	set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
	return 1;
#endif
}

extern spinlock_t pa_dbit_lock;

struct mm_struct;
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t old_pte;
	pte_t pte;

	spin_lock(&pa_dbit_lock);
	pte = old_pte = *ptep;
	pte_val(pte) &= ~_PAGE_PRESENT;
	pte_val(pte) |= _PAGE_FLUSH;
	set_pte_at(mm,addr,ptep,pte);
	spin_unlock(&pa_dbit_lock);

	return old_pte;
}

static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
#ifdef CONFIG_SMP
	unsigned long new, old;

	do {
		old = pte_val(*ptep);
		new = pte_val(pte_wrprotect(__pte (old)));
	} while (cmpxchg((unsigned long *) ptep, old, new) != old);
#else
	pte_t old_pte = *ptep;
	set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
#endif
}

#define pte_same(A,B)	(pte_val(A) == pte_val(B))

#endif /* !__ASSEMBLY__ */

#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)		\
		remap_pfn_range(vma, vaddr, pfn, size, prot)

#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)

#define MK_IOSPACE_PFN(space, pfn)	(pfn)
#define GET_IOSPACE(pfn)		0
#define GET_PFN(pfn)			(pfn)

/* We provide our own get_unmapped_area to provide cache coherency */

#define HAVE_ARCH_UNMAPPED_AREA

#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
#define __HAVE_ARCH_PTE_SAME
#include <asm-generic/pgtable.h>

#endif /* _PARISC_PGTABLE_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _PARISC_PGTABLE_H
	2	#define _PARISC_PGTABLE_H
	3
	4	#include <asm-generic/4level-fixup.h>
	5
	6	#include <linux/config.h>
	7	#include <asm/fixmap.h>
	8
	9	#ifndef __ASSEMBLY__
	10	/*
	11	* we simulate an x86-style page table for the linux mm code
	12	*/
	13
	14	#include <linux/spinlock.h>
8c65b4a6	15	#include <linux/mm.h> /* for vm_area_struct */
1da177e4 LT	16	#include <asm/processor.h>
	17	#include <asm/cache.h>
	18	#include <asm/bitops.h>
	19
	20	/*
	21	* kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
	22	* memory. For the return value to be meaningful, ADDR must be >=
	23	* PAGE_OFFSET. This operation can be relatively expensive (e.g.,
	24	* require a hash-, or multi-level tree-lookup or something of that
	25	* sort) but it guarantees to return TRUE only if accessing the page
	26	* at that address does not cause an error. Note that there may be
	27	* addresses for which kern_addr_valid() returns FALSE even though an
	28	* access would not cause an error (e.g., this is typically true for
	29	* memory mapped I/O regions.
	30	*
	31	* XXX Need to implement this for parisc.
	32	*/
	33	#define kern_addr_valid(addr) (1)
	34
	35	/* Certain architectures need to do special things when PTEs
	36	* within a page table are directly modified. Thus, the following
	37	* hook is made available.
	38	*/
	39	#define set_pte(pteptr, pteval) \
	40	do{ \
	41	*(pteptr) = (pteval); \
	42	} while(0)
	43	#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
	44
	45	#endif /* !__ASSEMBLY__ */
	46
	47	#define pte_ERROR(e) \
	48	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	49	#define pmd_ERROR(e) \
	50	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
	51	#define pgd_ERROR(e) \
	52	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
	53
	54	/* Note: If you change ISTACK_SIZE, you need to change the corresponding
	55	* values in vmlinux.lds and vmlinux64.lds (init_istack section). Also,
	56	* the "order" and size need to agree.
	57	*/
	58
	59	#define ISTACK_SIZE 32768 /* Interrupt Stack Size */
	60	#define ISTACK_ORDER 3
	61
	62	/* This is the size of the initially mapped kernel memory (i.e. currently
	63	* 0 to 1<<23 == 8MB */
	64	#ifdef CONFIG_64BIT
	65	#define KERNEL_INITIAL_ORDER 24
	66	#else
	67	#define KERNEL_INITIAL_ORDER 23
	68	#endif
	69	#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
	70
	71	#ifdef CONFIG_64BIT
	72	#define PT_NLEVELS 3
	73	#define PGD_ORDER 1 /* Number of pages per pgd */
	74	#define PMD_ORDER 1 /* Number of pages per pmd */
	75	#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
	76	#else
	77	#define PT_NLEVELS 2
	78	#define PGD_ORDER 1 /* Number of pages per pgd */
	79	#define PGD_ALLOC_ORDER PGD_ORDER
80	#endif
81
82	/* Definitions for 3rd level (we use PLD here for Page Lower directory
83	* because PTE_SHIFT is used lower down to mean shift that has to be
84	* done to get usable bits out of the PTE) */
85	#define PLD_SHIFT PAGE_SHIFT
86	#define PLD_SIZE PAGE_SIZE
87	#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
88	#define PTRS_PER_PTE (1UL << BITS_PER_PTE)
89
90	/* Definitions for 2nd level */
91	#define pgtable_cache_init() do { } while (0)
92
93	#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
94	#define PMD_SIZE (1UL << PMD_SHIFT)
95	#define PMD_MASK (~(PMD_SIZE-1))
96	#if PT_NLEVELS == 3
97	#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
98	#else
99	#define BITS_PER_PMD 0
100	#endif
101	#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
102
103	/* Definitions for 1st level */
104	#define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
105	#define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
106	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
107	#define PGDIR_MASK (~(PGDIR_SIZE-1))
108	#define PTRS_PER_PGD (1UL << BITS_PER_PGD)
109	#define USER_PTRS_PER_PGD PTRS_PER_PGD
110
111	#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
112	#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
113
114	#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
115
116	/* This calculates the number of initial pages we need for the initial
117	* page tables */
118	#define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
119
120	/*
121	* pgd entries used up by user/kernel:
122	*/
123
d455a369	124	#define FIRST_USER_ADDRESS 0
1da177e4 LT	125
	126	#ifndef __ASSEMBLY__
	127	extern void *vmalloc_start;
	128	#define PCXL_DMA_MAP_SIZE (810241024)
	129	#define VMALLOC_START ((unsigned long)vmalloc_start)
	130	/* this is a fixmap remnant, see fixmap.h */
	131	#define VMALLOC_END (KERNEL_MAP_END)
	132	#endif
	133
	134	/* NB: The tlb miss handlers make certain assumptions about the order */
	135	/* of the following bits, so be careful (One example, bits 25-31 */
	136	/* are moved together in one instruction). */
	137
	138	#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
	139	#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
	140	#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
	141	#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
	142	#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
	143	#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
	144	#define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */
	145	#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
	146	#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
	147	#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
	148	#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
	149	#define _PAGE_FLUSH_BIT 21 /* (0x400) Software: translation valid */
	150	/* for cache flushing only */
	151	#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
	152
	153	/* N.B. The bits are defined in terms of a 32 bit word above, so the */
	154	/* following macro is ok for both 32 and 64 bit. */
	155
	156	#define xlate_pabit(x) (31 - x)
	157
	158	/* this defines the shift to the usable bits in the PTE it is set so
	159	* that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
	160	* to zero */
	161	#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
	162
	163	/* this is how many bits may be used by the file functions */
	164	#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
	165
	166	#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
	167	#define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) \| _PAGE_FILE })
	168
	169	#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
	170	#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
	171	#define _PAGE_RW (_PAGE_READ \| _PAGE_WRITE)
	172	#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
	173	#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
	174	#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
	175	#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
	176	#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
	177	#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
	178	#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
	179	#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
	180	#define _PAGE_FLUSH (1 << xlate_pabit(_PAGE_FLUSH_BIT))
	181	#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
	182	#define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT))
	183
	184	#define _PAGE_TABLE (_PAGE_PRESENT \| _PAGE_READ \| _PAGE_WRITE \| _PAGE_DIRTY \| _PAGE_ACCESSED)
	185	#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
	186	#define _PAGE_KERNEL (_PAGE_PRESENT \| _PAGE_EXEC \| _PAGE_READ \| _PAGE_WRITE \| _PAGE_DIRTY \| _PAGE_ACCESSED)
	187
	188	/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
189	* are page-aligned, we don't care about the PAGE_OFFSET bits, except
190	* for a few meta-information bits, so we shift the address to be
191	* able to effectively address 40-bits of physical address space. */
192	#define _PxD_PRESENT_BIT 31
193	#define _PxD_ATTACHED_BIT 30
194	#define _PxD_VALID_BIT 29
195
196	#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
197	#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
198	#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
199	#define PxD_FLAG_MASK (0xf)
200	#define PxD_FLAG_SHIFT (4)
201	#define PxD_VALUE_SHIFT (8)
202
203	#ifndef __ASSEMBLY__
204
205	#define PAGE_NONE __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_ACCESSED)
206	#define PAGE_SHARED __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_READ \| _PAGE_WRITE \| _PAGE_ACCESSED)
207	/* Others seem to make this executable, I don't know if that's correct
208	or not. The stack is mapped this way though so this is necessary
209	in the short term - dhd@linuxcare.com, 2000-08-08 */
210	#define PAGE_READONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_READ \| _PAGE_ACCESSED)
211	#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITE \| _PAGE_ACCESSED)
212	#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_READ \| _PAGE_EXEC \|_PAGE_ACCESSED)
213	#define PAGE_COPY PAGE_EXECREAD
214	#define PAGE_RWX __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_READ \| _PAGE_WRITE \| _PAGE_EXEC \|_PAGE_ACCESSED)
215	#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
1bcdd854	216	#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
1da177e4 LT	217	#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL \| _PAGE_NO_CACHE)
	218	#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_ACCESSED \| _PAGE_GATEWAY\| _PAGE_READ)
	219	#define PAGE_FLUSH __pgprot(_PAGE_FLUSH)
	220
	221
	222	/*
	223	* We could have an execute only page using "gateway - promote to priv
	224	* level 3", but that is kind of silly. So, the way things are defined
	225	* now, we must always have read permission for pages with execute
	226	* permission. For the fun of it we'll go ahead and support write only
	227	* pages.
	228	*/
	229
	230	/xwr/
	231	#define __P000 PAGE_NONE
	232	#define __P001 PAGE_READONLY
	233	#define __P010 __P000 /* copy on write */
	234	#define __P011 __P001 /* copy on write */
	235	#define __P100 PAGE_EXECREAD
	236	#define __P101 PAGE_EXECREAD
	237	#define __P110 __P100 /* copy on write */
	238	#define __P111 __P101 /* copy on write */
	239
	240	#define __S000 PAGE_NONE
	241	#define __S001 PAGE_READONLY
	242	#define __S010 PAGE_WRITEONLY
	243	#define __S011 PAGE_SHARED
	244	#define __S100 PAGE_EXECREAD
	245	#define __S101 PAGE_EXECREAD
	246	#define __S110 PAGE_RWX
	247	#define __S111 PAGE_RWX
	248
	249	extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
	250
	251	/* initial page tables for 0-8MB for kernel */
	252
	253	extern pte_t pg0[];
	254
	255	/* zero page used for uninitialized stuff */
	256
	257	extern unsigned long *empty_zero_page;
	258
	259	/*
	260	* ZERO_PAGE is a global shared page that is always zero: used
	261	* for zero-mapped memory areas etc..
	262	*/
	263
	264	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	265
	266	#define pte_none(x) ((pte_val(x) == 0) \|\| (pte_val(x) & _PAGE_FLUSH))
	267	#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
	268	#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
	269
	270	#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
	271	#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
	272	#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
	273	#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
	274
	275	#ifdef CONFIG_64BIT
	276	/* The first entry of the permanent pmd is not there if it contains
	277	* the gateway marker */
	278	#define pmd_none(x) (!pmd_val(x) \|\| pmd_flag(x) == PxD_FLAG_ATTACHED)
	279	#else
	280	#define pmd_none(x) (!pmd_val(x))
281	#endif
282	#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
283	#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
284	static inline void pmd_clear(pmd_t *pmd) {
285	#ifdef CONFIG_64BIT
286	if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
287	/* This is the entry pointing to the permanent pmd
288	* attached to the pgd; cannot clear it */
289	__pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
290	else
291	#endif
292	__pmd_val_set(*pmd, 0);
293	}
294
295
296
297	#if PT_NLEVELS == 3
298	#define pgd_page(pgd) ((unsigned long) __va(pgd_address(pgd)))
299
300	/* For 64 bit we have three level tables */
301
302	#define pgd_none(x) (!pgd_val(x))
303	#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
304	#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
305	static inline void pgd_clear(pgd_t *pgd) {
306	#ifdef CONFIG_64BIT
307	if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
308	/* This is the permanent pmd attached to the pgd; cannot
309	* free it */
310	return;
311	#endif
312	__pgd_val_set(*pgd, 0);
313	}
314	#else
315	/*
316	* The "pgd_xxx()" functions here are trivial for a folded two-level
317	* setup: the pgd is never bad, and a pmd always exists (as it's folded
318	* into the pgd entry)
319	*/
320	extern inline int pgd_none(pgd_t pgd) { return 0; }
321	extern inline int pgd_bad(pgd_t pgd) { return 0; }
322	extern inline int pgd_present(pgd_t pgd) { return 1; }
323	extern inline void pgd_clear(pgd_t * pgdp) { }
324	#endif
325
326	/*
327	* The following only work if pte_present() is true.
328	* Undefined behaviour if not..
329	*/
330	extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
331	extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
332	extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
333	extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
334	extern inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
335	extern inline int pte_user(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
336
337	extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_READ; return pte; }
338	extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
339	extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
340	extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
341	extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) \|= _PAGE_READ; return pte; }
342	extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) \|= _PAGE_DIRTY; return pte; }
343	extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
344	extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) \|= _PAGE_WRITE; return pte; }
345
346	/*
347	* Conversion functions: convert a page and protection to a page entry,
348	* and a page entry and page directory to the page they refer to.
349	*/
350	#define __mk_pte(addr,pgprot) \
351	({ \
352	pte_t __pte; \
353	\
354	pte_val(__pte) = ((addr)+pgprot_val(pgprot)); \
355	\
356	__pte; \
357	})
358
359	#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
360
361	static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
362	{
363	pte_t pte;
364	pte_val(pte) = (pfn << PAGE_SHIFT) \| pgprot_val(pgprot);
365	return pte;
366	}
367
368	/* This takes a physical page address that is used by the remapping functions */
369	#define mk_pte_phys(physpage, pgprot) \
370	({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
371
372	extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
373	{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot); return pte; }
374
375	/* Permanent address of a page. On parisc we don't have highmem. */
376
377	#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
378
379	#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
380
381	#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_address(pmd)))
382
383	#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
384	#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
385
386	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
387
388	/* to find an entry in a page-table-directory */
389	#define pgd_offset(mm, address) \
390	((mm)->pgd + ((address) >> PGDIR_SHIFT))
391
392	/* to find an entry in a kernel page-table-directory */
393	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
394
395	/* Find an entry in the second-level page table.. */
396
397	#if PT_NLEVELS == 3
398	#define pmd_offset(dir,address) \
399	((pmd_t ) pgd_page((dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
400	#else
401	#define pmd_offset(dir,addr) ((pmd_t *) dir)
402	#endif
403
404	/* Find an entry in the third-level page table.. */
405	#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
406	#define pte_offset_kernel(pmd, address) \
407	((pte_t ) pmd_page_kernel((pmd)) + pte_index(address))
408	#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
409	#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
410	#define pte_unmap(pte) do { } while (0)
411	#define pte_unmap_nested(pte) do { } while (0)
412
413	#define pte_unmap(pte) do { } while (0)
414	#define pte_unmap_nested(pte) do { } while (0)
415
416	extern void paging_init (void);
417
418	/* Used for deferring calls to flush_dcache_page() */
419
420	#define PG_dcache_dirty PG_arch_1
421
1da177e4 LT	422	extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
	423
	424	/* Encode and de-code a swap entry */
	425
	426	#define __swp_type(x) ((x).val & 0x1f)
	427	#define __swp_offset(x) ( (((x).val >> 6) & 0x7) \| \
	428	(((x).val >> 8) & ~0x7) )
	429	#define __swp_entry(type, offset) ((swp_entry_t) { (type) \| \
	430	((offset & 0x7) << 6) \| \
	431	((offset & ~0x7) << 8) })
	432	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	433	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	434
	435	static inline int ptep_test_and_clear_young(struct vm_area_struct vma, unsigned long addr, pte_t ptep)
	436	{
	437	#ifdef CONFIG_SMP
	438	if (!pte_young(*ptep))
	439	return 0;
	440	return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
	441	#else
	442	pte_t pte = *ptep;
	443	if (!pte_young(pte))
	444	return 0;
	445	set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
	446	return 1;
	447	#endif
	448	}
	449
	450	static inline int ptep_test_and_clear_dirty(struct vm_area_struct vma, unsigned long addr, pte_t ptep)
	451	{
	452	#ifdef CONFIG_SMP
	453	if (!pte_dirty(*ptep))
	454	return 0;
	455	return test_and_clear_bit(xlate_pabit(_PAGE_DIRTY_BIT), &pte_val(*ptep));
	456	#else
	457	pte_t pte = *ptep;
	458	if (!pte_dirty(pte))
	459	return 0;
	460	set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
	461	return 1;
	462	#endif
	463	}
	464
	465	extern spinlock_t pa_dbit_lock;
	466
8c65b4a6	467	struct mm_struct;
1da177e4 LT	468	static inline pte_t ptep_get_and_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	469	{
	470	pte_t old_pte;
	471	pte_t pte;
	472
	473	spin_lock(&pa_dbit_lock);
	474	pte = old_pte = *ptep;
	475	pte_val(pte) &= ~_PAGE_PRESENT;
	476	pte_val(pte) \|= _PAGE_FLUSH;
	477	set_pte_at(mm,addr,ptep,pte);
	478	spin_unlock(&pa_dbit_lock);
	479
	480	return old_pte;
	481	}
	482
	483	static inline void ptep_set_wrprotect(struct mm_struct mm, unsigned long addr, pte_t ptep)
	484	{
	485	#ifdef CONFIG_SMP
	486	unsigned long new, old;
	487
	488	do {
	489	old = pte_val(*ptep);
	490	new = pte_val(pte_wrprotect(__pte (old)));
	491	} while (cmpxchg((unsigned long *) ptep, old, new) != old);
	492	#else
	493	pte_t old_pte = *ptep;
	494	set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
	495	#endif
	496	}
	497
	498	#define pte_same(A,B) (pte_val(A) == pte_val(B))
	499
	500	#endif /* !__ASSEMBLY__ */
	501
1da177e4 LT	502	#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
	503	remap_pfn_range(vma, vaddr, pfn, size, prot)
	504
63af965d GG	505	#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) \| _PAGE_NO_CACHE)
63af965d GG	506
1da177e4 LT	507	#define MK_IOSPACE_PFN(space, pfn) (pfn)
	508	#define GET_IOSPACE(pfn) 0
	509	#define GET_PFN(pfn) (pfn)
	510
	511	/* We provide our own get_unmapped_area to provide cache coherency */
	512
	513	#define HAVE_ARCH_UNMAPPED_AREA
	514
	515	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
	516	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
	517	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	518	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	519	#define __HAVE_ARCH_PTE_SAME
	520	#include <asm-generic/pgtable.h>
	521
	522	#endif /* _PARISC_PGTABLE_H */