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1 | #ifndef __PARISC_SYSTEM_H |
2 | #define __PARISC_SYSTEM_H | |
3 | ||
4 | #include <linux/config.h> | |
5 | #include <asm/psw.h> | |
6 | ||
7 | /* The program status word as bitfields. */ | |
8 | struct pa_psw { | |
9 | unsigned int y:1; | |
10 | unsigned int z:1; | |
11 | unsigned int rv:2; | |
12 | unsigned int w:1; | |
13 | unsigned int e:1; | |
14 | unsigned int s:1; | |
15 | unsigned int t:1; | |
16 | ||
17 | unsigned int h:1; | |
18 | unsigned int l:1; | |
19 | unsigned int n:1; | |
20 | unsigned int x:1; | |
21 | unsigned int b:1; | |
22 | unsigned int c:1; | |
23 | unsigned int v:1; | |
24 | unsigned int m:1; | |
25 | ||
26 | unsigned int cb:8; | |
27 | ||
28 | unsigned int o:1; | |
29 | unsigned int g:1; | |
30 | unsigned int f:1; | |
31 | unsigned int r:1; | |
32 | unsigned int q:1; | |
33 | unsigned int p:1; | |
34 | unsigned int d:1; | |
35 | unsigned int i:1; | |
36 | }; | |
37 | ||
38 | #ifdef __LP64__ | |
39 | #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4)) | |
40 | #else | |
41 | #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW)) | |
42 | #endif | |
43 | ||
44 | struct task_struct; | |
45 | ||
46 | extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *); | |
47 | ||
48 | #define switch_to(prev, next, last) do { \ | |
49 | (last) = _switch_to(prev, next); \ | |
50 | } while(0) | |
51 | ||
52 | ||
53 | ||
54 | /* interrupt control */ | |
55 | #define local_save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory") | |
56 | #define local_irq_disable() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) | |
57 | #define local_irq_enable() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) | |
58 | ||
59 | #define local_irq_save(x) \ | |
60 | __asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" ) | |
61 | #define local_irq_restore(x) \ | |
62 | __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" ) | |
63 | ||
64 | #define irqs_disabled() \ | |
65 | ({ \ | |
66 | unsigned long flags; \ | |
67 | local_save_flags(flags); \ | |
68 | (flags & PSW_I) == 0; \ | |
69 | }) | |
70 | ||
71 | #define mfctl(reg) ({ \ | |
72 | unsigned long cr; \ | |
73 | __asm__ __volatile__( \ | |
74 | "mfctl " #reg ",%0" : \ | |
75 | "=r" (cr) \ | |
76 | ); \ | |
77 | cr; \ | |
78 | }) | |
79 | ||
80 | #define mtctl(gr, cr) \ | |
81 | __asm__ __volatile__("mtctl %0,%1" \ | |
82 | : /* no outputs */ \ | |
83 | : "r" (gr), "i" (cr) : "memory") | |
84 | ||
85 | /* these are here to de-mystefy the calling code, and to provide hooks */ | |
86 | /* which I needed for debugging EIEM problems -PB */ | |
87 | #define get_eiem() mfctl(15) | |
88 | static inline void set_eiem(unsigned long val) | |
89 | { | |
90 | mtctl(val, 15); | |
91 | } | |
92 | ||
93 | #define mfsp(reg) ({ \ | |
94 | unsigned long cr; \ | |
95 | __asm__ __volatile__( \ | |
96 | "mfsp " #reg ",%0" : \ | |
97 | "=r" (cr) \ | |
98 | ); \ | |
99 | cr; \ | |
100 | }) | |
101 | ||
102 | #define mtsp(gr, cr) \ | |
103 | __asm__ __volatile__("mtsp %0,%1" \ | |
104 | : /* no outputs */ \ | |
105 | : "r" (gr), "i" (cr) : "memory") | |
106 | ||
107 | ||
108 | /* | |
109 | ** This is simply the barrier() macro from linux/kernel.h but when serial.c | |
110 | ** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h | |
111 | ** hasn't yet been included yet so it fails, thus repeating the macro here. | |
112 | ** | |
113 | ** PA-RISC architecture allows for weakly ordered memory accesses although | |
114 | ** none of the processors use it. There is a strong ordered bit that is | |
115 | ** set in the O-bit of the page directory entry. Operating systems that | |
116 | ** can not tolerate out of order accesses should set this bit when mapping | |
117 | ** pages. The O-bit of the PSW should also be set to 1 (I don't believe any | |
118 | ** of the processor implemented the PSW O-bit). The PCX-W ERS states that | |
119 | ** the TLB O-bit is not implemented so the page directory does not need to | |
120 | ** have the O-bit set when mapping pages (section 3.1). This section also | |
121 | ** states that the PSW Y, Z, G, and O bits are not implemented. | |
122 | ** So it looks like nothing needs to be done for parisc-linux (yet). | |
123 | ** (thanks to chada for the above comment -ggg) | |
124 | ** | |
125 | ** The __asm__ op below simple prevents gcc/ld from reordering | |
126 | ** instructions across the mb() "call". | |
127 | */ | |
128 | #define mb() __asm__ __volatile__("":::"memory") /* barrier() */ | |
129 | #define rmb() mb() | |
130 | #define wmb() mb() | |
131 | #define smp_mb() mb() | |
132 | #define smp_rmb() mb() | |
133 | #define smp_wmb() mb() | |
134 | #define smp_read_barrier_depends() do { } while(0) | |
135 | #define read_barrier_depends() do { } while(0) | |
136 | ||
137 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
138 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | |
139 | ||
140 | ||
141 | /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */ | |
142 | #define __ldcw(a) ({ \ | |
143 | unsigned __ret; \ | |
144 | __asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \ | |
145 | __ret; \ | |
146 | }) | |
147 | ||
148 | /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data, | |
149 | and GCC only guarantees 8-byte alignment for stack locals, we can't | |
150 | be assured of 16-byte alignment for atomic lock data even if we | |
151 | specify "__attribute ((aligned(16)))" in the type declaration. So, | |
152 | we use a struct containing an array of four ints for the atomic lock | |
153 | type and dynamically select the 16-byte aligned int from the array | |
154 | for the semaphore. */ | |
155 | #define __PA_LDCW_ALIGNMENT 16 | |
156 | #define __ldcw_align(a) ({ \ | |
157 | unsigned long __ret = (unsigned long) &(a)->lock[0]; \ | |
158 | __ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \ | |
159 | (volatile unsigned int *) __ret; \ | |
160 | }) | |
161 | ||
162 | #ifdef CONFIG_SMP | |
fb1c8f93 | 163 | # define __lock_aligned __attribute__((__section__(".data.lock_aligned"))) |
1da177e4 LT |
164 | #endif |
165 | ||
166 | #define KERNEL_START (0x10100000 - 0x1000) | |
167 | ||
168 | /* This is for the serialisation of PxTLB broadcasts. At least on the | |
169 | * N class systems, only one PxTLB inter processor broadcast can be | |
170 | * active at any one time on the Merced bus. This tlb purge | |
171 | * synchronisation is fairly lightweight and harmless so we activate | |
172 | * it on all SMP systems not just the N class. */ | |
173 | #ifdef CONFIG_SMP | |
174 | extern spinlock_t pa_tlb_lock; | |
175 | ||
176 | #define purge_tlb_start(x) spin_lock(&pa_tlb_lock) | |
177 | #define purge_tlb_end(x) spin_unlock(&pa_tlb_lock) | |
178 | ||
179 | #else | |
180 | ||
181 | #define purge_tlb_start(x) do { } while(0) | |
182 | #define purge_tlb_end(x) do { } while (0) | |
183 | ||
184 | #endif | |
185 | ||
186 | #define arch_align_stack(x) (x) | |
187 | ||
188 | #endif |