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33d71d26
KG		 1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
15f8c604 14#include <asm/cpm.h>
33d71d26 15
0bfd5df5
KG		 16#ifdef CONFIG_PPC_85xx
17#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
18#endif
19
33d71d26
KG		 20/* CPM Command register.
21*/
22#define CPM_CR_RST ((uint)0x80000000)
23#define CPM_CR_PAGE ((uint)0x7c000000)
24#define CPM_CR_SBLOCK ((uint)0x03e00000)
25#define CPM_CR_FLG ((uint)0x00010000)
26#define CPM_CR_MCN ((uint)0x00003fc0)
27#define CPM_CR_OPCODE ((uint)0x0000000f)
28
29/* Device sub-block and page codes.
30*/
31#define CPM_CR_SCC1_SBLOCK (0x04)
32#define CPM_CR_SCC2_SBLOCK (0x05)
33#define CPM_CR_SCC3_SBLOCK (0x06)
34#define CPM_CR_SCC4_SBLOCK (0x07)
35#define CPM_CR_SMC1_SBLOCK (0x08)
36#define CPM_CR_SMC2_SBLOCK (0x09)
37#define CPM_CR_SPI_SBLOCK (0x0a)
38#define CPM_CR_I2C_SBLOCK (0x0b)
39#define CPM_CR_TIMER_SBLOCK (0x0f)
40#define CPM_CR_RAND_SBLOCK (0x0e)
41#define CPM_CR_FCC1_SBLOCK (0x10)
42#define CPM_CR_FCC2_SBLOCK (0x11)
43#define CPM_CR_FCC3_SBLOCK (0x12)
44#define CPM_CR_IDMA1_SBLOCK (0x14)
45#define CPM_CR_IDMA2_SBLOCK (0x15)
46#define CPM_CR_IDMA3_SBLOCK (0x16)
47#define CPM_CR_IDMA4_SBLOCK (0x17)
48#define CPM_CR_MCC1_SBLOCK (0x1c)
49
50#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
51
52#define CPM_CR_SCC1_PAGE (0x00)
53#define CPM_CR_SCC2_PAGE (0x01)
54#define CPM_CR_SCC3_PAGE (0x02)
55#define CPM_CR_SCC4_PAGE (0x03)
56#define CPM_CR_SMC1_PAGE (0x07)
57#define CPM_CR_SMC2_PAGE (0x08)
58#define CPM_CR_SPI_PAGE (0x09)
59#define CPM_CR_I2C_PAGE (0x0a)
60#define CPM_CR_TIMER_PAGE (0x0a)
61#define CPM_CR_RAND_PAGE (0x0a)
62#define CPM_CR_FCC1_PAGE (0x04)
63#define CPM_CR_FCC2_PAGE (0x05)
64#define CPM_CR_FCC3_PAGE (0x06)
65#define CPM_CR_IDMA1_PAGE (0x07)
66#define CPM_CR_IDMA2_PAGE (0x08)
67#define CPM_CR_IDMA3_PAGE (0x09)
68#define CPM_CR_IDMA4_PAGE (0x0a)
69#define CPM_CR_MCC1_PAGE (0x07)
70#define CPM_CR_MCC2_PAGE (0x08)
71
72#define CPM_CR_FCC_PAGE(x) (x + 0x04)
73
e24e788a 74/* CPM2-specific opcodes (see cpm.h for common opcodes)
33d71d26 75*/
33d71d26 76#define CPM_CR_START_IDMA ((ushort)0x0009)
33d71d26
KG		 77
78#define mk_cr_cmd(PG, SBC, MCN, OP) \
79 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
80
33d71d26
KG		 81/* The number of pages of host memory we allocate for CPM. This is
82 * done early in kernel initialization to get physically contiguous
83 * pages.
84 */
85#define NUM_CPM_HOST_PAGES 2
86
87/* Export the base address of the communication processor registers
88 * and dual port ram.
89 */
449012da 90extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
33d71d26 91
15f8c604
SW		 92#define cpm_dpalloc cpm_muram_alloc
93#define cpm_dpfree cpm_muram_free
94#define cpm_dpram_addr cpm_muram_addr
15f8c604 95
33d71d26
KG		 96extern void cpm_setbrg(uint brg, uint rate);
97extern void cpm2_fastbrg(uint brg, uint rate, int div16);
98extern void cpm2_reset(void);
99
33d71d26
KG		 100/* Function code bits, usually generic to devices.
101*/
102#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
103#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
104#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
105#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
106#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
107
108/* Parameter RAM offsets from the base.
109*/
110#define PROFF_SCC1 ((uint)0x8000)
111#define PROFF_SCC2 ((uint)0x8100)
112#define PROFF_SCC3 ((uint)0x8200)
113#define PROFF_SCC4 ((uint)0x8300)
114#define PROFF_FCC1 ((uint)0x8400)
115#define PROFF_FCC2 ((uint)0x8500)
116#define PROFF_FCC3 ((uint)0x8600)
117#define PROFF_MCC1 ((uint)0x8700)
118#define PROFF_SMC1_BASE ((uint)0x87fc)
119#define PROFF_IDMA1_BASE ((uint)0x87fe)
120#define PROFF_MCC2 ((uint)0x8800)
121#define PROFF_SMC2_BASE ((uint)0x88fc)
122#define PROFF_IDMA2_BASE ((uint)0x88fe)
123#define PROFF_SPI_BASE ((uint)0x89fc)
124#define PROFF_IDMA3_BASE ((uint)0x89fe)
125#define PROFF_TIMERS ((uint)0x8ae0)
126#define PROFF_REVNUM ((uint)0x8af0)
127#define PROFF_RAND ((uint)0x8af8)
128#define PROFF_I2C_BASE ((uint)0x8afc)
129#define PROFF_IDMA4_BASE ((uint)0x8afe)
130
131#define PROFF_SCC_SIZE ((uint)0x100)
132#define PROFF_FCC_SIZE ((uint)0x100)
133#define PROFF_SMC_SIZE ((uint)64)
134
135/* The SMCs are relocated to any of the first eight DPRAM pages.
136 * We will fix these at the first locations of DPRAM, until we
137 * get some microcode patches :-).
138 * The parameter ram space for the SMCs is fifty-some bytes, and
139 * they are required to start on a 64 byte boundary.
140 */
141#define PROFF_SMC1 (0)
142#define PROFF_SMC2 (64)
143
144
145/* Define enough so I can at least use the serial port as a UART.
146 */
147typedef struct smc_uart {
148 ushort smc_rbase; /* Rx Buffer descriptor base address */
149 ushort smc_tbase; /* Tx Buffer descriptor base address */
150 u_char smc_rfcr; /* Rx function code */
151 u_char smc_tfcr; /* Tx function code */
152 ushort smc_mrblr; /* Max receive buffer length */
153 uint smc_rstate; /* Internal */
154 uint smc_idp; /* Internal */
155 ushort smc_rbptr; /* Internal */
156 ushort smc_ibc; /* Internal */
157 uint smc_rxtmp; /* Internal */
158 uint smc_tstate; /* Internal */
159 uint smc_tdp; /* Internal */
160 ushort smc_tbptr; /* Internal */
161 ushort smc_tbc; /* Internal */
162 uint smc_txtmp; /* Internal */
163 ushort smc_maxidl; /* Maximum idle characters */
164 ushort smc_tmpidl; /* Temporary idle counter */
165 ushort smc_brklen; /* Last received break length */
166 ushort smc_brkec; /* rcv'd break condition counter */
167 ushort smc_brkcr; /* xmt break count register */
168 ushort smc_rmask; /* Temporary bit mask */
169 uint smc_stmp; /* SDMA Temp */
170} smc_uart_t;
171
172/* SMC uart mode register (Internal memory map).
173*/
174#define SMCMR_REN ((ushort)0x0001)
175#define SMCMR_TEN ((ushort)0x0002)
176#define SMCMR_DM ((ushort)0x000c)
177#define SMCMR_SM_GCI ((ushort)0x0000)
178#define SMCMR_SM_UART ((ushort)0x0020)
179#define SMCMR_SM_TRANS ((ushort)0x0030)
180#define SMCMR_SM_MASK ((ushort)0x0030)
181#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
182#define SMCMR_REVD SMCMR_PM_EVEN
183#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
184#define SMCMR_BS SMCMR_PEN
185#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
186#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
187#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
188
189/* SMC Event and Mask register.
190*/
191#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
192#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
193#define SMCM_TXE ((unsigned char)0x10)
194#define SMCM_BSY ((unsigned char)0x04)
195#define SMCM_TX ((unsigned char)0x02)
196#define SMCM_RX ((unsigned char)0x01)
197
198/* Baud rate generators.
199*/
200#define CPM_BRG_RST ((uint)0x00020000)
201#define CPM_BRG_EN ((uint)0x00010000)
202#define CPM_BRG_EXTC_INT ((uint)0x00000000)
203#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
204#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
205#define CPM_BRG_ATB ((uint)0x00002000)
206#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
207#define CPM_BRG_DIV16 ((uint)0x00000001)
208
209/* SCCs.
210*/
211#define SCC_GSMRH_IRP ((uint)0x00040000)
212#define SCC_GSMRH_GDE ((uint)0x00010000)
213#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
214#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
215#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
216#define SCC_GSMRH_REVD ((uint)0x00002000)
217#define SCC_GSMRH_TRX ((uint)0x00001000)
218#define SCC_GSMRH_TTX ((uint)0x00000800)
219#define SCC_GSMRH_CDP ((uint)0x00000400)
220#define SCC_GSMRH_CTSP ((uint)0x00000200)
221#define SCC_GSMRH_CDS ((uint)0x00000100)
222#define SCC_GSMRH_CTSS ((uint)0x00000080)
223#define SCC_GSMRH_TFL ((uint)0x00000040)
224#define SCC_GSMRH_RFW ((uint)0x00000020)
225#define SCC_GSMRH_TXSY ((uint)0x00000010)
226#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
227#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
228#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
229#define SCC_GSMRH_RTSM ((uint)0x00000002)
230#define SCC_GSMRH_RSYN ((uint)0x00000001)
231
232#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
233#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
234#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
235#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
236#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
237#define SCC_GSMRL_TCI ((uint)0x10000000)
238#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
239#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
240#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
241#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
242#define SCC_GSMRL_RINV ((uint)0x02000000)
243#define SCC_GSMRL_TINV ((uint)0x01000000)
244#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
245#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
246#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
247#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
248#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
249#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
250#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
251#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
252#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
253#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
254#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
255#define SCC_GSMRL_TEND ((uint)0x00040000)
256#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
257#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
258#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
259#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
260#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
261#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
262#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
263#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
264#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
265#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
266#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
267#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
268#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
269#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
270#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
271#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
272#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
273#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
274#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
275#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
276#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
277#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
278#define SCC_GSMRL_ENR ((uint)0x00000020)
279#define SCC_GSMRL_ENT ((uint)0x00000010)
280#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
281#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
282#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
283#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
284#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
285#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
286#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
287#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
288#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
289#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
290
291#define SCC_TODR_TOD ((ushort)0x8000)
292
293/* SCC Event and Mask register.
294*/
295#define SCCM_TXE ((unsigned char)0x10)
296#define SCCM_BSY ((unsigned char)0x04)
297#define SCCM_TX ((unsigned char)0x02)
298#define SCCM_RX ((unsigned char)0x01)
299
300typedef struct scc_param {
301 ushort scc_rbase; /* Rx Buffer descriptor base address */
302 ushort scc_tbase; /* Tx Buffer descriptor base address */
303 u_char scc_rfcr; /* Rx function code */
304 u_char scc_tfcr; /* Tx function code */
305 ushort scc_mrblr; /* Max receive buffer length */
306 uint scc_rstate; /* Internal */
307 uint scc_idp; /* Internal */
308 ushort scc_rbptr; /* Internal */
309 ushort scc_ibc; /* Internal */
310 uint scc_rxtmp; /* Internal */
311 uint scc_tstate; /* Internal */
312 uint scc_tdp; /* Internal */
313 ushort scc_tbptr; /* Internal */
314 ushort scc_tbc; /* Internal */
315 uint scc_txtmp; /* Internal */
316 uint scc_rcrc; /* Internal */
317 uint scc_tcrc; /* Internal */
318} sccp_t;
319
320/* CPM Ethernet through SCC1.
321 */
322typedef struct scc_enet {
323 sccp_t sen_genscc;
324 uint sen_cpres; /* Preset CRC */
325 uint sen_cmask; /* Constant mask for CRC */
326 uint sen_crcec; /* CRC Error counter */
327 uint sen_alec; /* alignment error counter */
328 uint sen_disfc; /* discard frame counter */
329 ushort sen_pads; /* Tx short frame pad character */
330 ushort sen_retlim; /* Retry limit threshold */
331 ushort sen_retcnt; /* Retry limit counter */
332 ushort sen_maxflr; /* maximum frame length register */
333 ushort sen_minflr; /* minimum frame length register */
334 ushort sen_maxd1; /* maximum DMA1 length */
335 ushort sen_maxd2; /* maximum DMA2 length */
336 ushort sen_maxd; /* Rx max DMA */
337 ushort sen_dmacnt; /* Rx DMA counter */
338 ushort sen_maxb; /* Max BD byte count */
339 ushort sen_gaddr1; /* Group address filter */
340 ushort sen_gaddr2;
341 ushort sen_gaddr3;
342 ushort sen_gaddr4;
343 uint sen_tbuf0data0; /* Save area 0 - current frame */
344 uint sen_tbuf0data1; /* Save area 1 - current frame */
345 uint sen_tbuf0rba; /* Internal */
346 uint sen_tbuf0crc; /* Internal */
347 ushort sen_tbuf0bcnt; /* Internal */
348 ushort sen_paddrh; /* physical address (MSB) */
349 ushort sen_paddrm;
350 ushort sen_paddrl; /* physical address (LSB) */
351 ushort sen_pper; /* persistence */
352 ushort sen_rfbdptr; /* Rx first BD pointer */
353 ushort sen_tfbdptr; /* Tx first BD pointer */
354 ushort sen_tlbdptr; /* Tx last BD pointer */
355 uint sen_tbuf1data0; /* Save area 0 - current frame */
356 uint sen_tbuf1data1; /* Save area 1 - current frame */
357 uint sen_tbuf1rba; /* Internal */
358 uint sen_tbuf1crc; /* Internal */
359 ushort sen_tbuf1bcnt; /* Internal */
360 ushort sen_txlen; /* Tx Frame length counter */
361 ushort sen_iaddr1; /* Individual address filter */
362 ushort sen_iaddr2;
363 ushort sen_iaddr3;
364 ushort sen_iaddr4;
365 ushort sen_boffcnt; /* Backoff counter */
366
367 /* NOTE: Some versions of the manual have the following items
368 * incorrectly documented. Below is the proper order.
369 */
370 ushort sen_taddrh; /* temp address (MSB) */
371 ushort sen_taddrm;
372 ushort sen_taddrl; /* temp address (LSB) */
373} scc_enet_t;
374
375
376/* SCC Event register as used by Ethernet.
377*/
378#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
379#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
380#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
381#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
382#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
383#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
384
385/* SCC Mode Register (PSMR) as used by Ethernet.
386*/
387#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
388#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
389#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
390#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
391#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
392#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
393#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
394#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
395#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
396#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
397#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
398#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
399#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
400
33d71d26
KG		 401/* SCC as UART
402*/
403typedef struct scc_uart {
404 sccp_t scc_genscc;
405 uint scc_res1; /* Reserved */
406 uint scc_res2; /* Reserved */
407 ushort scc_maxidl; /* Maximum idle chars */
408 ushort scc_idlc; /* temp idle counter */
409 ushort scc_brkcr; /* Break count register */
410 ushort scc_parec; /* receive parity error counter */
411 ushort scc_frmec; /* receive framing error counter */
412 ushort scc_nosec; /* receive noise counter */
413 ushort scc_brkec; /* receive break condition counter */
414 ushort scc_brkln; /* last received break length */
415 ushort scc_uaddr1; /* UART address character 1 */
416 ushort scc_uaddr2; /* UART address character 2 */
417 ushort scc_rtemp; /* Temp storage */
418 ushort scc_toseq; /* Transmit out of sequence char */
419 ushort scc_char1; /* control character 1 */
420 ushort scc_char2; /* control character 2 */
421 ushort scc_char3; /* control character 3 */
422 ushort scc_char4; /* control character 4 */
423 ushort scc_char5; /* control character 5 */
424 ushort scc_char6; /* control character 6 */
425 ushort scc_char7; /* control character 7 */
426 ushort scc_char8; /* control character 8 */
427 ushort scc_rccm; /* receive control character mask */
428 ushort scc_rccr; /* receive control character register */
429 ushort scc_rlbc; /* receive last break character */
430} scc_uart_t;
431
432/* SCC Event and Mask registers when it is used as a UART.
433*/
434#define UART_SCCM_GLR ((ushort)0x1000)
435#define UART_SCCM_GLT ((ushort)0x0800)
436#define UART_SCCM_AB ((ushort)0x0200)
437#define UART_SCCM_IDL ((ushort)0x0100)
438#define UART_SCCM_GRA ((ushort)0x0080)
439#define UART_SCCM_BRKE ((ushort)0x0040)
440#define UART_SCCM_BRKS ((ushort)0x0020)
441#define UART_SCCM_CCR ((ushort)0x0008)
442#define UART_SCCM_BSY ((ushort)0x0004)
443#define UART_SCCM_TX ((ushort)0x0002)
444#define UART_SCCM_RX ((ushort)0x0001)
445
446/* The SCC PSMR when used as a UART.
447*/
448#define SCU_PSMR_FLC ((ushort)0x8000)
449#define SCU_PSMR_SL ((ushort)0x4000)
450#define SCU_PSMR_CL ((ushort)0x3000)
451#define SCU_PSMR_UM ((ushort)0x0c00)
452#define SCU_PSMR_FRZ ((ushort)0x0200)
453#define SCU_PSMR_RZS ((ushort)0x0100)
454#define SCU_PSMR_SYN ((ushort)0x0080)
455#define SCU_PSMR_DRT ((ushort)0x0040)
456#define SCU_PSMR_PEN ((ushort)0x0010)
457#define SCU_PSMR_RPM ((ushort)0x000c)
458#define SCU_PSMR_REVP ((ushort)0x0008)
459#define SCU_PSMR_TPM ((ushort)0x0003)
460#define SCU_PSMR_TEVP ((ushort)0x0002)
461
462/* CPM Transparent mode SCC.
463 */
464typedef struct scc_trans {
465 sccp_t st_genscc;
466 uint st_cpres; /* Preset CRC */
467 uint st_cmask; /* Constant mask for CRC */
468} scc_trans_t;
469
33d71d26
KG		 470/* How about some FCCs.....
471*/
472#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
473#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
474#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
475#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
476#define FCC_GFMR_TCI ((uint)0x20000000)
477#define FCC_GFMR_TRX ((uint)0x10000000)
478#define FCC_GFMR_TTX ((uint)0x08000000)
479#define FCC_GFMR_TTX ((uint)0x08000000)
480#define FCC_GFMR_CDP ((uint)0x04000000)
481#define FCC_GFMR_CTSP ((uint)0x02000000)
482#define FCC_GFMR_CDS ((uint)0x01000000)
483#define FCC_GFMR_CTSS ((uint)0x00800000)
484#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
485#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
486#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
487#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
488#define FCC_GFMR_RTSM ((uint)0x00002000)
489#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
490#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
491#define FCC_GFMR_REVD ((uint)0x00000400)
492#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
493#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
494#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
495#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
496#define FCC_GFMR_ENR ((uint)0x00000020)
497#define FCC_GFMR_ENT ((uint)0x00000010)
498#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
499#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
500#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
501
502/* Generic FCC parameter ram.
503*/
504typedef struct fcc_param {
505 ushort fcc_riptr; /* Rx Internal temp pointer */
506 ushort fcc_tiptr; /* Tx Internal temp pointer */
507 ushort fcc_res1;
508 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
509 uint fcc_rstate; /* Upper byte is Func code, must be set */
510 uint fcc_rbase; /* Receive BD base */
511 ushort fcc_rbdstat; /* RxBD status */
512 ushort fcc_rbdlen; /* RxBD down counter */
513 uint fcc_rdptr; /* RxBD internal data pointer */
514 uint fcc_tstate; /* Upper byte is Func code, must be set */
515 uint fcc_tbase; /* Transmit BD base */
516 ushort fcc_tbdstat; /* TxBD status */
517 ushort fcc_tbdlen; /* TxBD down counter */
518 uint fcc_tdptr; /* TxBD internal data pointer */
519 uint fcc_rbptr; /* Rx BD Internal buf pointer */
520 uint fcc_tbptr; /* Tx BD Internal buf pointer */
521 uint fcc_rcrc; /* Rx temp CRC */
522 uint fcc_res2;
523 uint fcc_tcrc; /* Tx temp CRC */
524} fccp_t;
525
526
527/* Ethernet controller through FCC.
528*/
529typedef struct fcc_enet {
530 fccp_t fen_genfcc;
531 uint fen_statbuf; /* Internal status buffer */
532 uint fen_camptr; /* CAM address */
533 uint fen_cmask; /* Constant mask for CRC */
534 uint fen_cpres; /* Preset CRC */
535 uint fen_crcec; /* CRC Error counter */
536 uint fen_alec; /* alignment error counter */
537 uint fen_disfc; /* discard frame counter */
538 ushort fen_retlim; /* Retry limit */
539 ushort fen_retcnt; /* Retry counter */
540 ushort fen_pper; /* Persistence */
541 ushort fen_boffcnt; /* backoff counter */
542 uint fen_gaddrh; /* Group address filter, high 32-bits */
543 uint fen_gaddrl; /* Group address filter, low 32-bits */
544 ushort fen_tfcstat; /* out of sequence TxBD */
545 ushort fen_tfclen;
546 uint fen_tfcptr;
547 ushort fen_mflr; /* Maximum frame length (1518) */
548 ushort fen_paddrh; /* MAC address */
549 ushort fen_paddrm;
550 ushort fen_paddrl;
551 ushort fen_ibdcount; /* Internal BD counter */
552 ushort fen_ibdstart; /* Internal BD start pointer */
553 ushort fen_ibdend; /* Internal BD end pointer */
554 ushort fen_txlen; /* Internal Tx frame length counter */
555 uint fen_ibdbase[8]; /* Internal use */
556 uint fen_iaddrh; /* Individual address filter */
557 uint fen_iaddrl;
558 ushort fen_minflr; /* Minimum frame length (64) */
559 ushort fen_taddrh; /* Filter transfer MAC address */
560 ushort fen_taddrm;
561 ushort fen_taddrl;
562 ushort fen_padptr; /* Pointer to pad byte buffer */
563 ushort fen_cftype; /* control frame type */
564 ushort fen_cfrange; /* control frame range */
565 ushort fen_maxb; /* maximum BD count */
566 ushort fen_maxd1; /* Max DMA1 length (1520) */
567 ushort fen_maxd2; /* Max DMA2 length (1520) */
568 ushort fen_maxd; /* internal max DMA count */
569 ushort fen_dmacnt; /* internal DMA counter */
570 uint fen_octc; /* Total octect counter */
571 uint fen_colc; /* Total collision counter */
572 uint fen_broc; /* Total broadcast packet counter */
573 uint fen_mulc; /* Total multicast packet count */
574 uint fen_uspc; /* Total packets < 64 bytes */
575 uint fen_frgc; /* Total packets < 64 bytes with errors */
576 uint fen_ospc; /* Total packets > 1518 */
577 uint fen_jbrc; /* Total packets > 1518 with errors */
578 uint fen_p64c; /* Total packets == 64 bytes */
579 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
580 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
581 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
582 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
583 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
584 uint fen_cambuf; /* Internal CAM buffer poiner */
585 ushort fen_rfthr; /* Received frames threshold */
586 ushort fen_rfcnt; /* Received frames count */
587} fcc_enet_t;
588
589/* FCC Event/Mask register as used by Ethernet.
590*/
591#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
592#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
593#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
594#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
595#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
596#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
597#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
598#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
599
600/* FCC Mode Register (FPSMR) as used by Ethernet.
601*/
602#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
603#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
604#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
605#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
606#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
607#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
608#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
609#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
610#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
611#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
612#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
613#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
614#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
615
616/* IIC parameter RAM.
617*/
618typedef struct iic {
619 ushort iic_rbase; /* Rx Buffer descriptor base address */
620 ushort iic_tbase; /* Tx Buffer descriptor base address */
621 u_char iic_rfcr; /* Rx function code */
622 u_char iic_tfcr; /* Tx function code */
623 ushort iic_mrblr; /* Max receive buffer length */
624 uint iic_rstate; /* Internal */
625 uint iic_rdp; /* Internal */
626 ushort iic_rbptr; /* Internal */
627 ushort iic_rbc; /* Internal */
628 uint iic_rxtmp; /* Internal */
629 uint iic_tstate; /* Internal */
630 uint iic_tdp; /* Internal */
631 ushort iic_tbptr; /* Internal */
632 ushort iic_tbc; /* Internal */
633 uint iic_txtmp; /* Internal */
634} iic_t;
635
636/* SPI parameter RAM.
637*/
638typedef struct spi {
639 ushort spi_rbase; /* Rx Buffer descriptor base address */
640 ushort spi_tbase; /* Tx Buffer descriptor base address */
641 u_char spi_rfcr; /* Rx function code */
642 u_char spi_tfcr; /* Tx function code */
643 ushort spi_mrblr; /* Max receive buffer length */
644 uint spi_rstate; /* Internal */
645 uint spi_rdp; /* Internal */
646 ushort spi_rbptr; /* Internal */
647 ushort spi_rbc; /* Internal */
648 uint spi_rxtmp; /* Internal */
649 uint spi_tstate; /* Internal */
650 uint spi_tdp; /* Internal */
651 ushort spi_tbptr; /* Internal */
652 ushort spi_tbc; /* Internal */
653 uint spi_txtmp; /* Internal */
654 uint spi_res; /* Tx temp. */
655 uint spi_res1[4]; /* SDMA temp. */
656} spi_t;
657
658/* SPI Mode register.
659*/
660#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
661#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
662#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
663#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
664#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
665#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
666#define SPMODE_EN ((ushort)0x0100) /* Enable */
667#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
668#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
669
670#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
671#define SPMODE_PM(x) ((x) &0xF)
672
673#define SPI_EB ((u_char)0x10) /* big endian byte order */
674
33d71d26
KG		 675/* IDMA parameter RAM
676*/
677typedef struct idma {
678 ushort ibase; /* IDMA buffer descriptor table base address */
679 ushort dcm; /* DMA channel mode */
680 ushort ibdptr; /* IDMA current buffer descriptor pointer */
681 ushort dpr_buf; /* IDMA transfer buffer base address */
682 ushort buf_inv; /* internal buffer inventory */
683 ushort ss_max; /* steady-state maximum transfer size */
684 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
685 ushort sts; /* source transfer size */
686 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
687 ushort seob; /* source end of burst */
688 ushort deob; /* destination end of burst */
689 ushort dts; /* destination transfer size */
690 ushort ret_add; /* return address when working in ERM=1 mode */
691 ushort res0; /* reserved */
692 uint bd_cnt; /* internal byte count */
693 uint s_ptr; /* source internal data pointer */
694 uint d_ptr; /* destination internal data pointer */
695 uint istate; /* internal state */
696 u_char res1[20]; /* pad to 64-byte length */
697} idma_t;
698
699/* DMA channel mode bit fields
700*/
701#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
702#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
703#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
704#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
705#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
706#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
707#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
708#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
709#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
710#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
711#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
712#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
713#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
714#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
715#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
716#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
717#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
718#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
719
720/* IDMA Buffer Descriptors
721*/
722typedef struct idma_bd {
723 uint flags;
724 uint len; /* data length */
725 uint src; /* source data buffer pointer */
726 uint dst; /* destination data buffer pointer */
727} idma_bd_t;
728
729/* IDMA buffer descriptor flag bit fields
730*/
731#define IDMA_BD_V ((uint)0x80000000) /* valid */
732#define IDMA_BD_W ((uint)0x20000000) /* wrap */
733#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
734#define IDMA_BD_L ((uint)0x08000000) /* last */
735#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
736#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
737#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
738#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
739#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
740#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
741#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
742#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
743#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
744#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
745#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
746
747/* per-channel IDMA registers
748*/
749typedef struct im_idma {
750 u_char idsr; /* IDMAn event status register */
751 u_char res0[3];
752 u_char idmr; /* IDMAn event mask register */
753 u_char res1[3];
754} im_idma_t;
755
756/* IDMA event register bit fields
757*/
758#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
759#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
760#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
761#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
762
763/* RISC Controller Configuration Register (RCCR) bit fields
764*/
765#define RCCR_TIME ((uint)0x80000000) /* timer enable */
766#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
767#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
768#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
769#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
770#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
771#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
772#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
773#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
774#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
775#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
776#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
777#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
778#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
779#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
780#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
781#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
782#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
783#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
784#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
785#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
786#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
787#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
788#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
789#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
790#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
791#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
792#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
793#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
794#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
795#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
796#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
797#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
798#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
799#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
800#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
801#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
802#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
803
804/*-----------------------------------------------------------------------
805 * CMXFCR - CMX FCC Clock Route Register
806 */
807#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
808#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
809#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
810#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
811#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
812#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
813#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
814#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
815#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
816
817#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
818#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
819#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
820#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
821#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
822#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
823#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
824#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
825
826#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
827#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
828#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
829#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
830#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
831#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
832#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
833#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
834
835#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
836#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
837#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
838#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
839#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
840#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
841#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
842#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
843
844#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
845#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
846#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
847#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
848#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
849#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
850#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
851#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
852
853#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
854#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
855#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
856#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
857#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
858#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
859#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
860#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
861
862#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
863#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
864#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
865#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
866#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
867#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
868#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
869#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
870
871/*-----------------------------------------------------------------------
872 * CMXSCR - CMX SCC Clock Route Register
873 */
874#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
875#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
876#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
877#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
878#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
879#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
880#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
881#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
882#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
883#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
884#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
885#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
886#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
887#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
888#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
889#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
890
891#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
892#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
893#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
894#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
895#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
896#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
897#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
898#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
899
900#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
901#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
902#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
903#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
904#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
905#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
906#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
907#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
908
909#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
910#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
911#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
912#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
913#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
914#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
915#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
916#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
917
918#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
919#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
920#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
921#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
922#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
923#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
924#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
925#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
926
927#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
928#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
929#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
930#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
931#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
932#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
933#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
934#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
935
936#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
937#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
938#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
939#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
940#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
941#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
942#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
943#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
944
945#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
946#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
947#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
948#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
949#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
950#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
951#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
952#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
953
954#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
955#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
956#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
957#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
958#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
959#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
960#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
961#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
962
963/*-----------------------------------------------------------------------
964 * SIUMCR - SIU Module Configuration Register 4-31
965 */
966#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
967#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
968#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
969#define SIUMCR_CDIS 0x10000000 /* Core Disable */
970#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
971#define SIUMCR_DPPC01 0x04000000 /* - " - */
972#define SIUMCR_DPPC10 0x08000000 /* - " - */
973#define SIUMCR_DPPC11 0x0c000000 /* - " - */
974#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
975#define SIUMCR_L2CPC01 0x01000000 /* - " - */
976#define SIUMCR_L2CPC10 0x02000000 /* - " - */
977#define SIUMCR_L2CPC11 0x03000000 /* - " - */
978#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
979#define SIUMCR_LBPC01 0x00400000 /* - " - */
980#define SIUMCR_LBPC10 0x00800000 /* - " - */
981#define SIUMCR_LBPC11 0x00c00000 /* - " - */
982#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
983#define SIUMCR_APPC01 0x00100000 /* - " - */
984#define SIUMCR_APPC10 0x00200000 /* - " - */
985#define SIUMCR_APPC11 0x00300000 /* - " - */
986#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
987#define SIUMCR_CS10PC01 0x00040000 /* - " - */
988#define SIUMCR_CS10PC10 0x00080000 /* - " - */
989#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
990#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
991#define SIUMCR_BCTLC01 0x00010000 /* - " - */
992#define SIUMCR_BCTLC10 0x00020000 /* - " - */
993#define SIUMCR_BCTLC11 0x00030000 /* - " - */
994#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
995#define SIUMCR_MMR01 0x00004000 /* - " - */
996#define SIUMCR_MMR10 0x00008000 /* - " - */
997#define SIUMCR_MMR11 0x0000c000 /* - " - */
998#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
999
1000/*-----------------------------------------------------------------------
1001 * SCCR - System Clock Control Register 9-8
1002*/
1003#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1004#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1005#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1006#define SCCR_PCIDF_SHIFT 3
1007
1008#ifndef CPM_IMMR_OFFSET
1009#define CPM_IMMR_OFFSET 0x101a8
1010#endif
1011
1012#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1013
1014/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1015 * in order to use clock-computing stuff below for the FCC x
1016 */
1017
1018/* Automatically generates register configurations */
1019#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1020
1021#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1022#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1023#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1024#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1025#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1026#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1027
1028#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1029#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1030#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1031#define CMX1_CLK_MASK ((uint)0xff000000)
1032
1033#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1034#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1035#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1036#define CMX2_CLK_MASK ((uint)0x00ff0000)
1037
1038#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1039#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1040#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1041#define CMX3_CLK_MASK ((uint)0x0000ff00)
1042
1043#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1044#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1045
1046#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1047
1048/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1049 * but there is little variation among the choices.
1050 */
1051#define PA1_COL 0x00000001U
1052#define PA1_CRS 0x00000002U
1053#define PA1_TXER 0x00000004U
1054#define PA1_TXEN 0x00000008U
1055#define PA1_RXDV 0x00000010U
1056#define PA1_RXER 0x00000020U
1057#define PA1_TXDAT 0x00003c00U
1058#define PA1_RXDAT 0x0003c000U
1059#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1060#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1061 PA1_RXDV | PA1_RXER)
1062#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1063#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1064
1065
1066/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1067 * but there is little variation among the choices.
1068 */
1069#define PB2_TXER 0x00000001U
1070#define PB2_RXDV 0x00000002U
1071#define PB2_TXEN 0x00000004U
1072#define PB2_RXER 0x00000008U
1073#define PB2_COL 0x00000010U
1074#define PB2_CRS 0x00000020U
1075#define PB2_TXDAT 0x000003c0U
1076#define PB2_RXDAT 0x00003c00U
1077#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1078 PB2_RXER | PB2_RXDV | PB2_TXER)
1079#define PB2_PSORB1 (PB2_TXEN)
1080#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1081#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1082
1083
1084/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1085 * but there is little variation among the choices.
1086 */
1087#define PB3_RXDV 0x00004000U
1088#define PB3_RXER 0x00008000U
1089#define PB3_TXER 0x00010000U
1090#define PB3_TXEN 0x00020000U
1091#define PB3_COL 0x00040000U
1092#define PB3_CRS 0x00080000U
1093#define PB3_TXDAT 0x0f000000U
1094#define PC3_TXDAT 0x00000010U
1095#define PB3_RXDAT 0x00f00000U
1096#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1097 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1098#define PB3_PSORB1 0
1099#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1100#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1101#define PC3_DIRC1 (PC3_TXDAT)
1102
1103/* Handy macro to specify mem for FCCs*/
1104#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1105#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1106#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1107#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1108
1109/* Clocks and GRG's */
1110
1111enum cpm_clk_dir {
1112 CPM_CLK_RX,
1113 CPM_CLK_TX,
1114 CPM_CLK_RTX
1115};
1116
1117enum cpm_clk_target {
1118 CPM_CLK_SCC1,
1119 CPM_CLK_SCC2,
1120 CPM_CLK_SCC3,
1121 CPM_CLK_SCC4,
1122 CPM_CLK_FCC1,
1123 CPM_CLK_FCC2,
2652d4ec
SW		 1124 CPM_CLK_FCC3,
1125 CPM_CLK_SMC1,
1126 CPM_CLK_SMC2,
33d71d26
KG		 1127};
1128
1129enum cpm_clk {
1130 CPM_CLK_NONE = 0,
1131 CPM_BRG1, /* Baud Rate Generator 1 */
1132 CPM_BRG2, /* Baud Rate Generator 2 */
1133 CPM_BRG3, /* Baud Rate Generator 3 */
1134 CPM_BRG4, /* Baud Rate Generator 4 */
1135 CPM_BRG5, /* Baud Rate Generator 5 */
1136 CPM_BRG6, /* Baud Rate Generator 6 */
1137 CPM_BRG7, /* Baud Rate Generator 7 */
1138 CPM_BRG8, /* Baud Rate Generator 8 */
1139 CPM_CLK1, /* Clock 1 */
1140 CPM_CLK2, /* Clock 2 */
1141 CPM_CLK3, /* Clock 3 */
1142 CPM_CLK4, /* Clock 4 */
1143 CPM_CLK5, /* Clock 5 */
1144 CPM_CLK6, /* Clock 6 */
1145 CPM_CLK7, /* Clock 7 */
1146 CPM_CLK8, /* Clock 8 */
1147 CPM_CLK9, /* Clock 9 */
1148 CPM_CLK10, /* Clock 10 */
1149 CPM_CLK11, /* Clock 11 */
1150 CPM_CLK12, /* Clock 12 */
1151 CPM_CLK13, /* Clock 13 */
1152 CPM_CLK14, /* Clock 14 */
1153 CPM_CLK15, /* Clock 15 */
1154 CPM_CLK16, /* Clock 16 */
1155 CPM_CLK17, /* Clock 17 */
1156 CPM_CLK18, /* Clock 18 */
1157 CPM_CLK19, /* Clock 19 */
1158 CPM_CLK20, /* Clock 20 */
1159 CPM_CLK_DUMMY
1160};
1161
1162extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
2652d4ec 1163extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
33d71d26 1164
7f21f529
SW		 1165#define CPM_PIN_INPUT 0
1166#define CPM_PIN_OUTPUT 1
1167#define CPM_PIN_PRIMARY 0
1168#define CPM_PIN_SECONDARY 2
1169#define CPM_PIN_GPIO 4
1170#define CPM_PIN_OPENDRAIN 8
1171
1172void cpm2_set_pin(int port, int pin, int flags);
1173
33d71d26
KG		 1174#endif /* __CPM2__ */
1175#endif /* __KERNEL__ */
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