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powerpc: Fix building of feature-fixup tests on ppc32
[mirror_ubuntu-bionic-kernel.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
10b35d99
KG		 4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 15#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
80f15dc7 20#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 23#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 24#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
e952e6c4 27#define PPC_FEATURE_ARCH_2_06 0x00000100
b962ce9d 28#define PPC_FEATURE_HAS_VSX 0x00000080
10b35d99 29
fab5db97
PM		 30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
10b35d99 33#ifdef __KERNEL__
d1cdcf22
AB		 34
35#include <asm/asm-compat.h>
c5157e58 36#include <asm/feature-fixups.h>
d1cdcf22 37
10b35d99
KG		 38#ifndef __ASSEMBLY__
39
40/* This structure can grow, it's real size is used by head.S code
41 * via the mkdefs mechanism.
42 */
43struct cpu_spec;
10b35d99 44
10b35d99 45typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 46typedef void (*cpu_restore_t)(void);
10b35d99 47
32a33994 48enum powerpc_oprofile_type {
7a45fb19
AW		 49 PPC_OPROFILE_INVALID = 0,
50 PPC_OPROFILE_RS64 = 1,
51 PPC_OPROFILE_POWER4 = 2,
52 PPC_OPROFILE_G4 = 3,
39aef685 53 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 54 PPC_OPROFILE_CELL = 5,
25fc530e 55 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 56};
57
1bd2e5ae
OJ		 58enum powerpc_pmc_type {
59 PPC_PMC_DEFAULT = 0,
60 PPC_PMC_IBM = 1,
61 PPC_PMC_PA6T = 2,
62};
63
47c0bd1a
BH		 64struct pt_regs;
65
66extern int machine_check_generic(struct pt_regs *regs);
67extern int machine_check_4xx(struct pt_regs *regs);
68extern int machine_check_440A(struct pt_regs *regs);
69extern int machine_check_e500(struct pt_regs *regs);
70extern int machine_check_e200(struct pt_regs *regs);
71
87a72f9e 72/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 73struct cpu_spec {
74 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
75 unsigned int pvr_mask;
76 unsigned int pvr_value;
77
78 char *cpu_name;
79 unsigned long cpu_features; /* Kernel features */
80 unsigned int cpu_user_features; /* Userland features */
81
82 /* cache line sizes */
83 unsigned int icache_bsize;
84 unsigned int dcache_bsize;
85
86 /* number of performance monitor counters */
87 unsigned int num_pmcs;
1bd2e5ae 88 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 89
90 /* this is called to initialize various CPU bits like L1 cache,
91 * BHT, SPD, etc... from head.S before branching to identify_machine
92 */
93 cpu_setup_t cpu_setup;
f39b7a55
OJ		 94 /* Used to restore cpu setup on secondary processors and at resume */
95 cpu_restore_t cpu_restore;
10b35d99
KG		 96
97 /* Used by oprofile userspace to select the right counters */
98 char *oprofile_cpu_type;
99
100 /* Processor specific oprofile operations */
32a33994 101 enum powerpc_oprofile_type oprofile_type;
80f15dc7 102
e78dbc80
MN		 103 /* Bit locations inside the mmcra change */
104 unsigned long oprofile_mmcra_sihv;
105 unsigned long oprofile_mmcra_sipr;
106
107 /* Bits to clear during an oprofile exception */
108 unsigned long oprofile_mmcra_clear;
109
80f15dc7
PM		 110 /* Name of processor class, for the ELF AT_PLATFORM entry */
111 char *platform;
47c0bd1a
BH		 112
113 /* Processor specific machine check handling. Return negative
114 * if the error is fatal, 1 if it was fully recovered and 0 to
115 * pass up (not CPU originated) */
116 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 117};
118
10b35d99 119extern struct cpu_spec *cur_cpu_spec;
10b35d99 120
42c4aaad
BH		 121extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
122
974a76f5 123extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 124extern void do_feature_fixups(unsigned long value, void *fixup_start,
125 void *fixup_end);
9b6b563c 126
10b35d99
KG		 127#endif /* __ASSEMBLY__ */
128
129/* CPU kernel features */
130
131/* Retain the 32b definitions all use bottom half of word */
4508dc21 132#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 133#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
134#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
135#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
136#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
137#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
138#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
aba11fc5 139#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
10b35d99
KG		 140#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
141#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
142#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
143#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
144#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
145#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
146#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
147#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
148#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
149#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
150#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
151#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 152#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 153#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
154#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 155#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 156#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 157#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
b64f87c1 158#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
10b35d99 159
3965f8c5
PM		 160/*
161 * Add the 64-bit processor unique features in the top half of the word;
162 * on 32-bit, make the names available but defined to be 0.
163 */
10b35d99 164#ifdef __powerpc64__
3965f8c5 165#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 166#else
3965f8c5 167#define LONG_ASM_CONST(x) 0
10b35d99
KG		 168#endif
169
3965f8c5
PM		 170#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
171#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
172#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
173#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
174#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
175#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
176#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
177#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 178#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
179#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
180#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
181#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 182#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 183#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 184#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
1189be65 185#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
f66bce5e 186#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
b962ce9d 187#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
3965f8c5 188
10b35d99
KG		 189#ifndef __ASSEMBLY__
190
0470466d
SR		 191#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
192 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
193 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 194
195/* We only set the altivec features if the kernel was compiled with altivec
196 * support
197 */
198#ifdef CONFIG_ALTIVEC
199#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
200#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
201#else
202#define CPU_FTR_ALTIVEC_COMP 0
203#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
204#endif
205
b962ce9d
MN		 206/* We only set the VSX features if the kernel was compiled with VSX
207 * support
208 */
209#ifdef CONFIG_VSX
210#define CPU_FTR_VSX_COMP CPU_FTR_VSX
211#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
212#else
213#define CPU_FTR_VSX_COMP 0
214#define PPC_FEATURE_HAS_VSX_COMP 0
215#endif
216
5e14d21e
KG		 217/* We only set the spe features if the kernel was compiled with spe
218 * support
219 */
220#ifdef CONFIG_SPE
221#define CPU_FTR_SPE_COMP CPU_FTR_SPE
222#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
223#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
224#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
225#else
226#define CPU_FTR_SPE_COMP 0
227#define PPC_FEATURE_HAS_SPE_COMP 0
228#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
229#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
230#endif
231
11af1192
SW		 232/* We need to mark all pages as being coherent if we're SMP or we have a
233 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
234 * require it for PCI "streaming/prefetch" to work properly.
10b35d99 235 */
1775dbbc 236#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
11af1192 237 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
10b35d99
KG		 238#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
239#else
240#define CPU_FTR_COMMON 0
241#endif
242
243/* The powersave features NAP & DOZE seems to confuse BDI when
244 debugging. So if a BDI is used, disable theses
245 */
246#ifndef CONFIG_BDI_SWITCH
247#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
248#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
249#else
250#define CPU_FTR_MAYBE_CAN_DOZE 0
251#define CPU_FTR_MAYBE_CAN_NAP 0
252#endif
253
254#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
255 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
256 !defined(CONFIG_BOOKE))
257
4508dc21
DG		 258#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
259 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
260#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 261 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 262 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 263#define CPU_FTRS_604 (CPU_FTR_COMMON | \
aba11fc5 264 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
4508dc21 265#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 266 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 267 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 268#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 269 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 270 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
271 CPU_FTR_PPC_LE)
4508dc21 272#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 274 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
275 CPU_FTR_PPC_LE)
b6f41cc8
JB		 276#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
277#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
278#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
279#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
280 CPU_FTR_HAS_HIGH_BATS)
281#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 282#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c
SR		 283 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
284 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 286#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c
SR		 287 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
288 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 290#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c
SR		 291 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
292 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
b64f87c1 293 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 294#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 295 CPU_FTR_USE_TB | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
297 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
298 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 299 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 300#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 301 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
303 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 304 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 305#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 306 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 307 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
308 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 309 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 310#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 311 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 312 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
313 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
314 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 315 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
4508dc21 316#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 317 CPU_FTR_USE_TB | \
318 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
319 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
320 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 321 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 322#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 323 CPU_FTR_USE_TB | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
325 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
326 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1
BB		 327 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
328 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 329#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 330 CPU_FTR_USE_TB | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 335#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 336 CPU_FTR_USE_TB | \
337 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
338 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
339 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 340 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 341#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 342 CPU_FTR_USE_TB | \
343 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
344 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
345 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 346 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 347#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 348 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 349#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c 350 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
4508dc21 351#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c
SR		 352 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
353 CPU_FTR_COMMON)
4508dc21 354#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
aa42c69c
KP		 355 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
356 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
4508dc21 357#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
7c92943c 358 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
4508dc21
DG		 359#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
360#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
361#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
5e14d21e
KG		 362#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
363 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
364 CPU_FTR_UNIFIED_ID_CACHE)
fc4033b2
KG		 365#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
366 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
367#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
368 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
3dfa8773 369 CPU_FTR_NODSISRALIGN)
fc4033b2 370#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
aba11fc5
KG		 371 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
372 CPU_FTR_L2CSR)
7c92943c 373#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 374
375/* 64-bit CPUs */
4508dc21 376#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
fab5db97 377 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
4508dc21 378#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c92943c
SR		 379 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
380 CPU_FTR_MMCRA | CPU_FTR_CTRL)
4508dc21 381#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
00243000
OJ		 382 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
383 CPU_FTR_MMCRA)
4508dc21 384#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
00243000 385 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 386 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
4508dc21 387#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
00243000 388 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 389 CPU_FTR_MMCRA | CPU_FTR_SMT | \
390 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 391 CPU_FTR_PURR)
4508dc21 392#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
00243000 393 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \
395 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557
AB		 396 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
397 CPU_FTR_DSCR)
e952e6c4
MN		 398#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
399 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
400 CPU_FTR_MMCRA | CPU_FTR_SMT | \
401 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
402 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
403 CPU_FTR_DSCR)
4508dc21 404#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
00243000 405 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 406 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
859deea9 407 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
4508dc21 408#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
b3ebd1d8
OJ		 409 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
410 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
f66bce5e 411 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
4508dc21 412#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
7c92943c 413 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 414
2406f606 415#ifdef __powerpc64__
7c92943c
SR		 416#define CPU_FTRS_POSSIBLE \
417 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 418 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
e952e6c4 419 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
b962ce9d 420 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
2406f606 421#else
7c92943c
SR		 422enum {
423 CPU_FTRS_POSSIBLE =
10b35d99
KG		 424#if CLASSIC_PPC
425 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
426 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
427 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
428 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
429 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
430 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
431 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 432 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
433 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 434#else
435 CPU_FTRS_GENERIC_32 |
436#endif
10b35d99
KG		 437#ifdef CONFIG_8xx
438 CPU_FTRS_8XX |
439#endif
440#ifdef CONFIG_40x
441 CPU_FTRS_40X |
442#endif
443#ifdef CONFIG_44x
444 CPU_FTRS_44X |
445#endif
446#ifdef CONFIG_E200
447 CPU_FTRS_E200 |
448#endif
449#ifdef CONFIG_E500
3dfa8773 450 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
10b35d99 451#endif
10b35d99 452 0,
7c92943c
SR		 453};
454#endif /* __powerpc64__ */
10b35d99 455
2406f606 456#ifdef __powerpc64__
7c92943c
SR		 457#define CPU_FTRS_ALWAYS \
458 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 459 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 460 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 461#else
7c92943c
SR		 462enum {
463 CPU_FTRS_ALWAYS =
10b35d99
KG		 464#if CLASSIC_PPC
465 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
466 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
467 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
468 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
469 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
470 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
471 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 472 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
473 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 474#else
475 CPU_FTRS_GENERIC_32 &
476#endif
10b35d99
KG		 477#ifdef CONFIG_8xx
478 CPU_FTRS_8XX &
479#endif
480#ifdef CONFIG_40x
481 CPU_FTRS_40X &
482#endif
483#ifdef CONFIG_44x
484 CPU_FTRS_44X &
485#endif
486#ifdef CONFIG_E200
487 CPU_FTRS_E200 &
488#endif
489#ifdef CONFIG_E500
3dfa8773 490 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
10b35d99 491#endif
10b35d99
KG		 492 CPU_FTRS_POSSIBLE,
493};
7c92943c 494#endif /* __powerpc64__ */
10b35d99
KG		 495
496static inline int cpu_has_feature(unsigned long feature)
497{
498 return (CPU_FTRS_ALWAYS & feature) ||
499 (CPU_FTRS_POSSIBLE
10b35d99 500 & cur_cpu_spec->cpu_features
10b35d99
KG		 501 & feature);
502}
503
504#endif /* !__ASSEMBLY__ */
505
10b35d99
KG		 506#endif /* __KERNEL__ */
507#endif /* __ASM_POWERPC_CPUTABLE_H */
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