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[POWERPC] Add the ability to find PCI capabilities early on
[mirror_ubuntu-zesty-kernel.git] / include / asm-powerpc / pci-bridge.h
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1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031 3#ifdef __KERNEL__
047ea784 4
5531e41b 5#include <linux/pci.h>
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6#include <linux/list.h>
7#include <linux/ioport.h>
8
9#ifndef CONFIG_PPC64
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10
11struct device_node;
12struct pci_controller;
13
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14/*
15 * Structure of a PCI controller (host bridge)
16 */
17struct pci_controller {
18 struct pci_bus *bus;
a4c9e328 19 char is_dynamic;
5531e41b 20 void *arch_data;
a4c9e328 21 struct list_head list_node;
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22 struct device *parent;
23
24 int first_busno;
25 int last_busno;
26 int self_busno;
27
28 void __iomem *io_base_virt;
29 resource_size_t io_base_phys;
30
31 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space
33 */
34 resource_size_t pci_mem_offset;
35
36 struct pci_ops *ops;
37 volatile unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data;
39
40 /*
41 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
43 * EXT_REG - provides access to PCI-e extended registers
44 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0
47 * config cycles
48 */
49#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
50#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
51#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
52 u32 indirect_type;
53
54 /* Currently, we limit ourselves to 1 IO range and 3 mem
55 * ranges since the common pci_bus structure can't handle more
56 */
57 struct resource io_resource;
58 struct resource mem_resources[3];
5516b540 59 int global_number; /* PCI domain number */
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60};
61
62static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
63{
64 return bus->sysdata;
65}
66
67/* These are used for config access before all the PCI probing
68 has been done. */
69int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
70 int where, u8 *val);
71int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
72 int where, u16 *val);
73int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
74 int where, u32 *val);
75int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
76 int where, u8 val);
77int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
78 int where, u16 val);
79int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
80 int where, u32 val);
81
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82extern int early_find_capability(struct pci_controller *hose, int bus,
83 int dev_fn, int cap);
84
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85extern void setup_indirect_pci_nomap(struct pci_controller* hose,
86 void __iomem *cfg_addr, void __iomem *cfg_data);
87extern void setup_indirect_pci(struct pci_controller* hose,
88 u32 cfg_addr, u32 cfg_data);
89extern void setup_grackle(struct pci_controller *hose);
90
047ea784 91#else
1da177e4 92
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93
94/*
95 * This program is free software; you can redistribute it and/or
96 * modify it under the terms of the GNU General Public License
97 * as published by the Free Software Foundation; either version
98 * 2 of the License, or (at your option) any later version.
99 */
100
101/*
102 * Structure of a PCI controller (host bridge)
103 */
104struct pci_controller {
105 struct pci_bus *bus;
106 char is_dynamic;
357518fa 107 int node;
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108 void *arch_data;
109 struct list_head list_node;
803d4573 110 struct device *parent;
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111
112 int first_busno;
113 int last_busno;
114
115 void __iomem *io_base_virt;
3d5134ee 116 void *io_base_alloc;
396a1a58 117 resource_size_t io_base_phys;
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118
119 /* Some machines have a non 1:1 mapping of
120 * the PCI memory space in the CPU bus space
121 */
396a1a58 122 resource_size_t pci_mem_offset;
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123 unsigned long pci_io_size;
124
125 struct pci_ops *ops;
126 volatile unsigned int __iomem *cfg_addr;
17a6392d 127 volatile void __iomem *cfg_data;
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128
129 /* Currently, we limit ourselves to 1 IO range and 3 mem
130 * ranges since the common pci_bus structure can't handle more
131 */
132 struct resource io_resource;
133 struct resource mem_resources[3];
5531e41b 134 int global_number;
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135 unsigned long buid;
136 unsigned long dma_window_base_cur;
137 unsigned long dma_window_size;
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138
139 void *private_data;
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140};
141
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142/*
143 * PCI stuff, for nodes representing PCI devices, pointed to
144 * by device_node->data.
145 */
146struct pci_controller;
147struct iommu_table;
148
149struct pci_dn {
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150 int busno; /* pci bus number */
151 int bussubno; /* pci subordinate bus number */
152 int devfn; /* pci device and function number */
153 int class_code; /* pci device class */
b5166cc2 154
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155 struct pci_controller *phb; /* for pci devices */
156 struct iommu_table *iommu_table; /* for phb's or bridges */
157 struct pci_dev *pcidev; /* back-pointer to the pci device */
158 struct device_node *node; /* back-pointer to the device_node */
159
160 int pci_ext_config_space; /* for pci devices */
161
162#ifdef CONFIG_EEH
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163 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
164 int eeh_config_addr;
25e591f6 165 int eeh_pe_config_addr; /* new-style partition endpoint address */
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166 int eeh_check_count; /* # times driver ignored error */
167 int eeh_freeze_count; /* # times this device froze up. */
858955bd 168 int eeh_false_positives; /* # times this device reported #ff's */
1635317f 169 u32 config_space[16]; /* saved PCI config space */
c2e221e8 170#endif
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171};
172
173/* Get the pointer to a device_node's pci_dn */
174#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
175
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176struct device_node *fetch_dev_dn(struct pci_dev *dev);
177
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178/* Get a device_node from a pci_dev. This code must be fast except
179 * in the case where the sysdata is incorrect and needs to be fixed
180 * up (this will only happen once).
181 * In this case the sysdata will have been inherited from a PCI host
182 * bridge or a PCI-PCI bridge further up the tree, so it will point
183 * to a valid struct pci_dn, just not the one we want.
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184 */
185static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
186{
187 struct device_node *dn = dev->sysdata;
1635317f 188 struct pci_dn *pdn = dn->data;
1da177e4 189
1635317f 190 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
1da177e4 191 return dn; /* fast path. sysdata is good */
1635317f 192 return fetch_dev_dn(dev);
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193}
194
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195static inline int pci_device_from_OF_node(struct device_node *np,
196 u8 *bus, u8 *devfn)
197{
198 if (!PCI_DN(np))
199 return -ENODEV;
200 *bus = PCI_DN(np)->busno;
201 *devfn = PCI_DN(np)->devfn;
202 return 0;
203}
204
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205static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
206{
207 if (bus->self)
208 return pci_device_to_OF_node(bus->self);
209 else
210 return bus->sysdata; /* Must be root bus (PHB) */
211}
212
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213/** Find the bus corresponding to the indicated device node */
214struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
215
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216/** Remove all of the PCI devices under this bus */
217void pcibios_remove_pci_devices(struct pci_bus *bus);
218
219/** Discover new pci devices under this bus, and add them */
220void pcibios_add_pci_devices(struct pci_bus * bus);
31087d7d 221void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
2bf6a8fa 222
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223extern int pcibios_remove_root_bus(struct pci_controller *phb);
224
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225static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
226{
227 struct device_node *busdn = bus->sysdata;
228
229 BUG_ON(busdn == NULL);
1635317f 230 return PCI_DN(busdn)->phb;
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231}
232
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233extern void pcibios_free_controller(struct pci_controller *phb);
234
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235extern void isa_bridge_find_early(struct pci_controller *hose);
236
237extern int pcibios_unmap_io_space(struct pci_bus *bus);
238extern int pcibios_map_io_space(struct pci_bus *bus);
239
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240/* Return values for ppc_md.pci_probe_mode function */
241#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
242#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
243#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
244
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245#ifdef CONFIG_NUMA
246#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
247#else
248#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
249#endif
250
047ea784 251#endif /* CONFIG_PPC64 */
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252
253/* Get the PCI host controller for an OF device */
254extern struct pci_controller*
255pci_find_hose_for_OF_device(struct device_node* node);
256
257/* Fill up host controller resources from the OF node */
258extern void
259pci_process_bridge_OF_ranges(struct pci_controller *hose,
260 struct device_node *dev, int primary);
261
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262/* Allocate a new PCI host bridge structure */
263extern struct pci_controller *
264pcibios_alloc_controller(struct device_node *dev);
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265#ifdef CONFIG_PCI
266extern unsigned long pci_address_to_pio(phys_addr_t address);
267#else
268static inline unsigned long pci_address_to_pio(phys_addr_t address)
269{
270 return (unsigned long)-1;
271}
272#endif
273
274
275
88ced031 276#endif /* __KERNEL__ */
1da177e4 277#endif