[mirror_ubuntu-artful-kernel.git] / include / asm-powerpc / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__

#ifndef CONFIG_PPC64
#include <linux/ioport.h>
#include <linux/pci.h>

struct device_node;
struct pci_controller;

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	void *arch_data;
	struct pci_controller *next;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;

	void __iomem *io_base_virt;
	resource_size_t io_base_phys;

	/* Some machines (PReP) have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;

	struct pci_ops *ops;
	volatile unsigned int __iomem *cfg_addr;
	volatile void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		(0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG		(0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	(0x00000004)
	u32 indirect_type;

	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	int global_number;		/* PCI domain number */
};

static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
{
	return bus->sysdata;
}

/* These are used for config access before all the PCI probing
   has been done. */
int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
			   int where, u8 *val);
int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
			   int where, u16 *val);
int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
			    int where, u32 *val);
int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
			    int where, u8 val);
int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
			    int where, u16 val);
int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
			     int where, u32 val);

extern void setup_indirect_pci_nomap(struct pci_controller* hose,
			       void __iomem *cfg_addr, void __iomem *cfg_data);
extern void setup_indirect_pci(struct pci_controller* hose,
			       u32 cfg_addr, u32 cfg_data);
extern void setup_grackle(struct pci_controller *hose);

#else

#include <linux/pci.h>
#include <linux/list.h>

/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
	int node;
	void *arch_data;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;

	void __iomem *io_base_virt;
	void *io_base_alloc;
	resource_size_t io_base_phys;

	/* Some machines have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;
	unsigned long pci_io_size;

	struct pci_ops *ops;
	volatile unsigned int __iomem *cfg_addr;
	volatile void __iomem *cfg_data;

	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource io_resource;
	struct resource mem_resources[3];
	int global_number;
	unsigned long buid;
	unsigned long dma_window_base_cur;
	unsigned long dma_window_size;

	void *private_data;
};

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct pci_controller;
struct iommu_table;

struct pci_dn {
	int	busno;			/* pci bus number */
	int	bussubno;		/* pci subordinate bus number */
	int	devfn;			/* pci device and function number */
	int	class_code;		/* pci device class */

	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

#ifdef CONFIG_EEH
	int	eeh_mode;		/* See eeh.h for possible EEH_MODEs */
	int	eeh_config_addr;
	int	eeh_pe_config_addr; /* new-style partition endpoint address */
	int 	eeh_check_count;	/* # times driver ignored error */
	int 	eeh_freeze_count;	/* # times this device froze up. */
	int 	eeh_false_positives;	/* # times this device reported #ff's */
	u32	config_space[16];	/* saved PCI config space */
#endif
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

struct device_node *fetch_dev_dn(struct pci_dev *dev);

/* Get a device_node from a pci_dev.  This code must be fast except
 * in the case where the sysdata is incorrect and needs to be fixed
 * up (this will only happen once).
 * In this case the sysdata will have been inherited from a PCI host
 * bridge or a PCI-PCI bridge further up the tree, so it will point
 * to a valid struct pci_dn, just not the one we want.
 */
static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
{
	struct device_node *dn = dev->sysdata;
	struct pci_dn *pdn = dn->data;

	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
		return dn;	/* fast path.  sysdata is good */
	return fetch_dev_dn(dev);
}

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	if (bus->self)
		return pci_device_to_OF_node(bus->self);
	else
		return bus->sysdata; /* Must be root bus (PHB) */
}

/** Find the bus corresponding to the indicated device node */
struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
void pcibios_add_pci_devices(struct pci_bus * bus);
void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);

extern int pcibios_remove_root_bus(struct pci_controller *phb);

static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
{
	struct device_node *busdn = bus->sysdata;

	BUG_ON(busdn == NULL);
	return PCI_DN(busdn)->phb;
}

extern void pcibios_free_controller(struct pci_controller *phb);

extern void isa_bridge_find_early(struct pci_controller *hose);

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

/* Return values for ppc_md.pci_probe_mode function */
#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif /* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller*
pci_find_hose_for_OF_device(struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void
pci_process_bridge_OF_ranges(struct pci_controller *hose,
			   struct device_node *dev, int primary);

/* Allocate a new PCI host bridge structure */
extern struct pci_controller *
pcibios_alloc_controller(struct device_node *dev);
#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
	return (unsigned long)-1;
}
#endif


#endif /* __KERNEL__ */
#endif
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
047ea784 PM	4
047ea784 PM	5	#ifndef CONFIG_PPC64
5531e41b KG	6	#include <linux/ioport.h>
	7	#include <linux/pci.h>
	8
	9	struct device_node;
	10	struct pci_controller;
	11
5531e41b KG	12	/*
	13	* Structure of a PCI controller (host bridge)
	14	*/
	15	struct pci_controller {
	16	struct pci_bus *bus;
	17	void *arch_data;
5531e41b KG	18	struct pci_controller *next;
	19	struct device *parent;
	20
	21	int first_busno;
	22	int last_busno;
	23	int self_busno;
	24
	25	void __iomem *io_base_virt;
	26	resource_size_t io_base_phys;
	27
	28	/* Some machines (PReP) have a non 1:1 mapping of
	29	* the PCI memory space in the CPU bus space
	30	*/
	31	resource_size_t pci_mem_offset;
	32
	33	struct pci_ops *ops;
	34	volatile unsigned int __iomem *cfg_addr;
	35	volatile void __iomem *cfg_data;
	36
	37	/*
	38	* Used for variants of PCI indirect handling and possible quirks:
	39	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	40	* EXT_REG - provides access to PCI-e extended registers
	41	* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	42	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	43	* to determine which bus number to match on when generating type0
	44	* config cycles
	45	*/
	46	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
	47	#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
	48	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
	49	u32 indirect_type;
	50
	51	/* Currently, we limit ourselves to 1 IO range and 3 mem
	52	* ranges since the common pci_bus structure can't handle more
	53	*/
	54	struct resource io_resource;
	55	struct resource mem_resources[3];
5516b540	56	int global_number; /* PCI domain number */
5531e41b KG	57	};
	58
	59	static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
	60	{
	61	return bus->sysdata;
	62	}
	63
	64	/* These are used for config access before all the PCI probing
	65	has been done. */
	66	int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
	67	int where, u8 *val);
	68	int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
	69	int where, u16 *val);
	70	int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
	71	int where, u32 *val);
	72	int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
	73	int where, u8 val);
	74	int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
	75	int where, u16 val);
	76	int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
	77	int where, u32 val);
	78
	79	extern void setup_indirect_pci_nomap(struct pci_controller* hose,
	80	void __iomem cfg_addr, void __iomem cfg_data);
	81	extern void setup_indirect_pci(struct pci_controller* hose,
	82	u32 cfg_addr, u32 cfg_data);
	83	extern void setup_grackle(struct pci_controller *hose);
	84
047ea784	85	#else
1da177e4 LT	86
1da177e4 LT	87	#include <linux/pci.h>
76f9f87f	88	#include <linux/list.h>
1da177e4 LT	89
	90	/*
	91	* This program is free software; you can redistribute it and/or
	92	* modify it under the terms of the GNU General Public License
	93	* as published by the Free Software Foundation; either version
	94	* 2 of the License, or (at your option) any later version.
	95	*/
	96
	97	/*
	98	* Structure of a PCI controller (host bridge)
	99	*/
	100	struct pci_controller {
	101	struct pci_bus *bus;
	102	char is_dynamic;
357518fa	103	int node;
1da177e4 LT	104	void *arch_data;
1da177e4 LT	105	struct list_head list_node;
803d4573	106	struct device *parent;
1da177e4 LT	107
	108	int first_busno;
	109	int last_busno;
	110
	111	void __iomem *io_base_virt;
3d5134ee	112	void *io_base_alloc;
396a1a58	113	resource_size_t io_base_phys;
1da177e4 LT	114
	115	/* Some machines have a non 1:1 mapping of
	116	* the PCI memory space in the CPU bus space
	117	*/
396a1a58	118	resource_size_t pci_mem_offset;
1da177e4 LT	119	unsigned long pci_io_size;
	120
	121	struct pci_ops *ops;
	122	volatile unsigned int __iomem *cfg_addr;
17a6392d	123	volatile void __iomem *cfg_data;
1da177e4 LT	124
	125	/* Currently, we limit ourselves to 1 IO range and 3 mem
	126	* ranges since the common pci_bus structure can't handle more
	127	*/
	128	struct resource io_resource;
	129	struct resource mem_resources[3];
5531e41b	130	int global_number;
1da177e4 LT	131	unsigned long buid;
	132	unsigned long dma_window_base_cur;
	133	unsigned long dma_window_size;
5b7c726f IK	134
5b7c726f IK	135	void *private_data;
1da177e4 LT	136	};
1da177e4 LT	137
1635317f PM	138	/*
	139	* PCI stuff, for nodes representing PCI devices, pointed to
	140	* by device_node->data.
	141	*/
	142	struct pci_controller;
	143	struct iommu_table;
	144
	145	struct pci_dn {
7684b40c LV	146	int busno; /* pci bus number */
	147	int bussubno; /* pci subordinate bus number */
	148	int devfn; /* pci device and function number */
	149	int class_code; /* pci device class */
b5166cc2	150
c2e221e8 LV	151	struct pci_controller phb; / for pci devices */
	152	struct iommu_table iommu_table; / for phb's or bridges */
	153	struct pci_dev pcidev; / back-pointer to the pci device */
	154	struct device_node node; / back-pointer to the device_node */
	155
	156	int pci_ext_config_space; /* for pci devices */
	157
	158	#ifdef CONFIG_EEH
1635317f PM	159	int eeh_mode; /* See eeh.h for possible EEH_MODEs */
1635317f PM	160	int eeh_config_addr;
25e591f6	161	int eeh_pe_config_addr; /* new-style partition endpoint address */
1635317f PM	162	int eeh_check_count; /* # times driver ignored error */
1635317f PM	163	int eeh_freeze_count; /* # times this device froze up. */
858955bd	164	int eeh_false_positives; /* # times this device reported #ff's */
1635317f	165	u32 config_space[16]; /* saved PCI config space */
c2e221e8	166	#endif
1635317f PM	167	};
	168
	169	/* Get the pointer to a device_node's pci_dn */
	170	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	171
1da177e4 LT	172	struct device_node fetch_dev_dn(struct pci_dev dev);
1da177e4 LT	173
1635317f PM	174	/* Get a device_node from a pci_dev. This code must be fast except
	175	* in the case where the sysdata is incorrect and needs to be fixed
	176	* up (this will only happen once).
	177	* In this case the sysdata will have been inherited from a PCI host
	178	* bridge or a PCI-PCI bridge further up the tree, so it will point
	179	* to a valid struct pci_dn, just not the one we want.
1da177e4 LT	180	*/
	181	static inline struct device_node pci_device_to_OF_node(struct pci_dev dev)
	182	{
	183	struct device_node *dn = dev->sysdata;
1635317f	184	struct pci_dn *pdn = dn->data;
1da177e4	185
1635317f	186	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
1da177e4	187	return dn; /* fast path. sysdata is good */
1635317f	188	return fetch_dev_dn(dev);
1da177e4 LT	189	}
1da177e4 LT	190
40ef8cbc PM	191	static inline int pci_device_from_OF_node(struct device_node *np,
	192	u8 bus, u8 devfn)
	193	{
	194	if (!PCI_DN(np))
	195	return -ENODEV;
	196	*bus = PCI_DN(np)->busno;
	197	*devfn = PCI_DN(np)->devfn;
	198	return 0;
	199	}
	200
1da177e4 LT	201	static inline struct device_node pci_bus_to_OF_node(struct pci_bus bus)
	202	{
	203	if (bus->self)
	204	return pci_device_to_OF_node(bus->self);
	205	else
	206	return bus->sysdata; /* Must be root bus (PHB) */
	207	}
	208
2bf6a8fa LV	209	/** Find the bus corresponding to the indicated device node */
	210	struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
	211
2bf6a8fa LV	212	/** Remove all of the PCI devices under this bus */
	213	void pcibios_remove_pci_devices(struct pci_bus *bus);
	214
	215	/** Discover new pci devices under this bus, and add them */
	216	void pcibios_add_pci_devices(struct pci_bus * bus);
31087d7d	217	void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
2bf6a8fa	218
1da177e4 LT	219	extern int pcibios_remove_root_bus(struct pci_controller *phb);
1da177e4 LT	220
1da177e4 LT	221	static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
	222	{
	223	struct device_node *busdn = bus->sysdata;
	224
	225	BUG_ON(busdn == NULL);
1635317f	226	return PCI_DN(busdn)->phb;
1da177e4 LT	227	}
1da177e4 LT	228
b5166cc2 BH	229	extern void pcibios_free_controller(struct pci_controller *phb);
b5166cc2 BH	230
3d5134ee BH	231	extern void isa_bridge_find_early(struct pci_controller *hose);
	232
	233	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	234	extern int pcibios_map_io_space(struct pci_bus *bus);
	235
4267292b PM	236	/* Return values for ppc_md.pci_probe_mode function */
	237	#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
	238	#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
	239	#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
	240
357518fa AB	241	#ifdef CONFIG_NUMA
	242	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	243	#else
	244	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	245	#endif
	246
047ea784	247	#endif /* CONFIG_PPC64 */
5531e41b KG	248
	249	/* Get the PCI host controller for an OF device */
	250	extern struct pci_controller*
	251	pci_find_hose_for_OF_device(struct device_node* node);
	252
	253	/* Fill up host controller resources from the OF node */
	254	extern void
	255	pci_process_bridge_OF_ranges(struct pci_controller *hose,
	256	struct device_node *dev, int primary);
	257
dbf8471f KG	258	/* Allocate a new PCI host bridge structure */
	259	extern struct pci_controller *
	260	pcibios_alloc_controller(struct device_node *dev);
5531e41b KG	261	#ifdef CONFIG_PCI
	262	extern unsigned long pci_address_to_pio(phys_addr_t address);
	263	#else
	264	static inline unsigned long pci_address_to_pio(phys_addr_t address)
	265	{
	266	return (unsigned long)-1;
	267	}
	268	#endif
	269
	270
	271
88ced031	272	#endif /* __KERNEL__ */
1da177e4	273	#endif