[mirror_ubuntu-artful-kernel.git] / include / asm-powerpc / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__

#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>

#ifndef CONFIG_PPC64

struct device_node;
struct pci_controller;

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
	void *arch_data;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;

	void __iomem *io_base_virt;
	resource_size_t io_base_phys;

	/* Some machines (PReP) have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;

	struct pci_ops *ops;
	volatile unsigned int __iomem *cfg_addr;
	volatile void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		(0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG		(0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	(0x00000004)
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		(0x00000008)
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		(0x00000010)
	u32 indirect_type;

	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	int global_number;		/* PCI domain number */
};

static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
{
	return bus->sysdata;
}

/* These are used for config access before all the PCI probing
   has been done. */
int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
			   int where, u8 *val);
int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
			   int where, u16 *val);
int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
			    int where, u32 *val);
int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
			    int where, u8 val);
int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
			    int where, u16 val);
int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
			     int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       u32 cfg_addr, u32 cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose);
extern void __init update_bridge_resource(struct pci_dev *dev,
					  struct resource *res);

#else


/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
	int node;
	void *arch_data;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;

	void __iomem *io_base_virt;
	void *io_base_alloc;
	resource_size_t io_base_phys;

	/* Some machines have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;
	unsigned long pci_io_size;

	struct pci_ops *ops;
	volatile unsigned int __iomem *cfg_addr;
	volatile void __iomem *cfg_data;

	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource io_resource;
	struct resource mem_resources[3];
	int global_number;
	unsigned long buid;
	unsigned long dma_window_base_cur;
	unsigned long dma_window_size;

	void *private_data;
};

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct pci_controller;
struct iommu_table;

struct pci_dn {
	int	busno;			/* pci bus number */
	int	bussubno;		/* pci subordinate bus number */
	int	devfn;			/* pci device and function number */
	int	class_code;		/* pci device class */

	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

#ifdef CONFIG_EEH
	int	eeh_mode;		/* See eeh.h for possible EEH_MODEs */
	int	eeh_config_addr;
	int	eeh_pe_config_addr; /* new-style partition endpoint address */
	int 	eeh_check_count;	/* # times driver ignored error */
	int 	eeh_freeze_count;	/* # times this device froze up. */
	int 	eeh_false_positives;	/* # times this device reported #ff's */
	u32	config_space[16];	/* saved PCI config space */
#endif
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

struct device_node *fetch_dev_dn(struct pci_dev *dev);

/* Get a device_node from a pci_dev.  This code must be fast except
 * in the case where the sysdata is incorrect and needs to be fixed
 * up (this will only happen once).
 * In this case the sysdata will have been inherited from a PCI host
 * bridge or a PCI-PCI bridge further up the tree, so it will point
 * to a valid struct pci_dn, just not the one we want.
 */
static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
{
	struct device_node *dn = dev->sysdata;
	struct pci_dn *pdn = dn->data;

	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
		return dn;	/* fast path.  sysdata is good */
	return fetch_dev_dn(dev);
}

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	if (bus->self)
		return pci_device_to_OF_node(bus->self);
	else
		return bus->sysdata; /* Must be root bus (PHB) */
}

/** Find the bus corresponding to the indicated device node */
struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
void pcibios_add_pci_devices(struct pci_bus * bus);
void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);

extern int pcibios_remove_root_bus(struct pci_controller *phb);

static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
{
	struct device_node *busdn = bus->sysdata;

	BUG_ON(busdn == NULL);
	return PCI_DN(busdn)->phb;
}

extern void pcibios_free_controller(struct pci_controller *phb);

extern void isa_bridge_find_early(struct pci_controller *hose);

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

/* Return values for ppc_md.pci_probe_mode function */
#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif /* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller*
pci_find_hose_for_OF_device(struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void
pci_process_bridge_OF_ranges(struct pci_controller *hose,
			   struct device_node *dev, int primary);

/* Allocate a new PCI host bridge structure */
extern struct pci_controller *
pcibios_alloc_controller(struct device_node *dev);
#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
	return (unsigned long)-1;
}
#endif


#endif /* __KERNEL__ */
#endif
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
047ea784	4
5531e41b	5	#include <linux/pci.h>
a4c9e328 KG	6	#include <linux/list.h>
	7	#include <linux/ioport.h>
	8
	9	#ifndef CONFIG_PPC64
5531e41b KG	10
	11	struct device_node;
	12	struct pci_controller;
	13
5531e41b KG	14	/*
	15	* Structure of a PCI controller (host bridge)
	16	*/
	17	struct pci_controller {
	18	struct pci_bus *bus;
a4c9e328	19	char is_dynamic;
5531e41b	20	void *arch_data;
a4c9e328	21	struct list_head list_node;
5531e41b KG	22	struct device *parent;
	23
	24	int first_busno;
	25	int last_busno;
	26	int self_busno;
	27
	28	void __iomem *io_base_virt;
	29	resource_size_t io_base_phys;
	30
	31	/* Some machines (PReP) have a non 1:1 mapping of
	32	* the PCI memory space in the CPU bus space
	33	*/
	34	resource_size_t pci_mem_offset;
	35
	36	struct pci_ops *ops;
	37	volatile unsigned int __iomem *cfg_addr;
	38	volatile void __iomem *cfg_data;
	39
	40	/*
	41	* Used for variants of PCI indirect handling and possible quirks:
	42	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	43	* EXT_REG - provides access to PCI-e extended registers
	44	* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	45	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	46	* to determine which bus number to match on when generating type0
	47	* config cycles
62c66c8e KG	48	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	49	* hanging if we don't have link and try to do config cycles to
	50	* anything but the PHB. Only allow talking to the PHB if this is
	51	* set.
2e56ff20	52	* BIG_ENDIAN - cfg_addr is a big endian register
5531e41b KG	53	*/
	54	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
	55	#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
	56	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
62c66c8e	57	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
2e56ff20	58	#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
5531e41b KG	59	u32 indirect_type;
	60
	61	/* Currently, we limit ourselves to 1 IO range and 3 mem
	62	* ranges since the common pci_bus structure can't handle more
	63	*/
	64	struct resource io_resource;
	65	struct resource mem_resources[3];
5516b540	66	int global_number; /* PCI domain number */
5531e41b KG	67	};
	68
	69	static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
	70	{
	71	return bus->sysdata;
	72	}
	73
	74	/* These are used for config access before all the PCI probing
	75	has been done. */
	76	int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
	77	int where, u8 *val);
	78	int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
	79	int where, u16 *val);
	80	int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
	81	int where, u32 *val);
	82	int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
	83	int where, u8 val);
	84	int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
	85	int where, u16 val);
	86	int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
	87	int where, u32 val);
	88
38805e5f KG	89	extern int early_find_capability(struct pci_controller *hose, int bus,
	90	int dev_fn, int cap);
	91
5531e41b	92	extern void setup_indirect_pci(struct pci_controller* hose,
2e56ff20	93	u32 cfg_addr, u32 cfg_data, u32 flags);
5531e41b	94	extern void setup_grackle(struct pci_controller *hose);
f64fddbe KG	95	extern void __init update_bridge_resource(struct pci_dev *dev,
f64fddbe KG	96	struct resource *res);
5531e41b	97
047ea784	98	#else
1da177e4	99
1da177e4 LT	100
	101	/*
	102	* This program is free software; you can redistribute it and/or
	103	* modify it under the terms of the GNU General Public License
	104	* as published by the Free Software Foundation; either version
	105	* 2 of the License, or (at your option) any later version.
	106	*/
	107
	108	/*
	109	* Structure of a PCI controller (host bridge)
	110	*/
	111	struct pci_controller {
	112	struct pci_bus *bus;
	113	char is_dynamic;
357518fa	114	int node;
1da177e4 LT	115	void *arch_data;
1da177e4 LT	116	struct list_head list_node;
803d4573	117	struct device *parent;
1da177e4 LT	118
	119	int first_busno;
	120	int last_busno;
	121
	122	void __iomem *io_base_virt;
3d5134ee	123	void *io_base_alloc;
396a1a58	124	resource_size_t io_base_phys;
1da177e4 LT	125
	126	/* Some machines have a non 1:1 mapping of
	127	* the PCI memory space in the CPU bus space
	128	*/
396a1a58	129	resource_size_t pci_mem_offset;
1da177e4 LT	130	unsigned long pci_io_size;
	131
	132	struct pci_ops *ops;
	133	volatile unsigned int __iomem *cfg_addr;
17a6392d	134	volatile void __iomem *cfg_data;
1da177e4 LT	135
	136	/* Currently, we limit ourselves to 1 IO range and 3 mem
	137	* ranges since the common pci_bus structure can't handle more
	138	*/
	139	struct resource io_resource;
	140	struct resource mem_resources[3];
5531e41b	141	int global_number;
1da177e4 LT	142	unsigned long buid;
	143	unsigned long dma_window_base_cur;
	144	unsigned long dma_window_size;
5b7c726f IK	145
5b7c726f IK	146	void *private_data;
1da177e4 LT	147	};
1da177e4 LT	148
1635317f PM	149	/*
	150	* PCI stuff, for nodes representing PCI devices, pointed to
	151	* by device_node->data.
	152	*/
	153	struct pci_controller;
	154	struct iommu_table;
	155
	156	struct pci_dn {
7684b40c LV	157	int busno; /* pci bus number */
	158	int bussubno; /* pci subordinate bus number */
	159	int devfn; /* pci device and function number */
	160	int class_code; /* pci device class */
b5166cc2	161
c2e221e8 LV	162	struct pci_controller phb; / for pci devices */
	163	struct iommu_table iommu_table; / for phb's or bridges */
	164	struct pci_dev pcidev; / back-pointer to the pci device */
	165	struct device_node node; / back-pointer to the device_node */
	166
	167	int pci_ext_config_space; /* for pci devices */
	168
	169	#ifdef CONFIG_EEH
1635317f PM	170	int eeh_mode; /* See eeh.h for possible EEH_MODEs */
1635317f PM	171	int eeh_config_addr;
25e591f6	172	int eeh_pe_config_addr; /* new-style partition endpoint address */
1635317f PM	173	int eeh_check_count; /* # times driver ignored error */
1635317f PM	174	int eeh_freeze_count; /* # times this device froze up. */
858955bd	175	int eeh_false_positives; /* # times this device reported #ff's */
1635317f	176	u32 config_space[16]; /* saved PCI config space */
c2e221e8	177	#endif
1635317f PM	178	};
	179
	180	/* Get the pointer to a device_node's pci_dn */
	181	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	182
1da177e4 LT	183	struct device_node fetch_dev_dn(struct pci_dev dev);
1da177e4 LT	184
1635317f PM	185	/* Get a device_node from a pci_dev. This code must be fast except
	186	* in the case where the sysdata is incorrect and needs to be fixed
	187	* up (this will only happen once).
	188	* In this case the sysdata will have been inherited from a PCI host
	189	* bridge or a PCI-PCI bridge further up the tree, so it will point
	190	* to a valid struct pci_dn, just not the one we want.
1da177e4 LT	191	*/
	192	static inline struct device_node pci_device_to_OF_node(struct pci_dev dev)
	193	{
	194	struct device_node *dn = dev->sysdata;
1635317f	195	struct pci_dn *pdn = dn->data;
1da177e4	196
1635317f	197	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
1da177e4	198	return dn; /* fast path. sysdata is good */
1635317f	199	return fetch_dev_dn(dev);
1da177e4 LT	200	}
1da177e4 LT	201
40ef8cbc PM	202	static inline int pci_device_from_OF_node(struct device_node *np,
	203	u8 bus, u8 devfn)
	204	{
	205	if (!PCI_DN(np))
	206	return -ENODEV;
	207	*bus = PCI_DN(np)->busno;
	208	*devfn = PCI_DN(np)->devfn;
	209	return 0;
	210	}
	211
1da177e4 LT	212	static inline struct device_node pci_bus_to_OF_node(struct pci_bus bus)
	213	{
	214	if (bus->self)
	215	return pci_device_to_OF_node(bus->self);
	216	else
	217	return bus->sysdata; /* Must be root bus (PHB) */
	218	}
	219
2bf6a8fa LV	220	/** Find the bus corresponding to the indicated device node */
	221	struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
	222
2bf6a8fa LV	223	/** Remove all of the PCI devices under this bus */
	224	void pcibios_remove_pci_devices(struct pci_bus *bus);
	225
	226	/** Discover new pci devices under this bus, and add them */
	227	void pcibios_add_pci_devices(struct pci_bus * bus);
31087d7d	228	void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
2bf6a8fa	229
1da177e4 LT	230	extern int pcibios_remove_root_bus(struct pci_controller *phb);
1da177e4 LT	231
1da177e4 LT	232	static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
	233	{
	234	struct device_node *busdn = bus->sysdata;
	235
	236	BUG_ON(busdn == NULL);
1635317f	237	return PCI_DN(busdn)->phb;
1da177e4 LT	238	}
1da177e4 LT	239
b5166cc2 BH	240	extern void pcibios_free_controller(struct pci_controller *phb);
b5166cc2 BH	241
3d5134ee BH	242	extern void isa_bridge_find_early(struct pci_controller *hose);
	243
	244	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	245	extern int pcibios_map_io_space(struct pci_bus *bus);
	246
4267292b PM	247	/* Return values for ppc_md.pci_probe_mode function */
	248	#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
	249	#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
	250	#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
	251
357518fa AB	252	#ifdef CONFIG_NUMA
	253	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	254	#else
	255	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	256	#endif
	257
047ea784	258	#endif /* CONFIG_PPC64 */
5531e41b KG	259
	260	/* Get the PCI host controller for an OF device */
	261	extern struct pci_controller*
	262	pci_find_hose_for_OF_device(struct device_node* node);
	263
	264	/* Fill up host controller resources from the OF node */
	265	extern void
	266	pci_process_bridge_OF_ranges(struct pci_controller *hose,
	267	struct device_node *dev, int primary);
	268
dbf8471f KG	269	/* Allocate a new PCI host bridge structure */
	270	extern struct pci_controller *
	271	pcibios_alloc_controller(struct device_node *dev);
5531e41b KG	272	#ifdef CONFIG_PCI
	273	extern unsigned long pci_address_to_pio(phys_addr_t address);
	274	#else
	275	static inline unsigned long pci_address_to_pio(phys_addr_t address)
	276	{
	277	return (unsigned long)-1;
	278	}
	279	#endif
	280
	281
	282
88ced031	283	#endif /* __KERNEL__ */
1da177e4	284	#endif