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Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-serial
[mirror_ubuntu-hirsute-kernel.git] / include / asm-ppc / cpm2.h
CommitLineData
1da177e4
LT		 1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
14
15/* CPM Command register.
16*/
17#define CPM_CR_RST ((uint)0x80000000)
18#define CPM_CR_PAGE ((uint)0x7c000000)
19#define CPM_CR_SBLOCK ((uint)0x03e00000)
20#define CPM_CR_FLG ((uint)0x00010000)
21#define CPM_CR_MCN ((uint)0x00003fc0)
22#define CPM_CR_OPCODE ((uint)0x0000000f)
23
24/* Device sub-block and page codes.
25*/
26#define CPM_CR_SCC1_SBLOCK (0x04)
27#define CPM_CR_SCC2_SBLOCK (0x05)
28#define CPM_CR_SCC3_SBLOCK (0x06)
29#define CPM_CR_SCC4_SBLOCK (0x07)
30#define CPM_CR_SMC1_SBLOCK (0x08)
31#define CPM_CR_SMC2_SBLOCK (0x09)
32#define CPM_CR_SPI_SBLOCK (0x0a)
33#define CPM_CR_I2C_SBLOCK (0x0b)
34#define CPM_CR_TIMER_SBLOCK (0x0f)
35#define CPM_CR_RAND_SBLOCK (0x0e)
36#define CPM_CR_FCC1_SBLOCK (0x10)
37#define CPM_CR_FCC2_SBLOCK (0x11)
38#define CPM_CR_FCC3_SBLOCK (0x12)
39#define CPM_CR_IDMA1_SBLOCK (0x14)
40#define CPM_CR_IDMA2_SBLOCK (0x15)
41#define CPM_CR_IDMA3_SBLOCK (0x16)
42#define CPM_CR_IDMA4_SBLOCK (0x17)
43#define CPM_CR_MCC1_SBLOCK (0x1c)
44
b0c110b4
VB		 45#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
46
1da177e4
LT		 47#define CPM_CR_SCC1_PAGE (0x00)
48#define CPM_CR_SCC2_PAGE (0x01)
49#define CPM_CR_SCC3_PAGE (0x02)
50#define CPM_CR_SCC4_PAGE (0x03)
51#define CPM_CR_SMC1_PAGE (0x07)
52#define CPM_CR_SMC2_PAGE (0x08)
53#define CPM_CR_SPI_PAGE (0x09)
54#define CPM_CR_I2C_PAGE (0x0a)
55#define CPM_CR_TIMER_PAGE (0x0a)
56#define CPM_CR_RAND_PAGE (0x0a)
57#define CPM_CR_FCC1_PAGE (0x04)
58#define CPM_CR_FCC2_PAGE (0x05)
59#define CPM_CR_FCC3_PAGE (0x06)
60#define CPM_CR_IDMA1_PAGE (0x07)
61#define CPM_CR_IDMA2_PAGE (0x08)
62#define CPM_CR_IDMA3_PAGE (0x09)
63#define CPM_CR_IDMA4_PAGE (0x0a)
64#define CPM_CR_MCC1_PAGE (0x07)
65#define CPM_CR_MCC2_PAGE (0x08)
66
b0c110b4
VB		 67#define CPM_CR_FCC_PAGE(x) (x + 0x04)
68
1da177e4
LT		 69/* Some opcodes (there are more...later)
70*/
71#define CPM_CR_INIT_TRX ((ushort)0x0000)
72#define CPM_CR_INIT_RX ((ushort)0x0001)
73#define CPM_CR_INIT_TX ((ushort)0x0002)
74#define CPM_CR_HUNT_MODE ((ushort)0x0003)
75#define CPM_CR_STOP_TX ((ushort)0x0004)
61f5657c 76#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
1da177e4
LT		 77#define CPM_CR_RESTART_TX ((ushort)0x0006)
78#define CPM_CR_SET_GADDR ((ushort)0x0008)
79#define CPM_CR_START_IDMA ((ushort)0x0009)
80#define CPM_CR_STOP_IDMA ((ushort)0x000b)
81
82#define mk_cr_cmd(PG, SBC, MCN, OP) \
83 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
84
85/* Dual Port RAM addresses. The first 16K is available for almost
86 * any CPM use, so we put the BDs there. The first 128 bytes are
87 * used for SMC1 and SMC2 parameter RAM, so we start allocating
88 * BDs above that. All of this must change when we start
89 * downloading RAM microcode.
90 */
91#define CPM_DATAONLY_BASE ((uint)128)
92#define CPM_DP_NOSPACE ((uint)0x7fffffff)
93#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
94#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
95#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
96#else
97#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
98#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
99#endif
100
101/* The number of pages of host memory we allocate for CPM. This is
102 * done early in kernel initialization to get physically contiguous
103 * pages.
104 */
105#define NUM_CPM_HOST_PAGES 2
106
107static inline long IS_DPERR(const uint offset)
108{
109 return (uint)offset > (uint)-1000L;
110}
111
112/* Export the base address of the communication processor registers
113 * and dual port ram.
114 */
115extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */
d054b5ac 116
1da177e4
LT		 117extern uint cpm_dpalloc(uint size, uint align);
118extern int cpm_dpfree(uint offset);
119extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
120extern void cpm_dpdump(void);
121extern void *cpm_dpram_addr(uint offset);
122extern void cpm_setbrg(uint brg, uint rate);
123extern void cpm2_fastbrg(uint brg, uint rate, int div16);
d054b5ac
KG		 124extern void cpm2_reset(void);
125
1da177e4
LT		 126
127/* Buffer descriptors used by many of the CPM protocols.
128*/
129typedef struct cpm_buf_desc {
130 ushort cbd_sc; /* Status and Control */
131 ushort cbd_datlen; /* Data length in buffer */
132 uint cbd_bufaddr; /* Buffer address in host memory */
133} cbd_t;
134
135#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
136#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
137#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
138#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
139#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
140#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
141#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
142#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
143#define BD_SC_BR ((ushort)0x0020) /* Break received */
144#define BD_SC_FR ((ushort)0x0010) /* Framing error */
145#define BD_SC_PR ((ushort)0x0008) /* Parity error */
146#define BD_SC_OV ((ushort)0x0002) /* Overrun */
147#define BD_SC_CD ((ushort)0x0001) /* ?? */
148
149/* Function code bits, usually generic to devices.
150*/
151#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
152#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
153#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
154#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
155#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
156
157/* Parameter RAM offsets from the base.
158*/
159#define PROFF_SCC1 ((uint)0x8000)
160#define PROFF_SCC2 ((uint)0x8100)
161#define PROFF_SCC3 ((uint)0x8200)
162#define PROFF_SCC4 ((uint)0x8300)
163#define PROFF_FCC1 ((uint)0x8400)
164#define PROFF_FCC2 ((uint)0x8500)
165#define PROFF_FCC3 ((uint)0x8600)
166#define PROFF_MCC1 ((uint)0x8700)
167#define PROFF_SMC1_BASE ((uint)0x87fc)
168#define PROFF_IDMA1_BASE ((uint)0x87fe)
169#define PROFF_MCC2 ((uint)0x8800)
170#define PROFF_SMC2_BASE ((uint)0x88fc)
171#define PROFF_IDMA2_BASE ((uint)0x88fe)
172#define PROFF_SPI_BASE ((uint)0x89fc)
173#define PROFF_IDMA3_BASE ((uint)0x89fe)
174#define PROFF_TIMERS ((uint)0x8ae0)
175#define PROFF_REVNUM ((uint)0x8af0)
176#define PROFF_RAND ((uint)0x8af8)
177#define PROFF_I2C_BASE ((uint)0x8afc)
178#define PROFF_IDMA4_BASE ((uint)0x8afe)
179
fc8e50e3
VB		 180#define PROFF_SCC_SIZE ((uint)0x100)
181#define PROFF_FCC_SIZE ((uint)0x100)
182#define PROFF_SMC_SIZE ((uint)64)
183
1da177e4
LT		 184/* The SMCs are relocated to any of the first eight DPRAM pages.
185 * We will fix these at the first locations of DPRAM, until we
186 * get some microcode patches :-).
187 * The parameter ram space for the SMCs is fifty-some bytes, and
188 * they are required to start on a 64 byte boundary.
189 */
190#define PROFF_SMC1 (0)
191#define PROFF_SMC2 (64)
192
193
194/* Define enough so I can at least use the serial port as a UART.
195 */
196typedef struct smc_uart {
197 ushort smc_rbase; /* Rx Buffer descriptor base address */
198 ushort smc_tbase; /* Tx Buffer descriptor base address */
199 u_char smc_rfcr; /* Rx function code */
200 u_char smc_tfcr; /* Tx function code */
201 ushort smc_mrblr; /* Max receive buffer length */
202 uint smc_rstate; /* Internal */
203 uint smc_idp; /* Internal */
204 ushort smc_rbptr; /* Internal */
205 ushort smc_ibc; /* Internal */
206 uint smc_rxtmp; /* Internal */
207 uint smc_tstate; /* Internal */
208 uint smc_tdp; /* Internal */
209 ushort smc_tbptr; /* Internal */
210 ushort smc_tbc; /* Internal */
211 uint smc_txtmp; /* Internal */
212 ushort smc_maxidl; /* Maximum idle characters */
213 ushort smc_tmpidl; /* Temporary idle counter */
214 ushort smc_brklen; /* Last received break length */
215 ushort smc_brkec; /* rcv'd break condition counter */
216 ushort smc_brkcr; /* xmt break count register */
217 ushort smc_rmask; /* Temporary bit mask */
218 uint smc_stmp; /* SDMA Temp */
219} smc_uart_t;
220
221/* SMC uart mode register (Internal memory map).
222*/
223#define SMCMR_REN ((ushort)0x0001)
224#define SMCMR_TEN ((ushort)0x0002)
225#define SMCMR_DM ((ushort)0x000c)
226#define SMCMR_SM_GCI ((ushort)0x0000)
227#define SMCMR_SM_UART ((ushort)0x0020)
228#define SMCMR_SM_TRANS ((ushort)0x0030)
229#define SMCMR_SM_MASK ((ushort)0x0030)
230#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
231#define SMCMR_REVD SMCMR_PM_EVEN
232#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
233#define SMCMR_BS SMCMR_PEN
234#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
235#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
236#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
237
238/* SMC Event and Mask register.
239*/
240#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
241#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
242#define SMCM_TXE ((unsigned char)0x10)
243#define SMCM_BSY ((unsigned char)0x04)
244#define SMCM_TX ((unsigned char)0x02)
245#define SMCM_RX ((unsigned char)0x01)
246
247/* Baud rate generators.
248*/
249#define CPM_BRG_RST ((uint)0x00020000)
250#define CPM_BRG_EN ((uint)0x00010000)
251#define CPM_BRG_EXTC_INT ((uint)0x00000000)
252#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
253#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
254#define CPM_BRG_ATB ((uint)0x00002000)
255#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
256#define CPM_BRG_DIV16 ((uint)0x00000001)
257
258/* SCCs.
259*/
260#define SCC_GSMRH_IRP ((uint)0x00040000)
261#define SCC_GSMRH_GDE ((uint)0x00010000)
262#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
263#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
264#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
265#define SCC_GSMRH_REVD ((uint)0x00002000)
266#define SCC_GSMRH_TRX ((uint)0x00001000)
267#define SCC_GSMRH_TTX ((uint)0x00000800)
268#define SCC_GSMRH_CDP ((uint)0x00000400)
269#define SCC_GSMRH_CTSP ((uint)0x00000200)
270#define SCC_GSMRH_CDS ((uint)0x00000100)
271#define SCC_GSMRH_CTSS ((uint)0x00000080)
272#define SCC_GSMRH_TFL ((uint)0x00000040)
273#define SCC_GSMRH_RFW ((uint)0x00000020)
274#define SCC_GSMRH_TXSY ((uint)0x00000010)
275#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
276#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
277#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
278#define SCC_GSMRH_RTSM ((uint)0x00000002)
279#define SCC_GSMRH_RSYN ((uint)0x00000001)
280
281#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
282#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
283#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
284#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
285#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
286#define SCC_GSMRL_TCI ((uint)0x10000000)
287#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
288#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
289#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
290#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
291#define SCC_GSMRL_RINV ((uint)0x02000000)
292#define SCC_GSMRL_TINV ((uint)0x01000000)
293#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
294#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
295#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
296#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
297#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
298#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
299#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
300#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
301#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
302#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
303#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
304#define SCC_GSMRL_TEND ((uint)0x00040000)
305#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
306#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
307#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
308#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
309#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
310#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
311#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
312#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
313#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
314#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
315#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
316#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
317#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
318#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
319#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
320#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
321#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
322#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
323#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
324#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
325#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
326#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
327#define SCC_GSMRL_ENR ((uint)0x00000020)
328#define SCC_GSMRL_ENT ((uint)0x00000010)
329#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
330#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
331#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
332#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
333#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
334#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
335#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
336#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
337#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
338#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
339
340#define SCC_TODR_TOD ((ushort)0x8000)
341
342/* SCC Event and Mask register.
343*/
344#define SCCM_TXE ((unsigned char)0x10)
345#define SCCM_BSY ((unsigned char)0x04)
346#define SCCM_TX ((unsigned char)0x02)
347#define SCCM_RX ((unsigned char)0x01)
348
349typedef struct scc_param {
350 ushort scc_rbase; /* Rx Buffer descriptor base address */
351 ushort scc_tbase; /* Tx Buffer descriptor base address */
352 u_char scc_rfcr; /* Rx function code */
353 u_char scc_tfcr; /* Tx function code */
354 ushort scc_mrblr; /* Max receive buffer length */
355 uint scc_rstate; /* Internal */
356 uint scc_idp; /* Internal */
357 ushort scc_rbptr; /* Internal */
358 ushort scc_ibc; /* Internal */
359 uint scc_rxtmp; /* Internal */
360 uint scc_tstate; /* Internal */
361 uint scc_tdp; /* Internal */
362 ushort scc_tbptr; /* Internal */
363 ushort scc_tbc; /* Internal */
364 uint scc_txtmp; /* Internal */
365 uint scc_rcrc; /* Internal */
366 uint scc_tcrc; /* Internal */
367} sccp_t;
368
369/* CPM Ethernet through SCC1.
370 */
371typedef struct scc_enet {
372 sccp_t sen_genscc;
373 uint sen_cpres; /* Preset CRC */
374 uint sen_cmask; /* Constant mask for CRC */
375 uint sen_crcec; /* CRC Error counter */
376 uint sen_alec; /* alignment error counter */
377 uint sen_disfc; /* discard frame counter */
378 ushort sen_pads; /* Tx short frame pad character */
379 ushort sen_retlim; /* Retry limit threshold */
380 ushort sen_retcnt; /* Retry limit counter */
381 ushort sen_maxflr; /* maximum frame length register */
382 ushort sen_minflr; /* minimum frame length register */
383 ushort sen_maxd1; /* maximum DMA1 length */
384 ushort sen_maxd2; /* maximum DMA2 length */
385 ushort sen_maxd; /* Rx max DMA */
386 ushort sen_dmacnt; /* Rx DMA counter */
387 ushort sen_maxb; /* Max BD byte count */
388 ushort sen_gaddr1; /* Group address filter */
389 ushort sen_gaddr2;
390 ushort sen_gaddr3;
391 ushort sen_gaddr4;
392 uint sen_tbuf0data0; /* Save area 0 - current frame */
393 uint sen_tbuf0data1; /* Save area 1 - current frame */
394 uint sen_tbuf0rba; /* Internal */
395 uint sen_tbuf0crc; /* Internal */
396 ushort sen_tbuf0bcnt; /* Internal */
397 ushort sen_paddrh; /* physical address (MSB) */
398 ushort sen_paddrm;
399 ushort sen_paddrl; /* physical address (LSB) */
400 ushort sen_pper; /* persistence */
401 ushort sen_rfbdptr; /* Rx first BD pointer */
402 ushort sen_tfbdptr; /* Tx first BD pointer */
403 ushort sen_tlbdptr; /* Tx last BD pointer */
404 uint sen_tbuf1data0; /* Save area 0 - current frame */
405 uint sen_tbuf1data1; /* Save area 1 - current frame */
406 uint sen_tbuf1rba; /* Internal */
407 uint sen_tbuf1crc; /* Internal */
408 ushort sen_tbuf1bcnt; /* Internal */
409 ushort sen_txlen; /* Tx Frame length counter */
410 ushort sen_iaddr1; /* Individual address filter */
411 ushort sen_iaddr2;
412 ushort sen_iaddr3;
413 ushort sen_iaddr4;
414 ushort sen_boffcnt; /* Backoff counter */
415
416 /* NOTE: Some versions of the manual have the following items
417 * incorrectly documented. Below is the proper order.
418 */
419 ushort sen_taddrh; /* temp address (MSB) */
420 ushort sen_taddrm;
421 ushort sen_taddrl; /* temp address (LSB) */
422} scc_enet_t;
423
424
425/* SCC Event register as used by Ethernet.
426*/
427#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
428#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
429#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
430#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
431#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
432#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
433
434/* SCC Mode Register (PSMR) as used by Ethernet.
435*/
436#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
437#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
438#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
439#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
440#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
441#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
442#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
443#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
444#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
445#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
446#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
447#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
448#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
449
450/* Buffer descriptor control/status used by Ethernet receive.
451 * Common to SCC and FCC.
452 */
453#define BD_ENET_RX_EMPTY ((ushort)0x8000)
454#define BD_ENET_RX_WRAP ((ushort)0x2000)
455#define BD_ENET_RX_INTR ((ushort)0x1000)
456#define BD_ENET_RX_LAST ((ushort)0x0800)
457#define BD_ENET_RX_FIRST ((ushort)0x0400)
458#define BD_ENET_RX_MISS ((ushort)0x0100)
459#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
460#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
461#define BD_ENET_RX_LG ((ushort)0x0020)
462#define BD_ENET_RX_NO ((ushort)0x0010)
463#define BD_ENET_RX_SH ((ushort)0x0008)
464#define BD_ENET_RX_CR ((ushort)0x0004)
465#define BD_ENET_RX_OV ((ushort)0x0002)
466#define BD_ENET_RX_CL ((ushort)0x0001)
467#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
468
469/* Buffer descriptor control/status used by Ethernet transmit.
470 * Common to SCC and FCC.
471 */
472#define BD_ENET_TX_READY ((ushort)0x8000)
473#define BD_ENET_TX_PAD ((ushort)0x4000)
474#define BD_ENET_TX_WRAP ((ushort)0x2000)
475#define BD_ENET_TX_INTR ((ushort)0x1000)
476#define BD_ENET_TX_LAST ((ushort)0x0800)
477#define BD_ENET_TX_TC ((ushort)0x0400)
478#define BD_ENET_TX_DEF ((ushort)0x0200)
479#define BD_ENET_TX_HB ((ushort)0x0100)
480#define BD_ENET_TX_LC ((ushort)0x0080)
481#define BD_ENET_TX_RL ((ushort)0x0040)
482#define BD_ENET_TX_RCMASK ((ushort)0x003c)
483#define BD_ENET_TX_UN ((ushort)0x0002)
484#define BD_ENET_TX_CSL ((ushort)0x0001)
485#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
486
487/* SCC as UART
488*/
489typedef struct scc_uart {
490 sccp_t scc_genscc;
491 uint scc_res1; /* Reserved */
492 uint scc_res2; /* Reserved */
493 ushort scc_maxidl; /* Maximum idle chars */
494 ushort scc_idlc; /* temp idle counter */
495 ushort scc_brkcr; /* Break count register */
496 ushort scc_parec; /* receive parity error counter */
497 ushort scc_frmec; /* receive framing error counter */
498 ushort scc_nosec; /* receive noise counter */
499 ushort scc_brkec; /* receive break condition counter */
500 ushort scc_brkln; /* last received break length */
501 ushort scc_uaddr1; /* UART address character 1 */
502 ushort scc_uaddr2; /* UART address character 2 */
503 ushort scc_rtemp; /* Temp storage */
504 ushort scc_toseq; /* Transmit out of sequence char */
505 ushort scc_char1; /* control character 1 */
506 ushort scc_char2; /* control character 2 */
507 ushort scc_char3; /* control character 3 */
508 ushort scc_char4; /* control character 4 */
509 ushort scc_char5; /* control character 5 */
510 ushort scc_char6; /* control character 6 */
511 ushort scc_char7; /* control character 7 */
512 ushort scc_char8; /* control character 8 */
513 ushort scc_rccm; /* receive control character mask */
514 ushort scc_rccr; /* receive control character register */
515 ushort scc_rlbc; /* receive last break character */
516} scc_uart_t;
517
518/* SCC Event and Mask registers when it is used as a UART.
519*/
520#define UART_SCCM_GLR ((ushort)0x1000)
521#define UART_SCCM_GLT ((ushort)0x0800)
522#define UART_SCCM_AB ((ushort)0x0200)
523#define UART_SCCM_IDL ((ushort)0x0100)
524#define UART_SCCM_GRA ((ushort)0x0080)
525#define UART_SCCM_BRKE ((ushort)0x0040)
526#define UART_SCCM_BRKS ((ushort)0x0020)
527#define UART_SCCM_CCR ((ushort)0x0008)
528#define UART_SCCM_BSY ((ushort)0x0004)
529#define UART_SCCM_TX ((ushort)0x0002)
530#define UART_SCCM_RX ((ushort)0x0001)
531
532/* The SCC PSMR when used as a UART.
533*/
534#define SCU_PSMR_FLC ((ushort)0x8000)
535#define SCU_PSMR_SL ((ushort)0x4000)
536#define SCU_PSMR_CL ((ushort)0x3000)
537#define SCU_PSMR_UM ((ushort)0x0c00)
538#define SCU_PSMR_FRZ ((ushort)0x0200)
539#define SCU_PSMR_RZS ((ushort)0x0100)
540#define SCU_PSMR_SYN ((ushort)0x0080)
541#define SCU_PSMR_DRT ((ushort)0x0040)
542#define SCU_PSMR_PEN ((ushort)0x0010)
543#define SCU_PSMR_RPM ((ushort)0x000c)
544#define SCU_PSMR_REVP ((ushort)0x0008)
545#define SCU_PSMR_TPM ((ushort)0x0003)
546#define SCU_PSMR_TEVP ((ushort)0x0002)
547
548/* CPM Transparent mode SCC.
549 */
550typedef struct scc_trans {
551 sccp_t st_genscc;
552 uint st_cpres; /* Preset CRC */
553 uint st_cmask; /* Constant mask for CRC */
554} scc_trans_t;
555
556#define BD_SCC_TX_LAST ((ushort)0x0800)
557
558/* How about some FCCs.....
559*/
560#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
561#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
562#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
563#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
564#define FCC_GFMR_TCI ((uint)0x20000000)
565#define FCC_GFMR_TRX ((uint)0x10000000)
566#define FCC_GFMR_TTX ((uint)0x08000000)
567#define FCC_GFMR_TTX ((uint)0x08000000)
568#define FCC_GFMR_CDP ((uint)0x04000000)
569#define FCC_GFMR_CTSP ((uint)0x02000000)
570#define FCC_GFMR_CDS ((uint)0x01000000)
571#define FCC_GFMR_CTSS ((uint)0x00800000)
572#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
573#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
574#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
575#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
576#define FCC_GFMR_RTSM ((uint)0x00002000)
577#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
578#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
579#define FCC_GFMR_REVD ((uint)0x00000400)
580#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
581#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
582#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
583#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
584#define FCC_GFMR_ENR ((uint)0x00000020)
585#define FCC_GFMR_ENT ((uint)0x00000010)
586#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
587#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
588#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
589
590/* Generic FCC parameter ram.
591*/
592typedef struct fcc_param {
593 ushort fcc_riptr; /* Rx Internal temp pointer */
594 ushort fcc_tiptr; /* Tx Internal temp pointer */
595 ushort fcc_res1;
596 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
597 uint fcc_rstate; /* Upper byte is Func code, must be set */
598 uint fcc_rbase; /* Receive BD base */
599 ushort fcc_rbdstat; /* RxBD status */
600 ushort fcc_rbdlen; /* RxBD down counter */
601 uint fcc_rdptr; /* RxBD internal data pointer */
602 uint fcc_tstate; /* Upper byte is Func code, must be set */
603 uint fcc_tbase; /* Transmit BD base */
604 ushort fcc_tbdstat; /* TxBD status */
605 ushort fcc_tbdlen; /* TxBD down counter */
606 uint fcc_tdptr; /* TxBD internal data pointer */
607 uint fcc_rbptr; /* Rx BD Internal buf pointer */
608 uint fcc_tbptr; /* Tx BD Internal buf pointer */
609 uint fcc_rcrc; /* Rx temp CRC */
610 uint fcc_res2;
611 uint fcc_tcrc; /* Tx temp CRC */
612} fccp_t;
613
614
615/* Ethernet controller through FCC.
616*/
617typedef struct fcc_enet {
618 fccp_t fen_genfcc;
619 uint fen_statbuf; /* Internal status buffer */
620 uint fen_camptr; /* CAM address */
621 uint fen_cmask; /* Constant mask for CRC */
622 uint fen_cpres; /* Preset CRC */
623 uint fen_crcec; /* CRC Error counter */
624 uint fen_alec; /* alignment error counter */
625 uint fen_disfc; /* discard frame counter */
626 ushort fen_retlim; /* Retry limit */
627 ushort fen_retcnt; /* Retry counter */
628 ushort fen_pper; /* Persistence */
629 ushort fen_boffcnt; /* backoff counter */
630 uint fen_gaddrh; /* Group address filter, high 32-bits */
631 uint fen_gaddrl; /* Group address filter, low 32-bits */
632 ushort fen_tfcstat; /* out of sequence TxBD */
633 ushort fen_tfclen;
634 uint fen_tfcptr;
635 ushort fen_mflr; /* Maximum frame length (1518) */
636 ushort fen_paddrh; /* MAC address */
637 ushort fen_paddrm;
638 ushort fen_paddrl;
639 ushort fen_ibdcount; /* Internal BD counter */
640 ushort fen_ibdstart; /* Internal BD start pointer */
641 ushort fen_ibdend; /* Internal BD end pointer */
642 ushort fen_txlen; /* Internal Tx frame length counter */
643 uint fen_ibdbase[8]; /* Internal use */
644 uint fen_iaddrh; /* Individual address filter */
645 uint fen_iaddrl;
646 ushort fen_minflr; /* Minimum frame length (64) */
647 ushort fen_taddrh; /* Filter transfer MAC address */
648 ushort fen_taddrm;
649 ushort fen_taddrl;
650 ushort fen_padptr; /* Pointer to pad byte buffer */
651 ushort fen_cftype; /* control frame type */
652 ushort fen_cfrange; /* control frame range */
653 ushort fen_maxb; /* maximum BD count */
654 ushort fen_maxd1; /* Max DMA1 length (1520) */
655 ushort fen_maxd2; /* Max DMA2 length (1520) */
656 ushort fen_maxd; /* internal max DMA count */
657 ushort fen_dmacnt; /* internal DMA counter */
658 uint fen_octc; /* Total octect counter */
659 uint fen_colc; /* Total collision counter */
660 uint fen_broc; /* Total broadcast packet counter */
661 uint fen_mulc; /* Total multicast packet count */
662 uint fen_uspc; /* Total packets < 64 bytes */
663 uint fen_frgc; /* Total packets < 64 bytes with errors */
664 uint fen_ospc; /* Total packets > 1518 */
665 uint fen_jbrc; /* Total packets > 1518 with errors */
666 uint fen_p64c; /* Total packets == 64 bytes */
667 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
668 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
669 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
670 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
671 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
672 uint fen_cambuf; /* Internal CAM buffer poiner */
673 ushort fen_rfthr; /* Received frames threshold */
674 ushort fen_rfcnt; /* Received frames count */
675} fcc_enet_t;
676
677/* FCC Event/Mask register as used by Ethernet.
678*/
679#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
680#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
681#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
682#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
683#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
684#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
685#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
686#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
687
688/* FCC Mode Register (FPSMR) as used by Ethernet.
689*/
690#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
691#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
692#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
693#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
694#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
695#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
696#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
697#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
698#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
699#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
700#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
701#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
702#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
703
704/* IIC parameter RAM.
705*/
706typedef struct iic {
707 ushort iic_rbase; /* Rx Buffer descriptor base address */
708 ushort iic_tbase; /* Tx Buffer descriptor base address */
709 u_char iic_rfcr; /* Rx function code */
710 u_char iic_tfcr; /* Tx function code */
711 ushort iic_mrblr; /* Max receive buffer length */
712 uint iic_rstate; /* Internal */
713 uint iic_rdp; /* Internal */
714 ushort iic_rbptr; /* Internal */
715 ushort iic_rbc; /* Internal */
716 uint iic_rxtmp; /* Internal */
717 uint iic_tstate; /* Internal */
718 uint iic_tdp; /* Internal */
719 ushort iic_tbptr; /* Internal */
720 ushort iic_tbc; /* Internal */
721 uint iic_txtmp; /* Internal */
722} iic_t;
723
724/* SPI parameter RAM.
725*/
726typedef struct spi {
727 ushort spi_rbase; /* Rx Buffer descriptor base address */
728 ushort spi_tbase; /* Tx Buffer descriptor base address */
729 u_char spi_rfcr; /* Rx function code */
730 u_char spi_tfcr; /* Tx function code */
731 ushort spi_mrblr; /* Max receive buffer length */
732 uint spi_rstate; /* Internal */
733 uint spi_rdp; /* Internal */
734 ushort spi_rbptr; /* Internal */
735 ushort spi_rbc; /* Internal */
736 uint spi_rxtmp; /* Internal */
737 uint spi_tstate; /* Internal */
738 uint spi_tdp; /* Internal */
739 ushort spi_tbptr; /* Internal */
740 ushort spi_tbc; /* Internal */
741 uint spi_txtmp; /* Internal */
742 uint spi_res; /* Tx temp. */
743 uint spi_res1[4]; /* SDMA temp. */
744} spi_t;
745
746/* SPI Mode register.
747*/
748#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
749#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
750#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
751#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
752#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
753#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
754#define SPMODE_EN ((ushort)0x0100) /* Enable */
755#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
756#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
757
758#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
759#define SPMODE_PM(x) ((x) &0xF)
760
761#define SPI_EB ((u_char)0x10) /* big endian byte order */
762
763#define BD_IIC_START ((ushort)0x0400)
764
765/* IDMA parameter RAM
766*/
767typedef struct idma {
768 ushort ibase; /* IDMA buffer descriptor table base address */
769 ushort dcm; /* DMA channel mode */
770 ushort ibdptr; /* IDMA current buffer descriptor pointer */
771 ushort dpr_buf; /* IDMA transfer buffer base address */
772 ushort buf_inv; /* internal buffer inventory */
773 ushort ss_max; /* steady-state maximum transfer size */
774 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
775 ushort sts; /* source transfer size */
776 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
777 ushort seob; /* source end of burst */
778 ushort deob; /* destination end of burst */
779 ushort dts; /* destination transfer size */
780 ushort ret_add; /* return address when working in ERM=1 mode */
781 ushort res0; /* reserved */
782 uint bd_cnt; /* internal byte count */
783 uint s_ptr; /* source internal data pointer */
784 uint d_ptr; /* destination internal data pointer */
785 uint istate; /* internal state */
786 u_char res1[20]; /* pad to 64-byte length */
787} idma_t;
788
789/* DMA channel mode bit fields
790*/
791#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
792#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
793#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
794#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
795#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
796#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
797#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
798#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
799#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
800#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
801#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
802#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
803#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
804#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
805#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
806#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
807#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
808#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
809
810/* IDMA Buffer Descriptors
811*/
812typedef struct idma_bd {
813 uint flags;
814 uint len; /* data length */
815 uint src; /* source data buffer pointer */
816 uint dst; /* destination data buffer pointer */
817} idma_bd_t;
818
819/* IDMA buffer descriptor flag bit fields
820*/
821#define IDMA_BD_V ((uint)0x80000000) /* valid */
822#define IDMA_BD_W ((uint)0x20000000) /* wrap */
823#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
824#define IDMA_BD_L ((uint)0x08000000) /* last */
825#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
826#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
827#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
828#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
829#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
830#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
831#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
832#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
833#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
834#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
835#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
836
837/* per-channel IDMA registers
838*/
839typedef struct im_idma {
840 u_char idsr; /* IDMAn event status register */
841 u_char res0[3];
842 u_char idmr; /* IDMAn event mask register */
843 u_char res1[3];
844} im_idma_t;
845
846/* IDMA event register bit fields
847*/
848#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
849#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
850#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
851#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
852
853/* RISC Controller Configuration Register (RCCR) bit fields
854*/
855#define RCCR_TIME ((uint)0x80000000) /* timer enable */
856#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
857#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
858#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
859#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
860#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
861#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
862#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
863#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
864#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
865#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
866#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
867#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
868#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
869#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
870#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
871#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
872#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
873#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
874#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
875#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
876#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
877#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
878#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
879#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
880#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
881#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
882#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
883#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
884#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
885#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
886#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
887#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
888#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
889#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
890#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
891#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
892#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
893
894/*-----------------------------------------------------------------------
895 * CMXFCR - CMX FCC Clock Route Register
896 */
897#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
898#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
899#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
900#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
901#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
902#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
903#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
904#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
905#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
906
907#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
908#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
909#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
910#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
911#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
912#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
913#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
914#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
915
916#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
917#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
918#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
919#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
920#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
921#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
922#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
923#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
924
925#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
926#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
927#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
928#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
929#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
930#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
931#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
932#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
933
934#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
935#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
936#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
937#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
938#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
939#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
940#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
941#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
942
943#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
944#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
945#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
946#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
947#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
948#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
949#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
950#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
951
952#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
953#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
954#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
955#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
956#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
957#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
958#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
959#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
960
961/*-----------------------------------------------------------------------
962 * CMXSCR - CMX SCC Clock Route Register
963 */
964#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
965#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
966#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
967#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
968#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
969#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
970#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
971#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
972#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
973#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
974#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
975#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
976#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
977#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
978#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
979#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
980
981#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
982#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
983#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
984#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
985#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
986#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
987#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
988#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
989
990#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
991#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
992#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
993#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
994#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
995#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
996#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
997#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
998
999#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
1000#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
1001#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
1002#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
1003#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
1004#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
1005#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
1006#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
1007
1008#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
1009#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
1010#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
1011#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
1012#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
1013#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
1014#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
1015#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
1016
1017#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
1018#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
1019#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
1020#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
1021#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
1022#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
1023#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
1024#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
1025
1026#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
1027#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
1028#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
1029#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
1030#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
1031#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
1032#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
1033#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
1034
1035#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
1036#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
1037#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
1038#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
1039#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
1040#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
1041#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
1042#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
1043
1044#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
1045#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
1046#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
1047#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
1048#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
1049#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
1050#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
1051#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
1052
a6dbba77
VB		 1053/*-----------------------------------------------------------------------
1054 * SIUMCR - SIU Module Configuration Register 4-31
1055 */
1056#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
1057#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
1058#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
1059#define SIUMCR_CDIS 0x10000000 /* Core Disable */
1060#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
1061#define SIUMCR_DPPC01 0x04000000 /* - " - */
1062#define SIUMCR_DPPC10 0x08000000 /* - " - */
1063#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1064#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1065#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1066#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1067#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1068#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1069#define SIUMCR_LBPC01 0x00400000 /* - " - */
1070#define SIUMCR_LBPC10 0x00800000 /* - " - */
1071#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1072#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1073#define SIUMCR_APPC01 0x00100000 /* - " - */
1074#define SIUMCR_APPC10 0x00200000 /* - " - */
1075#define SIUMCR_APPC11 0x00300000 /* - " - */
1076#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1077#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1078#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1079#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1080#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1081#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1082#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1083#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1084#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1085#define SIUMCR_MMR01 0x00004000 /* - " - */
1086#define SIUMCR_MMR10 0x00008000 /* - " - */
1087#define SIUMCR_MMR11 0x0000c000 /* - " - */
1088#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1089
1090/*-----------------------------------------------------------------------
1091 * SCCR - System Clock Control Register 9-8
1092*/
1093#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1094#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1095#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1096#define SCCR_PCIDF_SHIFT 3
1097
1461b4ea
VB		 1098#ifndef CPM_IMMR_OFFSET
1099#define CPM_IMMR_OFFSET 0x101a8
1100#endif
a6dbba77 1101
966cc04b
VB		 1102#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1103
2ca2d5e8
VB		 1104/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1105 * in order to use clock-computing stuff below for the FCC x
1106 */
1107
1108/* Automatically generates register configurations */
1109#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1110
1111#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1112#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1113#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1114#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1115#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1116#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1117
1118#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1119#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1120#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1121#define CMX1_CLK_MASK ((uint)0xff000000)
1122
1123#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1124#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1125#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1126#define CMX2_CLK_MASK ((uint)0x00ff0000)
1127
1128#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1129#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1130#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1131#define CMX3_CLK_MASK ((uint)0x0000ff00)
1132
1133#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1134#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1135
1136#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1137
1138/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1139 * but there is little variation among the choices.
1140 */
1141#define PA1_COL 0x00000001U
1142#define PA1_CRS 0x00000002U
1143#define PA1_TXER 0x00000004U
1144#define PA1_TXEN 0x00000008U
1145#define PA1_RXDV 0x00000010U
1146#define PA1_RXER 0x00000020U
1147#define PA1_TXDAT 0x00003c00U
1148#define PA1_RXDAT 0x0003c000U
1149#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1150#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1151 PA1_RXDV | PA1_RXER)
1152#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1153#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1154
1155
1156/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1157 * but there is little variation among the choices.
1158 */
1159#define PB2_TXER 0x00000001U
1160#define PB2_RXDV 0x00000002U
1161#define PB2_TXEN 0x00000004U
1162#define PB2_RXER 0x00000008U
1163#define PB2_COL 0x00000010U
1164#define PB2_CRS 0x00000020U
1165#define PB2_TXDAT 0x000003c0U
1166#define PB2_RXDAT 0x00003c00U
1167#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1168 PB2_RXER | PB2_RXDV | PB2_TXER)
1169#define PB2_PSORB1 (PB2_TXEN)
1170#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1171#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1172
1173
1174/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1175 * but there is little variation among the choices.
1176 */
1177#define PB3_RXDV 0x00004000U
1178#define PB3_RXER 0x00008000U
1179#define PB3_TXER 0x00010000U
1180#define PB3_TXEN 0x00020000U
1181#define PB3_COL 0x00040000U
1182#define PB3_CRS 0x00080000U
1183#define PB3_TXDAT 0x0f000000U
1184#define PC3_TXDAT 0x00000010U
1185#define PB3_RXDAT 0x00f00000U
1186#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1187 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1188#define PB3_PSORB1 0
1189#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1190#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1191#define PC3_DIRC1 (PC3_TXDAT)
1192
1193/* Handy macro to specify mem for FCCs*/
1194#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1195#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1196#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
b0c110b4 1197#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
2ca2d5e8 1198
d3465c92
VB		 1199/* Clocks and GRG's */
1200
1201enum cpm_clk_dir {
1202 CPM_CLK_RX,
1203 CPM_CLK_TX,
1204 CPM_CLK_RTX
1205};
1206
1207enum cpm_clk_target {
1208 CPM_CLK_SCC1,
1209 CPM_CLK_SCC2,
1210 CPM_CLK_SCC3,
1211 CPM_CLK_SCC4,
1212 CPM_CLK_FCC1,
1213 CPM_CLK_FCC2,
1214 CPM_CLK_FCC3
1215};
1216
1217enum cpm_clk {
1218 CPM_CLK_NONE = 0,
1219 CPM_BRG1, /* Baud Rate Generator 1 */
1220 CPM_BRG2, /* Baud Rate Generator 2 */
1221 CPM_BRG3, /* Baud Rate Generator 3 */
1222 CPM_BRG4, /* Baud Rate Generator 4 */
1223 CPM_BRG5, /* Baud Rate Generator 5 */
1224 CPM_BRG6, /* Baud Rate Generator 6 */
1225 CPM_BRG7, /* Baud Rate Generator 7 */
1226 CPM_BRG8, /* Baud Rate Generator 8 */
1227 CPM_CLK1, /* Clock 1 */
1228 CPM_CLK2, /* Clock 2 */
1229 CPM_CLK3, /* Clock 3 */
1230 CPM_CLK4, /* Clock 4 */
1231 CPM_CLK5, /* Clock 5 */
1232 CPM_CLK6, /* Clock 6 */
1233 CPM_CLK7, /* Clock 7 */
1234 CPM_CLK8, /* Clock 8 */
1235 CPM_CLK9, /* Clock 9 */
1236 CPM_CLK10, /* Clock 10 */
1237 CPM_CLK11, /* Clock 11 */
1238 CPM_CLK12, /* Clock 12 */
1239 CPM_CLK13, /* Clock 13 */
1240 CPM_CLK14, /* Clock 14 */
1241 CPM_CLK15, /* Clock 15 */
1242 CPM_CLK16, /* Clock 16 */
1243 CPM_CLK17, /* Clock 17 */
1244 CPM_CLK18, /* Clock 18 */
1245 CPM_CLK19, /* Clock 19 */
1246 CPM_CLK20, /* Clock 20 */
1247 CPM_CLK_DUMMY
1248};
1249
1250extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1251
1da177e4
LT		 1252#endif /* __CPM2__ */
1253#endif /* __KERNEL__ */
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