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1da177e4 LT |
1 | /* |
2 | * include/asm-ppc/mpc52xx.h | |
3 | * | |
4 | * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips | |
5 | * May need to be cleaned as the port goes on ... | |
6 | * | |
7 | * | |
8 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9 | * | |
10 | * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> | |
11 | * for the 2.4 kernel. | |
12 | * | |
13 | * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> | |
14 | * Copyright (C) 2003 MontaVista, Software, Inc. | |
15 | * | |
16 | * This file is licensed under the terms of the GNU General Public License | |
17 | * version 2. This program is licensed "as is" without any warranty of any | |
18 | * kind, whether express or implied. | |
19 | */ | |
20 | ||
21 | #ifndef __ASM_MPC52xx_H__ | |
22 | #define __ASM_MPC52xx_H__ | |
23 | ||
24 | #ifndef __ASSEMBLY__ | |
25 | #include <asm/ppcboot.h> | |
26 | #include <asm/types.h> | |
27 | ||
28 | struct pt_regs; | |
29 | #endif /* __ASSEMBLY__ */ | |
30 | ||
31 | ||
f80257a2 SM |
32 | #ifdef CONFIG_PCI |
33 | #define _IO_BASE isa_io_base | |
34 | #define _ISA_MEM_BASE isa_mem_base | |
35 | #define PCI_DRAM_OFFSET pci_dram_offset | |
36 | #else | |
37 | #define _IO_BASE 0 | |
38 | #define _ISA_MEM_BASE 0 | |
39 | #define PCI_DRAM_OFFSET 0 | |
40 | #endif | |
41 | ||
42 | ||
1da177e4 LT |
43 | /* ======================================================================== */ |
44 | /* PPC Sys devices definition */ | |
45 | /* ======================================================================== */ | |
46 | ||
47 | enum ppc_sys_devices { | |
48 | MPC52xx_MSCAN1, | |
49 | MPC52xx_MSCAN2, | |
50 | MPC52xx_SPI, | |
51 | MPC52xx_USB, | |
52 | MPC52xx_BDLC, | |
53 | MPC52xx_PSC1, | |
54 | MPC52xx_PSC2, | |
55 | MPC52xx_PSC3, | |
56 | MPC52xx_PSC4, | |
57 | MPC52xx_PSC5, | |
58 | MPC52xx_PSC6, | |
59 | MPC52xx_FEC, | |
60 | MPC52xx_ATA, | |
61 | MPC52xx_I2C1, | |
62 | MPC52xx_I2C2, | |
75288c78 | 63 | NUM_PPC_SYS_DEVS, |
1da177e4 LT |
64 | }; |
65 | ||
66 | ||
67 | /* ======================================================================== */ | |
68 | /* Main registers/struct addresses */ | |
69 | /* ======================================================================== */ | |
70 | ||
71 | /* MBAR position */ | |
72 | #define MPC52xx_MBAR 0xf0000000 /* Phys address */ | |
73 | #define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */ | |
74 | #define MPC52xx_MBAR_SIZE 0x00010000 | |
75 | ||
76 | #define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x))) | |
77 | #define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x))) | |
78 | ||
79 | /* Registers zone offset/size */ | |
80 | #define MPC52xx_MMAP_CTL_OFFSET 0x0000 | |
81 | #define MPC52xx_MMAP_CTL_SIZE 0x068 | |
82 | #define MPC52xx_SDRAM_OFFSET 0x0100 | |
83 | #define MPC52xx_SDRAM_SIZE 0x010 | |
84 | #define MPC52xx_CDM_OFFSET 0x0200 | |
85 | #define MPC52xx_CDM_SIZE 0x038 | |
86 | #define MPC52xx_INTR_OFFSET 0x0500 | |
87 | #define MPC52xx_INTR_SIZE 0x04c | |
88 | #define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4)) | |
89 | #define MPC52xx_GPT_SIZE 0x010 | |
90 | #define MPC52xx_RTC_OFFSET 0x0800 | |
91 | #define MPC52xx_RTC_SIZE 0x024 | |
92 | #define MPC52xx_GPIO_OFFSET 0x0b00 | |
93 | #define MPC52xx_GPIO_SIZE 0x040 | |
94 | #define MPC52xx_GPIO_WKUP_OFFSET 0x0c00 | |
95 | #define MPC52xx_GPIO_WKUP_SIZE 0x028 | |
96 | #define MPC52xx_PCI_OFFSET 0x0d00 | |
97 | #define MPC52xx_PCI_SIZE 0x100 | |
98 | #define MPC52xx_SDMA_OFFSET 0x1200 | |
99 | #define MPC52xx_SDMA_SIZE 0x100 | |
100 | #define MPC52xx_XLB_OFFSET 0x1f00 | |
101 | #define MPC52xx_XLB_SIZE 0x100 | |
102 | #define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00) | |
103 | #define MPC52xx_PSC_SIZE 0x0a0 | |
104 | ||
105 | /* SRAM used for SDMA */ | |
106 | #define MPC52xx_SRAM_OFFSET 0x8000 | |
107 | #define MPC52xx_SRAM_SIZE 0x4000 | |
108 | ||
109 | ||
110 | /* ======================================================================== */ | |
111 | /* IRQ mapping */ | |
112 | /* ======================================================================== */ | |
113 | /* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change | |
114 | * this | |
115 | */ | |
116 | ||
117 | #define MPC52xx_CRIT_IRQ_NUM 4 | |
118 | #define MPC52xx_MAIN_IRQ_NUM 17 | |
119 | #define MPC52xx_SDMA_IRQ_NUM 17 | |
120 | #define MPC52xx_PERP_IRQ_NUM 23 | |
121 | ||
e21b9f2e | 122 | #define MPC52xx_CRIT_IRQ_BASE 1 |
1da177e4 LT |
123 | #define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM) |
124 | #define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM) | |
125 | #define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM) | |
126 | ||
127 | #define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0) | |
128 | #define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1) | |
129 | #define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2) | |
130 | #define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3) | |
131 | ||
132 | #define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1) | |
133 | #define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2) | |
134 | #define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3) | |
135 | ||
136 | #define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0) | |
137 | #define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1) | |
138 | #define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2) | |
139 | #define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3) | |
140 | #define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4) | |
141 | #define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4) | |
142 | #define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5) | |
143 | #define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6) | |
144 | #define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7) | |
145 | #define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8) | |
146 | #define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9) | |
147 | #define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10) | |
148 | #define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11) | |
149 | #define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12) | |
150 | #define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13) | |
151 | #define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14) | |
152 | #define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15) | |
153 | #define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16) | |
154 | #define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17) | |
155 | #define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18) | |
156 | #define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19) | |
157 | #define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20) | |
158 | #define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21) | |
159 | #define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22) | |
160 | ||
161 | ||
162 | ||
163 | /* ======================================================================== */ | |
164 | /* Structures mapping of some unit register set */ | |
165 | /* ======================================================================== */ | |
166 | ||
167 | #ifndef __ASSEMBLY__ | |
168 | ||
169 | /* Memory Mapping Control */ | |
170 | struct mpc52xx_mmap_ctl { | |
171 | u32 mbar; /* MMAP_CTRL + 0x00 */ | |
172 | ||
173 | u32 cs0_start; /* MMAP_CTRL + 0x04 */ | |
174 | u32 cs0_stop; /* MMAP_CTRL + 0x08 */ | |
175 | u32 cs1_start; /* MMAP_CTRL + 0x0c */ | |
176 | u32 cs1_stop; /* MMAP_CTRL + 0x10 */ | |
177 | u32 cs2_start; /* MMAP_CTRL + 0x14 */ | |
178 | u32 cs2_stop; /* MMAP_CTRL + 0x18 */ | |
179 | u32 cs3_start; /* MMAP_CTRL + 0x1c */ | |
180 | u32 cs3_stop; /* MMAP_CTRL + 0x20 */ | |
181 | u32 cs4_start; /* MMAP_CTRL + 0x24 */ | |
182 | u32 cs4_stop; /* MMAP_CTRL + 0x28 */ | |
183 | u32 cs5_start; /* MMAP_CTRL + 0x2c */ | |
184 | u32 cs5_stop; /* MMAP_CTRL + 0x30 */ | |
185 | ||
186 | u32 sdram0; /* MMAP_CTRL + 0x34 */ | |
187 | u32 sdram1; /* MMAP_CTRL + 0X38 */ | |
188 | ||
189 | u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ | |
190 | ||
191 | u32 boot_start; /* MMAP_CTRL + 0x4c */ | |
192 | u32 boot_stop; /* MMAP_CTRL + 0x50 */ | |
193 | ||
194 | u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ | |
195 | ||
196 | u32 cs6_start; /* MMAP_CTRL + 0x58 */ | |
197 | u32 cs6_stop; /* MMAP_CTRL + 0x5c */ | |
198 | u32 cs7_start; /* MMAP_CTRL + 0x60 */ | |
199 | u32 cs7_stop; /* MMAP_CTRL + 0x64 */ | |
200 | }; | |
201 | ||
202 | /* SDRAM control */ | |
203 | struct mpc52xx_sdram { | |
204 | u32 mode; /* SDRAM + 0x00 */ | |
205 | u32 ctrl; /* SDRAM + 0x04 */ | |
206 | u32 config1; /* SDRAM + 0x08 */ | |
207 | u32 config2; /* SDRAM + 0x0c */ | |
208 | }; | |
209 | ||
210 | /* Interrupt controller */ | |
211 | struct mpc52xx_intr { | |
212 | u32 per_mask; /* INTR + 0x00 */ | |
213 | u32 per_pri1; /* INTR + 0x04 */ | |
214 | u32 per_pri2; /* INTR + 0x08 */ | |
215 | u32 per_pri3; /* INTR + 0x0c */ | |
216 | u32 ctrl; /* INTR + 0x10 */ | |
217 | u32 main_mask; /* INTR + 0x14 */ | |
218 | u32 main_pri1; /* INTR + 0x18 */ | |
219 | u32 main_pri2; /* INTR + 0x1c */ | |
220 | u32 reserved1; /* INTR + 0x20 */ | |
221 | u32 enc_status; /* INTR + 0x24 */ | |
222 | u32 crit_status; /* INTR + 0x28 */ | |
223 | u32 main_status; /* INTR + 0x2c */ | |
224 | u32 per_status; /* INTR + 0x30 */ | |
225 | u32 reserved2; /* INTR + 0x34 */ | |
226 | u32 per_error; /* INTR + 0x38 */ | |
227 | }; | |
228 | ||
229 | /* SDMA */ | |
230 | struct mpc52xx_sdma { | |
231 | u32 taskBar; /* SDMA + 0x00 */ | |
232 | u32 currentPointer; /* SDMA + 0x04 */ | |
233 | u32 endPointer; /* SDMA + 0x08 */ | |
234 | u32 variablePointer;/* SDMA + 0x0c */ | |
235 | ||
236 | u8 IntVect1; /* SDMA + 0x10 */ | |
237 | u8 IntVect2; /* SDMA + 0x11 */ | |
238 | u16 PtdCntrl; /* SDMA + 0x12 */ | |
239 | ||
240 | u32 IntPend; /* SDMA + 0x14 */ | |
241 | u32 IntMask; /* SDMA + 0x18 */ | |
242 | ||
243 | u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ | |
244 | ||
245 | u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */ | |
246 | ||
247 | u32 cReqSelect; /* SDMA + 0x5c */ | |
248 | u32 task_size0; /* SDMA + 0x60 */ | |
249 | u32 task_size1; /* SDMA + 0x64 */ | |
250 | u32 MDEDebug; /* SDMA + 0x68 */ | |
251 | u32 ADSDebug; /* SDMA + 0x6c */ | |
252 | u32 Value1; /* SDMA + 0x70 */ | |
253 | u32 Value2; /* SDMA + 0x74 */ | |
254 | u32 Control; /* SDMA + 0x78 */ | |
255 | u32 Status; /* SDMA + 0x7c */ | |
256 | u32 PTDDebug; /* SDMA + 0x80 */ | |
257 | }; | |
258 | ||
259 | /* GPT */ | |
260 | struct mpc52xx_gpt { | |
261 | u32 mode; /* GPTx + 0x00 */ | |
262 | u32 count; /* GPTx + 0x04 */ | |
263 | u32 pwm; /* GPTx + 0x08 */ | |
264 | u32 status; /* GPTx + 0X0c */ | |
265 | }; | |
266 | ||
267 | /* RTC */ | |
268 | struct mpc52xx_rtc { | |
269 | u32 time_set; /* RTC + 0x00 */ | |
270 | u32 date_set; /* RTC + 0x04 */ | |
271 | u32 stopwatch; /* RTC + 0x08 */ | |
272 | u32 int_enable; /* RTC + 0x0c */ | |
273 | u32 time; /* RTC + 0x10 */ | |
274 | u32 date; /* RTC + 0x14 */ | |
275 | u32 stopwatch_intr; /* RTC + 0x18 */ | |
276 | u32 bus_error; /* RTC + 0x1c */ | |
277 | u32 dividers; /* RTC + 0x20 */ | |
278 | }; | |
279 | ||
280 | /* GPIO */ | |
281 | struct mpc52xx_gpio { | |
282 | u32 port_config; /* GPIO + 0x00 */ | |
283 | u32 simple_gpioe; /* GPIO + 0x04 */ | |
284 | u32 simple_ode; /* GPIO + 0x08 */ | |
285 | u32 simple_ddr; /* GPIO + 0x0c */ | |
286 | u32 simple_dvo; /* GPIO + 0x10 */ | |
287 | u32 simple_ival; /* GPIO + 0x14 */ | |
288 | u8 outo_gpioe; /* GPIO + 0x18 */ | |
289 | u8 reserved1[3]; /* GPIO + 0x19 */ | |
290 | u8 outo_dvo; /* GPIO + 0x1c */ | |
291 | u8 reserved2[3]; /* GPIO + 0x1d */ | |
292 | u8 sint_gpioe; /* GPIO + 0x20 */ | |
293 | u8 reserved3[3]; /* GPIO + 0x21 */ | |
294 | u8 sint_ode; /* GPIO + 0x24 */ | |
295 | u8 reserved4[3]; /* GPIO + 0x25 */ | |
296 | u8 sint_ddr; /* GPIO + 0x28 */ | |
297 | u8 reserved5[3]; /* GPIO + 0x29 */ | |
298 | u8 sint_dvo; /* GPIO + 0x2c */ | |
299 | u8 reserved6[3]; /* GPIO + 0x2d */ | |
300 | u8 sint_inten; /* GPIO + 0x30 */ | |
301 | u8 reserved7[3]; /* GPIO + 0x31 */ | |
302 | u16 sint_itype; /* GPIO + 0x34 */ | |
303 | u16 reserved8; /* GPIO + 0x36 */ | |
304 | u8 gpio_control; /* GPIO + 0x38 */ | |
305 | u8 reserved9[3]; /* GPIO + 0x39 */ | |
306 | u8 sint_istat; /* GPIO + 0x3c */ | |
307 | u8 sint_ival; /* GPIO + 0x3d */ | |
308 | u8 bus_errs; /* GPIO + 0x3e */ | |
309 | u8 reserved10; /* GPIO + 0x3f */ | |
310 | }; | |
311 | ||
312 | #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4 | |
313 | #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5 | |
314 | #define MPC52xx_GPIO_PCI_DIS (1<<15) | |
315 | ||
316 | /* GPIO with WakeUp*/ | |
317 | struct mpc52xx_gpio_wkup { | |
318 | u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */ | |
319 | u8 reserved1[3]; /* GPIO_WKUP + 0x03 */ | |
320 | u8 wkup_ode; /* GPIO_WKUP + 0x04 */ | |
321 | u8 reserved2[3]; /* GPIO_WKUP + 0x05 */ | |
322 | u8 wkup_ddr; /* GPIO_WKUP + 0x08 */ | |
323 | u8 reserved3[3]; /* GPIO_WKUP + 0x09 */ | |
324 | u8 wkup_dvo; /* GPIO_WKUP + 0x0C */ | |
325 | u8 reserved4[3]; /* GPIO_WKUP + 0x0D */ | |
326 | u8 wkup_inten; /* GPIO_WKUP + 0x10 */ | |
327 | u8 reserved5[3]; /* GPIO_WKUP + 0x11 */ | |
328 | u8 wkup_iinten; /* GPIO_WKUP + 0x14 */ | |
329 | u8 reserved6[3]; /* GPIO_WKUP + 0x15 */ | |
330 | u16 wkup_itype; /* GPIO_WKUP + 0x18 */ | |
331 | u8 reserved7[2]; /* GPIO_WKUP + 0x1A */ | |
332 | u8 wkup_maste; /* GPIO_WKUP + 0x1C */ | |
333 | u8 reserved8[3]; /* GPIO_WKUP + 0x1D */ | |
334 | u8 wkup_ival; /* GPIO_WKUP + 0x20 */ | |
335 | u8 reserved9[3]; /* GPIO_WKUP + 0x21 */ | |
336 | u8 wkup_istat; /* GPIO_WKUP + 0x24 */ | |
337 | u8 reserved10[3]; /* GPIO_WKUP + 0x25 */ | |
338 | }; | |
339 | ||
340 | /* XLB Bus control */ | |
341 | struct mpc52xx_xlb { | |
342 | u8 reserved[0x40]; | |
343 | u32 config; /* XLB + 0x40 */ | |
344 | u32 version; /* XLB + 0x44 */ | |
345 | u32 status; /* XLB + 0x48 */ | |
346 | u32 int_enable; /* XLB + 0x4c */ | |
347 | u32 addr_capture; /* XLB + 0x50 */ | |
348 | u32 bus_sig_capture; /* XLB + 0x54 */ | |
349 | u32 addr_timeout; /* XLB + 0x58 */ | |
350 | u32 data_timeout; /* XLB + 0x5c */ | |
351 | u32 bus_act_timeout; /* XLB + 0x60 */ | |
352 | u32 master_pri_enable; /* XLB + 0x64 */ | |
353 | u32 master_priority; /* XLB + 0x68 */ | |
354 | u32 base_address; /* XLB + 0x6c */ | |
355 | u32 snoop_window; /* XLB + 0x70 */ | |
356 | }; | |
357 | ||
1f5e3b02 | 358 | #define MPC52xx_XLB_CFG_PLDIS (1 << 31) |
1da177e4 LT |
359 | #define MPC52xx_XLB_CFG_SNOOP (1 << 15) |
360 | ||
361 | /* Clock Distribution control */ | |
362 | struct mpc52xx_cdm { | |
363 | u32 jtag_id; /* CDM + 0x00 reg0 read only */ | |
364 | u32 rstcfg; /* CDM + 0x04 reg1 read only */ | |
365 | u32 breadcrumb; /* CDM + 0x08 reg2 */ | |
366 | ||
367 | u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */ | |
368 | u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */ | |
369 | u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */ | |
370 | u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */ | |
371 | ||
372 | u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */ | |
373 | u8 fd_enable; /* CDM + 0x11 reg4 byte1 */ | |
374 | u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */ | |
375 | ||
376 | u32 clk_enables; /* CDM + 0x14 reg5 */ | |
377 | ||
378 | u8 osc_disable; /* CDM + 0x18 reg6 byte0 */ | |
379 | u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */ | |
380 | ||
381 | u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */ | |
382 | u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */ | |
383 | u8 reserved1; /* CDM + 0x1e reg7 byte2 */ | |
384 | u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */ | |
385 | ||
386 | u8 soft_reset; /* CDM + 0x20 u8 byte0 */ | |
387 | u8 no_ckstp; /* CDM + 0x21 u8 byte0 */ | |
388 | u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */ | |
389 | ||
390 | u8 pll_lock; /* CDM + 0x24 reg9 byte0 */ | |
391 | u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */ | |
392 | u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */ | |
393 | u8 reserved3; /* CDM + 0x27 reg9 byte3 */ | |
394 | ||
395 | u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */ | |
396 | u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */ | |
397 | ||
398 | u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */ | |
399 | u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */ | |
400 | ||
401 | u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */ | |
402 | u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */ | |
403 | ||
404 | u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */ | |
405 | u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */ | |
406 | }; | |
407 | ||
408 | #endif /* __ASSEMBLY__ */ | |
409 | ||
410 | ||
411 | /* ========================================================================= */ | |
412 | /* Prototypes for MPC52xx syslib */ | |
413 | /* ========================================================================= */ | |
414 | ||
415 | #ifndef __ASSEMBLY__ | |
416 | ||
417 | extern void mpc52xx_init_irq(void); | |
418 | extern int mpc52xx_get_irq(struct pt_regs *regs); | |
419 | ||
420 | extern unsigned long mpc52xx_find_end_of_memory(void); | |
421 | extern void mpc52xx_set_bat(void); | |
422 | extern void mpc52xx_map_io(void); | |
423 | extern void mpc52xx_restart(char *cmd); | |
424 | extern void mpc52xx_halt(void); | |
425 | extern void mpc52xx_power_off(void); | |
426 | extern void mpc52xx_progress(char *s, unsigned short hex); | |
427 | extern void mpc52xx_calibrate_decr(void); | |
428 | ||
429 | extern void mpc52xx_find_bridges(void); | |
430 | ||
1f5e3b02 SM |
431 | extern void mpc52xx_setup_cpu(void); |
432 | ||
433 | ||
1da177e4 LT |
434 | |
435 | /* Matching of PSC function */ | |
436 | struct mpc52xx_psc_func { | |
437 | int id; | |
438 | char *func; | |
439 | }; | |
440 | ||
441 | extern int mpc52xx_match_psc_function(int psc_idx, const char *func); | |
442 | extern struct mpc52xx_psc_func mpc52xx_psc_functions[]; | |
443 | /* This array is to be defined in platform file */ | |
444 | ||
445 | #endif /* __ASSEMBLY__ */ | |
446 | ||
447 | ||
448 | /* ========================================================================= */ | |
449 | /* Platform configuration */ | |
450 | /* ========================================================================= */ | |
451 | ||
452 | /* The U-Boot platform information struct */ | |
453 | extern bd_t __res; | |
454 | ||
455 | /* Platform options */ | |
456 | #if defined(CONFIG_LITE5200) | |
457 | #include <platforms/lite5200.h> | |
458 | #endif | |
459 | ||
460 | ||
461 | #endif /* __ASM_MPC52xx_H__ */ |