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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/pgtable.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com) | |
7 | * Ulrich Weigand (weigand@de.ibm.com) | |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
9 | * | |
10 | * Derived from "include/asm-i386/pgtable.h" | |
11 | */ | |
12 | ||
13 | #ifndef _ASM_S390_PGTABLE_H | |
14 | #define _ASM_S390_PGTABLE_H | |
15 | ||
1da177e4 LT |
16 | /* |
17 | * The Linux memory management assumes a three-level page table setup. For | |
18 | * s390 31 bit we "fold" the mid level into the top-level page table, so | |
19 | * that we physically have the same two-level page table as the s390 mmu | |
20 | * expects in 31 bit mode. For s390 64 bit we use three of the five levels | |
21 | * the hardware provides (region first and region second tables are not | |
22 | * used). | |
23 | * | |
24 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
25 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
26 | * into the pgd entry) | |
27 | * | |
28 | * This file contains the functions and defines necessary to modify and use | |
29 | * the S390 page table tree. | |
30 | */ | |
31 | #ifndef __ASSEMBLY__ | |
2dcea57a | 32 | #include <linux/mm_types.h> |
5b7baf05 | 33 | #include <asm/bitops.h> |
1da177e4 LT |
34 | #include <asm/bug.h> |
35 | #include <asm/processor.h> | |
1da177e4 | 36 | |
1da177e4 LT |
37 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
38 | extern void paging_init(void); | |
2b67fc46 | 39 | extern void vmem_map_init(void); |
1da177e4 LT |
40 | |
41 | /* | |
42 | * The S390 doesn't have any external MMU info: the kernel page | |
43 | * tables contain all the necessary information. | |
44 | */ | |
45 | #define update_mmu_cache(vma, address, pte) do { } while (0) | |
46 | ||
47 | /* | |
48 | * ZERO_PAGE is a global shared page that is always zero: used | |
49 | * for zero-mapped memory areas etc.. | |
50 | */ | |
51 | extern char empty_zero_page[PAGE_SIZE]; | |
52 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | |
53 | #endif /* !__ASSEMBLY__ */ | |
54 | ||
55 | /* | |
56 | * PMD_SHIFT determines the size of the area a second-level page | |
57 | * table can map | |
58 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
59 | */ | |
60 | #ifndef __s390x__ | |
146e4b3c MS |
61 | # define PMD_SHIFT 20 |
62 | # define PUD_SHIFT 20 | |
63 | # define PGDIR_SHIFT 20 | |
1da177e4 | 64 | #else /* __s390x__ */ |
146e4b3c | 65 | # define PMD_SHIFT 20 |
190a1d72 | 66 | # define PUD_SHIFT 31 |
5a216a20 | 67 | # define PGDIR_SHIFT 42 |
1da177e4 LT |
68 | #endif /* __s390x__ */ |
69 | ||
70 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
71 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
72 | #define PUD_SIZE (1UL << PUD_SHIFT) |
73 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
74 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
75 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
76 | |
77 | /* | |
78 | * entries per page directory level: the S390 is two-level, so | |
79 | * we don't really have any PMD directory physically. | |
80 | * for S390 segment-table entries are combined to one PGD | |
81 | * that leads to 1024 pte per pgd | |
82 | */ | |
146e4b3c | 83 | #define PTRS_PER_PTE 256 |
1da177e4 | 84 | #ifndef __s390x__ |
146e4b3c | 85 | #define PTRS_PER_PMD 1 |
5a216a20 | 86 | #define PTRS_PER_PUD 1 |
1da177e4 | 87 | #else /* __s390x__ */ |
146e4b3c | 88 | #define PTRS_PER_PMD 2048 |
5a216a20 | 89 | #define PTRS_PER_PUD 2048 |
1da177e4 | 90 | #endif /* __s390x__ */ |
146e4b3c | 91 | #define PTRS_PER_PGD 2048 |
1da177e4 | 92 | |
d455a369 HD |
93 | #define FIRST_USER_ADDRESS 0 |
94 | ||
1da177e4 LT |
95 | #define pte_ERROR(e) \ |
96 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
97 | #define pmd_ERROR(e) \ | |
98 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
99 | #define pud_ERROR(e) \ |
100 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
101 | #define pgd_ERROR(e) \ |
102 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
103 | ||
104 | #ifndef __ASSEMBLY__ | |
105 | /* | |
5fd9c6e2 CB |
106 | * The vmalloc area will always be on the topmost area of the kernel |
107 | * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc, | |
108 | * which should be enough for any sane case. | |
109 | * By putting vmalloc at the top, we maximise the gap between physical | |
110 | * memory and vmalloc to catch misplaced memory accesses. As a side | |
111 | * effect, this also makes sure that 64 bit module code cannot be used | |
112 | * as system call address. | |
8b62bc96 | 113 | */ |
1da177e4 | 114 | #ifndef __s390x__ |
5fd9c6e2 CB |
115 | #define VMALLOC_START 0x78000000UL |
116 | #define VMALLOC_END 0x7e000000UL | |
0189103c | 117 | #define VMEM_MAP_END 0x80000000UL |
1da177e4 | 118 | #else /* __s390x__ */ |
5fd9c6e2 CB |
119 | #define VMALLOC_START 0x3e000000000UL |
120 | #define VMALLOC_END 0x3e040000000UL | |
0189103c | 121 | #define VMEM_MAP_END 0x40000000000UL |
1da177e4 LT |
122 | #endif /* __s390x__ */ |
123 | ||
0189103c HC |
124 | /* |
125 | * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1 | |
126 | * mapping. This needs to be calculated at compile time since the size of the | |
127 | * VMEM_MAP is static but the size of struct page can change. | |
128 | */ | |
522d8dc0 MS |
129 | #define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page)) |
130 | #define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES) | |
131 | #define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1)) | |
5fd9c6e2 | 132 | #define VMEM_MAP ((struct page *) VMALLOC_END) |
5fd9c6e2 | 133 | |
1da177e4 LT |
134 | /* |
135 | * A 31 bit pagetable entry of S390 has following format: | |
136 | * | PFRA | | OS | | |
137 | * 0 0IP0 | |
138 | * 00000000001111111111222222222233 | |
139 | * 01234567890123456789012345678901 | |
140 | * | |
141 | * I Page-Invalid Bit: Page is not available for address-translation | |
142 | * P Page-Protection Bit: Store access not possible for page | |
143 | * | |
144 | * A 31 bit segmenttable entry of S390 has following format: | |
145 | * | P-table origin | |PTL | |
146 | * 0 IC | |
147 | * 00000000001111111111222222222233 | |
148 | * 01234567890123456789012345678901 | |
149 | * | |
150 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
151 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
152 | * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) | |
153 | * | |
154 | * The 31 bit segmenttable origin of S390 has following format: | |
155 | * | |
156 | * |S-table origin | | STL | | |
157 | * X **GPS | |
158 | * 00000000001111111111222222222233 | |
159 | * 01234567890123456789012345678901 | |
160 | * | |
161 | * X Space-Switch event: | |
162 | * G Segment-Invalid Bit: * | |
163 | * P Private-Space Bit: Segment is not private (PoP 3-30) | |
164 | * S Storage-Alteration: | |
165 | * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) | |
166 | * | |
167 | * A 64 bit pagetable entry of S390 has following format: | |
168 | * | PFRA |0IP0| OS | | |
169 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
170 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
171 | * | |
172 | * I Page-Invalid Bit: Page is not available for address-translation | |
173 | * P Page-Protection Bit: Store access not possible for page | |
174 | * | |
175 | * A 64 bit segmenttable entry of S390 has following format: | |
176 | * | P-table origin | TT | |
177 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
178 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
179 | * | |
180 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
181 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
182 | * P Page-Protection Bit: Store access not possible for page | |
183 | * TT Type 00 | |
184 | * | |
185 | * A 64 bit region table entry of S390 has following format: | |
186 | * | S-table origin | TF TTTL | |
187 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
188 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
189 | * | |
190 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
191 | * TT Type 01 | |
192 | * TF | |
190a1d72 | 193 | * TL Table length |
1da177e4 LT |
194 | * |
195 | * The 64 bit regiontable origin of S390 has following format: | |
196 | * | region table origon | DTTL | |
197 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
198 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
199 | * | |
200 | * X Space-Switch event: | |
201 | * G Segment-Invalid Bit: | |
202 | * P Private-Space Bit: | |
203 | * S Storage-Alteration: | |
204 | * R Real space | |
205 | * TL Table-Length: | |
206 | * | |
207 | * A storage key has the following format: | |
208 | * | ACC |F|R|C|0| | |
209 | * 0 3 4 5 6 7 | |
210 | * ACC: access key | |
211 | * F : fetch protection bit | |
212 | * R : referenced bit | |
213 | * C : changed bit | |
214 | */ | |
215 | ||
216 | /* Hardware bits in the page table entry */ | |
83377484 MS |
217 | #define _PAGE_RO 0x200 /* HW read-only bit */ |
218 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
3610cce8 MS |
219 | |
220 | /* Software bits in the page table entry */ | |
83377484 MS |
221 | #define _PAGE_SWT 0x001 /* SW pte type bit t */ |
222 | #define _PAGE_SWX 0x002 /* SW pte type bit x */ | |
a08cb629 NP |
223 | #define _PAGE_SPECIAL 0x004 /* SW associated with special page */ |
224 | #define __HAVE_ARCH_PTE_SPECIAL | |
1da177e4 | 225 | |
83377484 | 226 | /* Six different types of pages. */ |
9282ed92 GS |
227 | #define _PAGE_TYPE_EMPTY 0x400 |
228 | #define _PAGE_TYPE_NONE 0x401 | |
83377484 MS |
229 | #define _PAGE_TYPE_SWAP 0x403 |
230 | #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ | |
9282ed92 GS |
231 | #define _PAGE_TYPE_RO 0x200 |
232 | #define _PAGE_TYPE_RW 0x000 | |
c1821c2e GS |
233 | #define _PAGE_TYPE_EX_RO 0x202 |
234 | #define _PAGE_TYPE_EX_RW 0x002 | |
1da177e4 | 235 | |
83377484 MS |
236 | /* |
237 | * PTE type bits are rather complicated. handle_pte_fault uses pte_present, | |
238 | * pte_none and pte_file to find out the pte type WITHOUT holding the page | |
239 | * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to | |
240 | * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs | |
241 | * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. | |
242 | * This change is done while holding the lock, but the intermediate step | |
243 | * of a previously valid pte with the hw invalid bit set can be observed by | |
244 | * handle_pte_fault. That makes it necessary that all valid pte types with | |
245 | * the hw invalid bit set must be distinguishable from the four pte types | |
246 | * empty, none, swap and file. | |
247 | * | |
248 | * irxt ipte irxt | |
249 | * _PAGE_TYPE_EMPTY 1000 -> 1000 | |
250 | * _PAGE_TYPE_NONE 1001 -> 1001 | |
251 | * _PAGE_TYPE_SWAP 1011 -> 1011 | |
252 | * _PAGE_TYPE_FILE 11?1 -> 11?1 | |
253 | * _PAGE_TYPE_RO 0100 -> 1100 | |
254 | * _PAGE_TYPE_RW 0000 -> 1000 | |
c1821c2e GS |
255 | * _PAGE_TYPE_EX_RO 0110 -> 1110 |
256 | * _PAGE_TYPE_EX_RW 0010 -> 1010 | |
83377484 | 257 | * |
c1821c2e | 258 | * pte_none is true for bits combinations 1000, 1010, 1100, 1110 |
83377484 MS |
259 | * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 |
260 | * pte_file is true for bits combinations 1101, 1111 | |
c1821c2e | 261 | * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. |
83377484 MS |
262 | */ |
263 | ||
5b7baf05 CB |
264 | /* Page status table bits for virtualization */ |
265 | #define RCP_PCL_BIT 55 | |
266 | #define RCP_HR_BIT 54 | |
267 | #define RCP_HC_BIT 53 | |
268 | #define RCP_GR_BIT 50 | |
269 | #define RCP_GC_BIT 49 | |
270 | ||
1da177e4 LT |
271 | #ifndef __s390x__ |
272 | ||
3610cce8 MS |
273 | /* Bits in the segment table address-space-control-element */ |
274 | #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ | |
275 | #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ | |
276 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
277 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
278 | #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ | |
1da177e4 | 279 | |
3610cce8 MS |
280 | /* Bits in the segment table entry */ |
281 | #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ | |
282 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
283 | #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ | |
284 | #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ | |
1da177e4 | 285 | |
3610cce8 MS |
286 | #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) |
287 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
1da177e4 LT |
288 | |
289 | #else /* __s390x__ */ | |
290 | ||
3610cce8 MS |
291 | /* Bits in the segment/region table address-space-control-element */ |
292 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
293 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
294 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
295 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
296 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
297 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
298 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
299 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
300 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
301 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
302 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
303 | ||
304 | /* Bits in the region table entry */ | |
305 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
306 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ | |
307 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
308 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
309 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
310 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
311 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
312 | ||
313 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
314 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) | |
315 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) | |
316 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) | |
317 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) | |
318 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) | |
319 | ||
1da177e4 | 320 | /* Bits in the segment table entry */ |
3610cce8 MS |
321 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
322 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
323 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
1da177e4 | 324 | |
3610cce8 MS |
325 | #define _SEGMENT_ENTRY (0) |
326 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
327 | ||
328 | #endif /* __s390x__ */ | |
1da177e4 LT |
329 | |
330 | /* | |
3610cce8 MS |
331 | * A user page table pointer has the space-switch-event bit, the |
332 | * private-space-control bit and the storage-alteration-event-control | |
333 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 334 | */ |
3610cce8 MS |
335 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
336 | _ASCE_ALT_EVENT) | |
1da177e4 | 337 | |
3610cce8 | 338 | /* Bits int the storage key */ |
1da177e4 LT |
339 | #define _PAGE_CHANGED 0x02 /* HW changed bit */ |
340 | #define _PAGE_REFERENCED 0x04 /* HW referenced bit */ | |
341 | ||
1da177e4 | 342 | /* |
9282ed92 | 343 | * Page protection definitions. |
1da177e4 | 344 | */ |
9282ed92 GS |
345 | #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) |
346 | #define PAGE_RO __pgprot(_PAGE_TYPE_RO) | |
347 | #define PAGE_RW __pgprot(_PAGE_TYPE_RW) | |
c1821c2e GS |
348 | #define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO) |
349 | #define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW) | |
9282ed92 GS |
350 | |
351 | #define PAGE_KERNEL PAGE_RW | |
352 | #define PAGE_COPY PAGE_RO | |
1da177e4 LT |
353 | |
354 | /* | |
c1821c2e GS |
355 | * Dependent on the EXEC_PROTECT option s390 can do execute protection. |
356 | * Write permission always implies read permission. In theory with a | |
357 | * primary/secondary page table execute only can be implemented but | |
358 | * it would cost an additional bit in the pte to distinguish all the | |
359 | * different pte types. To avoid that execute permission currently | |
360 | * implies read permission as well. | |
1da177e4 LT |
361 | */ |
362 | /*xwr*/ | |
9282ed92 GS |
363 | #define __P000 PAGE_NONE |
364 | #define __P001 PAGE_RO | |
365 | #define __P010 PAGE_RO | |
366 | #define __P011 PAGE_RO | |
c1821c2e GS |
367 | #define __P100 PAGE_EX_RO |
368 | #define __P101 PAGE_EX_RO | |
369 | #define __P110 PAGE_EX_RO | |
370 | #define __P111 PAGE_EX_RO | |
9282ed92 GS |
371 | |
372 | #define __S000 PAGE_NONE | |
373 | #define __S001 PAGE_RO | |
374 | #define __S010 PAGE_RW | |
375 | #define __S011 PAGE_RW | |
c1821c2e GS |
376 | #define __S100 PAGE_EX_RO |
377 | #define __S101 PAGE_EX_RO | |
378 | #define __S110 PAGE_EX_RW | |
379 | #define __S111 PAGE_EX_RW | |
380 | ||
381 | #ifndef __s390x__ | |
3610cce8 | 382 | # define PxD_SHADOW_SHIFT 1 |
c1821c2e | 383 | #else /* __s390x__ */ |
3610cce8 | 384 | # define PxD_SHADOW_SHIFT 2 |
c1821c2e GS |
385 | #endif /* __s390x__ */ |
386 | ||
3610cce8 | 387 | static inline void *get_shadow_table(void *table) |
c1821c2e | 388 | { |
3610cce8 MS |
389 | unsigned long addr, offset; |
390 | struct page *page; | |
391 | ||
392 | addr = (unsigned long) table; | |
393 | offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1); | |
394 | page = virt_to_page((void *)(addr ^ offset)); | |
395 | return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL); | |
c1821c2e | 396 | } |
1da177e4 LT |
397 | |
398 | /* | |
399 | * Certain architectures need to do special things when PTEs | |
400 | * within a page table are directly modified. Thus, the following | |
401 | * hook is made available. | |
402 | */ | |
ba8a9229 | 403 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
146e4b3c | 404 | pte_t *ptep, pte_t entry) |
1da177e4 | 405 | { |
146e4b3c MS |
406 | *ptep = entry; |
407 | if (mm->context.noexec) { | |
408 | if (!(pte_val(entry) & _PAGE_INVALID) && | |
409 | (pte_val(entry) & _PAGE_SWX)) | |
410 | pte_val(entry) |= _PAGE_RO; | |
c1821c2e | 411 | else |
146e4b3c MS |
412 | pte_val(entry) = _PAGE_TYPE_EMPTY; |
413 | ptep[PTRS_PER_PTE] = entry; | |
c1821c2e | 414 | } |
1da177e4 | 415 | } |
1da177e4 LT |
416 | |
417 | /* | |
418 | * pgd/pmd/pte query functions | |
419 | */ | |
420 | #ifndef __s390x__ | |
421 | ||
4448aaf0 AB |
422 | static inline int pgd_present(pgd_t pgd) { return 1; } |
423 | static inline int pgd_none(pgd_t pgd) { return 0; } | |
424 | static inline int pgd_bad(pgd_t pgd) { return 0; } | |
1da177e4 | 425 | |
190a1d72 MS |
426 | static inline int pud_present(pud_t pud) { return 1; } |
427 | static inline int pud_none(pud_t pud) { return 0; } | |
428 | static inline int pud_bad(pud_t pud) { return 0; } | |
429 | ||
1da177e4 LT |
430 | #else /* __s390x__ */ |
431 | ||
5a216a20 MS |
432 | static inline int pgd_present(pgd_t pgd) |
433 | { | |
6252d702 MS |
434 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
435 | return 1; | |
5a216a20 MS |
436 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
437 | } | |
438 | ||
439 | static inline int pgd_none(pgd_t pgd) | |
440 | { | |
6252d702 MS |
441 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
442 | return 0; | |
5a216a20 MS |
443 | return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; |
444 | } | |
445 | ||
446 | static inline int pgd_bad(pgd_t pgd) | |
447 | { | |
6252d702 MS |
448 | /* |
449 | * With dynamic page table levels the pgd can be a region table | |
450 | * entry or a segment table entry. Check for the bit that are | |
451 | * invalid for either table entry. | |
452 | */ | |
5a216a20 | 453 | unsigned long mask = |
6252d702 | 454 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
455 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
456 | return (pgd_val(pgd) & mask) != 0; | |
457 | } | |
190a1d72 MS |
458 | |
459 | static inline int pud_present(pud_t pud) | |
1da177e4 | 460 | { |
6252d702 MS |
461 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
462 | return 1; | |
0d017923 | 463 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
464 | } |
465 | ||
190a1d72 | 466 | static inline int pud_none(pud_t pud) |
1da177e4 | 467 | { |
6252d702 MS |
468 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
469 | return 0; | |
0d017923 | 470 | return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; |
1da177e4 LT |
471 | } |
472 | ||
190a1d72 | 473 | static inline int pud_bad(pud_t pud) |
1da177e4 | 474 | { |
6252d702 MS |
475 | /* |
476 | * With dynamic page table levels the pud can be a region table | |
477 | * entry or a segment table entry. Check for the bit that are | |
478 | * invalid for either table entry. | |
479 | */ | |
5a216a20 | 480 | unsigned long mask = |
6252d702 | 481 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
482 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
483 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
484 | } |
485 | ||
3610cce8 MS |
486 | #endif /* __s390x__ */ |
487 | ||
4448aaf0 | 488 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 489 | { |
0d017923 | 490 | return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
491 | } |
492 | ||
4448aaf0 | 493 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 494 | { |
0d017923 | 495 | return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL; |
1da177e4 LT |
496 | } |
497 | ||
4448aaf0 | 498 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 499 | { |
3610cce8 MS |
500 | unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; |
501 | return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; | |
1da177e4 LT |
502 | } |
503 | ||
4448aaf0 | 504 | static inline int pte_none(pte_t pte) |
1da177e4 | 505 | { |
83377484 | 506 | return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); |
1da177e4 LT |
507 | } |
508 | ||
4448aaf0 | 509 | static inline int pte_present(pte_t pte) |
1da177e4 | 510 | { |
83377484 MS |
511 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; |
512 | return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || | |
513 | (!(pte_val(pte) & _PAGE_INVALID) && | |
514 | !(pte_val(pte) & _PAGE_SWT)); | |
1da177e4 LT |
515 | } |
516 | ||
4448aaf0 | 517 | static inline int pte_file(pte_t pte) |
1da177e4 | 518 | { |
83377484 MS |
519 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; |
520 | return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; | |
1da177e4 LT |
521 | } |
522 | ||
7e675137 NP |
523 | static inline int pte_special(pte_t pte) |
524 | { | |
a08cb629 | 525 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
526 | } |
527 | ||
ba8a9229 MS |
528 | #define __HAVE_ARCH_PTE_SAME |
529 | #define pte_same(a,b) (pte_val(a) == pte_val(b)) | |
1da177e4 | 530 | |
5b7baf05 CB |
531 | static inline void rcp_lock(pte_t *ptep) |
532 | { | |
533 | #ifdef CONFIG_PGSTE | |
534 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
535 | preempt_disable(); | |
536 | while (test_and_set_bit(RCP_PCL_BIT, pgste)) | |
537 | ; | |
538 | #endif | |
539 | } | |
540 | ||
541 | static inline void rcp_unlock(pte_t *ptep) | |
542 | { | |
543 | #ifdef CONFIG_PGSTE | |
544 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
545 | clear_bit(RCP_PCL_BIT, pgste); | |
546 | preempt_enable(); | |
547 | #endif | |
548 | } | |
549 | ||
550 | /* forward declaration for SetPageUptodate in page-flags.h*/ | |
551 | static inline void page_clear_dirty(struct page *page); | |
552 | #include <linux/page-flags.h> | |
553 | ||
554 | static inline void ptep_rcp_copy(pte_t *ptep) | |
555 | { | |
556 | #ifdef CONFIG_PGSTE | |
557 | struct page *page = virt_to_page(pte_val(*ptep)); | |
558 | unsigned int skey; | |
559 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
560 | ||
561 | skey = page_get_storage_key(page_to_phys(page)); | |
562 | if (skey & _PAGE_CHANGED) | |
c71799c1 | 563 | set_bit_simple(RCP_GC_BIT, pgste); |
5b7baf05 | 564 | if (skey & _PAGE_REFERENCED) |
c71799c1 HC |
565 | set_bit_simple(RCP_GR_BIT, pgste); |
566 | if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) | |
5b7baf05 | 567 | SetPageDirty(page); |
c71799c1 | 568 | if (test_and_clear_bit_simple(RCP_HR_BIT, pgste)) |
5b7baf05 CB |
569 | SetPageReferenced(page); |
570 | #endif | |
571 | } | |
572 | ||
1da177e4 LT |
573 | /* |
574 | * query functions pte_write/pte_dirty/pte_young only work if | |
575 | * pte_present() is true. Undefined behaviour if not.. | |
576 | */ | |
4448aaf0 | 577 | static inline int pte_write(pte_t pte) |
1da177e4 LT |
578 | { |
579 | return (pte_val(pte) & _PAGE_RO) == 0; | |
580 | } | |
581 | ||
4448aaf0 | 582 | static inline int pte_dirty(pte_t pte) |
1da177e4 LT |
583 | { |
584 | /* A pte is neither clean nor dirty on s/390. The dirty bit | |
585 | * is in the storage key. See page_test_and_clear_dirty for | |
586 | * details. | |
587 | */ | |
588 | return 0; | |
589 | } | |
590 | ||
4448aaf0 | 591 | static inline int pte_young(pte_t pte) |
1da177e4 LT |
592 | { |
593 | /* A pte is neither young nor old on s/390. The young bit | |
594 | * is in the storage key. See page_test_and_clear_young for | |
595 | * details. | |
596 | */ | |
597 | return 0; | |
598 | } | |
599 | ||
1da177e4 LT |
600 | /* |
601 | * pgd/pmd/pte modification functions | |
602 | */ | |
603 | ||
604 | #ifndef __s390x__ | |
605 | ||
190a1d72 MS |
606 | #define pgd_clear(pgd) do { } while (0) |
607 | #define pud_clear(pud) do { } while (0) | |
1da177e4 | 608 | |
1da177e4 LT |
609 | #else /* __s390x__ */ |
610 | ||
5a216a20 MS |
611 | static inline void pgd_clear_kernel(pgd_t * pgd) |
612 | { | |
6252d702 MS |
613 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
614 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
615 | } |
616 | ||
617 | static inline void pgd_clear(pgd_t * pgd) | |
618 | { | |
619 | pgd_t *shadow = get_shadow_table(pgd); | |
620 | ||
621 | pgd_clear_kernel(pgd); | |
622 | if (shadow) | |
623 | pgd_clear_kernel(shadow); | |
624 | } | |
190a1d72 MS |
625 | |
626 | static inline void pud_clear_kernel(pud_t *pud) | |
1da177e4 | 627 | { |
6252d702 MS |
628 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
629 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
630 | } |
631 | ||
6252d702 | 632 | static inline void pud_clear(pud_t *pud) |
c1821c2e | 633 | { |
190a1d72 | 634 | pud_t *shadow = get_shadow_table(pud); |
c1821c2e | 635 | |
190a1d72 MS |
636 | pud_clear_kernel(pud); |
637 | if (shadow) | |
638 | pud_clear_kernel(shadow); | |
c1821c2e GS |
639 | } |
640 | ||
146e4b3c MS |
641 | #endif /* __s390x__ */ |
642 | ||
c1821c2e | 643 | static inline void pmd_clear_kernel(pmd_t * pmdp) |
1da177e4 | 644 | { |
3610cce8 | 645 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
646 | } |
647 | ||
146e4b3c | 648 | static inline void pmd_clear(pmd_t *pmd) |
c1821c2e | 649 | { |
146e4b3c | 650 | pmd_t *shadow = get_shadow_table(pmd); |
c1821c2e | 651 | |
146e4b3c MS |
652 | pmd_clear_kernel(pmd); |
653 | if (shadow) | |
654 | pmd_clear_kernel(shadow); | |
c1821c2e GS |
655 | } |
656 | ||
4448aaf0 | 657 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 658 | { |
5b7baf05 CB |
659 | if (mm->context.pgstes) |
660 | ptep_rcp_copy(ptep); | |
9282ed92 | 661 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
146e4b3c MS |
662 | if (mm->context.noexec) |
663 | pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY; | |
1da177e4 LT |
664 | } |
665 | ||
666 | /* | |
667 | * The following pte modification functions only work if | |
668 | * pte_present() is true. Undefined behaviour if not.. | |
669 | */ | |
4448aaf0 | 670 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 LT |
671 | { |
672 | pte_val(pte) &= PAGE_MASK; | |
673 | pte_val(pte) |= pgprot_val(newprot); | |
674 | return pte; | |
675 | } | |
676 | ||
4448aaf0 | 677 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 678 | { |
9282ed92 | 679 | /* Do not clobber _PAGE_TYPE_NONE pages! */ |
1da177e4 LT |
680 | if (!(pte_val(pte) & _PAGE_INVALID)) |
681 | pte_val(pte) |= _PAGE_RO; | |
682 | return pte; | |
683 | } | |
684 | ||
4448aaf0 | 685 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 LT |
686 | { |
687 | pte_val(pte) &= ~_PAGE_RO; | |
688 | return pte; | |
689 | } | |
690 | ||
4448aaf0 | 691 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 LT |
692 | { |
693 | /* The only user of pte_mkclean is the fork() code. | |
694 | We must *not* clear the *physical* page dirty bit | |
695 | just because fork() wants to clear the dirty bit in | |
696 | *one* of the page's mappings. So we just do nothing. */ | |
697 | return pte; | |
698 | } | |
699 | ||
4448aaf0 | 700 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 LT |
701 | { |
702 | /* We do not explicitly set the dirty bit because the | |
703 | * sske instruction is slow. It is faster to let the | |
704 | * next instruction set the dirty bit. | |
705 | */ | |
706 | return pte; | |
707 | } | |
708 | ||
4448aaf0 | 709 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 LT |
710 | { |
711 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
712 | * There is no point in clearing the real referenced bit. | |
713 | */ | |
714 | return pte; | |
715 | } | |
716 | ||
4448aaf0 | 717 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 LT |
718 | { |
719 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
720 | * There is no point in setting the real referenced bit. | |
721 | */ | |
722 | return pte; | |
723 | } | |
724 | ||
7e675137 NP |
725 | static inline pte_t pte_mkspecial(pte_t pte) |
726 | { | |
a08cb629 | 727 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
728 | return pte; |
729 | } | |
730 | ||
ba8a9229 MS |
731 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
732 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
733 | unsigned long addr, pte_t *ptep) | |
1da177e4 | 734 | { |
5b7baf05 CB |
735 | #ifdef CONFIG_PGSTE |
736 | unsigned long physpage; | |
737 | int young; | |
738 | unsigned long *pgste; | |
739 | ||
740 | if (!vma->vm_mm->context.pgstes) | |
741 | return 0; | |
742 | physpage = pte_val(*ptep) & PAGE_MASK; | |
743 | pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
744 | ||
745 | young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0); | |
746 | rcp_lock(ptep); | |
747 | if (young) | |
c71799c1 HC |
748 | set_bit_simple(RCP_GR_BIT, pgste); |
749 | young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste); | |
5b7baf05 CB |
750 | rcp_unlock(ptep); |
751 | return young; | |
752 | #endif | |
1da177e4 LT |
753 | return 0; |
754 | } | |
755 | ||
ba8a9229 MS |
756 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
757 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
758 | unsigned long address, pte_t *ptep) | |
1da177e4 | 759 | { |
5b7baf05 CB |
760 | /* No need to flush TLB |
761 | * On s390 reference bits are in storage key and never in TLB | |
762 | * With virtualization we handle the reference bit, without we | |
763 | * we can simply return */ | |
764 | #ifdef CONFIG_PGSTE | |
765 | return ptep_test_and_clear_young(vma, address, ptep); | |
766 | #endif | |
ba8a9229 | 767 | return 0; |
1da177e4 LT |
768 | } |
769 | ||
9282ed92 | 770 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 771 | { |
9282ed92 | 772 | if (!(pte_val(*ptep) & _PAGE_INVALID)) { |
1da177e4 | 773 | #ifndef __s390x__ |
146e4b3c | 774 | /* pto must point to the start of the segment table */ |
1da177e4 | 775 | pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); |
9282ed92 GS |
776 | #else |
777 | /* ipte in zarch mode can do the math */ | |
778 | pte_t *pto = ptep; | |
779 | #endif | |
94c12cc7 MS |
780 | asm volatile( |
781 | " ipte %2,%3" | |
782 | : "=m" (*ptep) : "m" (*ptep), | |
783 | "a" (pto), "a" (address)); | |
1da177e4 | 784 | } |
9282ed92 GS |
785 | } |
786 | ||
146e4b3c MS |
787 | static inline void ptep_invalidate(struct mm_struct *mm, |
788 | unsigned long address, pte_t *ptep) | |
9282ed92 | 789 | { |
5b7baf05 CB |
790 | if (mm->context.pgstes) { |
791 | rcp_lock(ptep); | |
792 | __ptep_ipte(address, ptep); | |
793 | ptep_rcp_copy(ptep); | |
794 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; | |
795 | rcp_unlock(ptep); | |
796 | return; | |
797 | } | |
9282ed92 | 798 | __ptep_ipte(address, ptep); |
5b7baf05 CB |
799 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
800 | if (mm->context.noexec) { | |
146e4b3c | 801 | __ptep_ipte(address, ptep + PTRS_PER_PTE); |
5b7baf05 CB |
802 | pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY; |
803 | } | |
f0e47c22 MS |
804 | } |
805 | ||
ba8a9229 MS |
806 | /* |
807 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
808 | * both clear the TLB for the unmapped pte. The reason is that | |
809 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
810 | * to modify an active pte. The sequence is | |
811 | * 1) ptep_get_and_clear | |
812 | * 2) set_pte_at | |
813 | * 3) flush_tlb_range | |
814 | * On s390 the tlb needs to get flushed with the modification of the pte | |
815 | * if the pte is active. The only way how this can be implemented is to | |
816 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
817 | * is a nop. | |
818 | */ | |
819 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
820 | #define ptep_get_and_clear(__mm, __address, __ptep) \ | |
821 | ({ \ | |
822 | pte_t __pte = *(__ptep); \ | |
823 | if (atomic_read(&(__mm)->mm_users) > 1 || \ | |
824 | (__mm) != current->active_mm) \ | |
146e4b3c | 825 | ptep_invalidate(__mm, __address, __ptep); \ |
ba8a9229 MS |
826 | else \ |
827 | pte_clear((__mm), (__address), (__ptep)); \ | |
828 | __pte; \ | |
829 | }) | |
830 | ||
831 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
832 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
833 | unsigned long address, pte_t *ptep) | |
834 | { | |
835 | pte_t pte = *ptep; | |
146e4b3c | 836 | ptep_invalidate(vma->vm_mm, address, ptep); |
1da177e4 LT |
837 | return pte; |
838 | } | |
839 | ||
ba8a9229 MS |
840 | /* |
841 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
842 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
843 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
844 | * cannot be accessed while the batched unmap is running. In this case | |
845 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
846 | */ | |
847 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
848 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
849 | unsigned long addr, | |
850 | pte_t *ptep, int full) | |
1da177e4 | 851 | { |
ba8a9229 MS |
852 | pte_t pte = *ptep; |
853 | ||
854 | if (full) | |
855 | pte_clear(mm, addr, ptep); | |
856 | else | |
146e4b3c | 857 | ptep_invalidate(mm, addr, ptep); |
ba8a9229 | 858 | return pte; |
1da177e4 LT |
859 | } |
860 | ||
ba8a9229 MS |
861 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
862 | #define ptep_set_wrprotect(__mm, __addr, __ptep) \ | |
863 | ({ \ | |
864 | pte_t __pte = *(__ptep); \ | |
865 | if (pte_write(__pte)) { \ | |
866 | if (atomic_read(&(__mm)->mm_users) > 1 || \ | |
867 | (__mm) != current->active_mm) \ | |
146e4b3c | 868 | ptep_invalidate(__mm, __addr, __ptep); \ |
ba8a9229 MS |
869 | set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \ |
870 | } \ | |
871 | }) | |
872 | ||
873 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
f0e47c22 MS |
874 | #define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \ |
875 | ({ \ | |
876 | int __changed = !pte_same(*(__ptep), __entry); \ | |
877 | if (__changed) { \ | |
146e4b3c | 878 | ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \ |
f0e47c22 MS |
879 | set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \ |
880 | } \ | |
881 | __changed; \ | |
8dab5241 | 882 | }) |
1da177e4 LT |
883 | |
884 | /* | |
885 | * Test and clear dirty bit in storage key. | |
886 | * We can't clear the changed bit atomically. This is a potential | |
887 | * race against modification of the referenced bit. This function | |
888 | * should therefore only be called if it is not mapped in any | |
889 | * address space. | |
890 | */ | |
ba8a9229 | 891 | #define __HAVE_ARCH_PAGE_TEST_DIRTY |
6c210482 | 892 | static inline int page_test_dirty(struct page *page) |
2dcea57a | 893 | { |
6c210482 MS |
894 | return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0; |
895 | } | |
2dcea57a | 896 | |
ba8a9229 | 897 | #define __HAVE_ARCH_PAGE_CLEAR_DIRTY |
6c210482 MS |
898 | static inline void page_clear_dirty(struct page *page) |
899 | { | |
900 | page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY); | |
2dcea57a | 901 | } |
1da177e4 LT |
902 | |
903 | /* | |
904 | * Test and clear referenced bit in storage key. | |
905 | */ | |
ba8a9229 | 906 | #define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG |
2dcea57a HC |
907 | static inline int page_test_and_clear_young(struct page *page) |
908 | { | |
0b2b6e1d | 909 | unsigned long physpage = page_to_phys(page); |
2dcea57a HC |
910 | int ccode; |
911 | ||
0b2b6e1d HC |
912 | asm volatile( |
913 | " rrbe 0,%1\n" | |
914 | " ipm %0\n" | |
915 | " srl %0,28\n" | |
2dcea57a HC |
916 | : "=d" (ccode) : "a" (physpage) : "cc" ); |
917 | return ccode & 2; | |
918 | } | |
1da177e4 LT |
919 | |
920 | /* | |
921 | * Conversion functions: convert a page and protection to a page entry, | |
922 | * and a page entry and page directory to the page they refer to. | |
923 | */ | |
924 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
925 | { | |
926 | pte_t __pte; | |
927 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
928 | return __pte; | |
929 | } | |
930 | ||
2dcea57a HC |
931 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
932 | { | |
0b2b6e1d | 933 | unsigned long physpage = page_to_phys(page); |
1da177e4 | 934 | |
2dcea57a HC |
935 | return mk_pte_phys(physpage, pgprot); |
936 | } | |
937 | ||
190a1d72 MS |
938 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
939 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
940 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
941 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 942 | |
190a1d72 MS |
943 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
944 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 945 | |
190a1d72 | 946 | #ifndef __s390x__ |
1da177e4 | 947 | |
190a1d72 MS |
948 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
949 | #define pud_deref(pmd) ({ BUG(); 0UL; }) | |
950 | #define pgd_deref(pmd) ({ BUG(); 0UL; }) | |
46a82b2d | 951 | |
190a1d72 MS |
952 | #define pud_offset(pgd, address) ((pud_t *) pgd) |
953 | #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) | |
1da177e4 | 954 | |
190a1d72 | 955 | #else /* __s390x__ */ |
1da177e4 | 956 | |
190a1d72 MS |
957 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
958 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 959 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 960 | |
5a216a20 MS |
961 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
962 | { | |
6252d702 MS |
963 | pud_t *pud = (pud_t *) pgd; |
964 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
965 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
966 | return pud + pud_index(address); |
967 | } | |
1da177e4 | 968 | |
190a1d72 | 969 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 970 | { |
6252d702 MS |
971 | pmd_t *pmd = (pmd_t *) pud; |
972 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
973 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 974 | return pmd + pmd_index(address); |
1da177e4 LT |
975 | } |
976 | ||
190a1d72 | 977 | #endif /* __s390x__ */ |
1da177e4 | 978 | |
190a1d72 MS |
979 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
980 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
981 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 982 | |
190a1d72 | 983 | #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) |
1da177e4 | 984 | |
190a1d72 MS |
985 | /* Find an entry in the lowest level page table.. */ |
986 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
987 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 LT |
988 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
989 | #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address) | |
990 | #define pte_unmap(pte) do { } while (0) | |
991 | #define pte_unmap_nested(pte) do { } while (0) | |
992 | ||
993 | /* | |
994 | * 31 bit swap entry format: | |
995 | * A page-table entry has some bits we have to treat in a special way. | |
996 | * Bits 0, 20 and bit 23 have to be zero, otherwise an specification | |
997 | * exception will occur instead of a page translation exception. The | |
998 | * specifiation exception has the bad habit not to store necessary | |
999 | * information in the lowcore. | |
1000 | * Bit 21 and bit 22 are the page invalid bit and the page protection | |
1001 | * bit. We set both to indicate a swapped page. | |
1002 | * Bit 30 and 31 are used to distinguish the different page types. For | |
1003 | * a swapped page these bits need to be zero. | |
1004 | * This leaves the bits 1-19 and bits 24-29 to store type and offset. | |
1005 | * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 | |
1006 | * plus 24 for the offset. | |
1007 | * 0| offset |0110|o|type |00| | |
1008 | * 0 0000000001111111111 2222 2 22222 33 | |
1009 | * 0 1234567890123456789 0123 4 56789 01 | |
1010 | * | |
1011 | * 64 bit swap entry format: | |
1012 | * A page-table entry has some bits we have to treat in a special way. | |
1013 | * Bits 52 and bit 55 have to be zero, otherwise an specification | |
1014 | * exception will occur instead of a page translation exception. The | |
1015 | * specifiation exception has the bad habit not to store necessary | |
1016 | * information in the lowcore. | |
1017 | * Bit 53 and bit 54 are the page invalid bit and the page protection | |
1018 | * bit. We set both to indicate a swapped page. | |
1019 | * Bit 62 and 63 are used to distinguish the different page types. For | |
1020 | * a swapped page these bits need to be zero. | |
1021 | * This leaves the bits 0-51 and bits 56-61 to store type and offset. | |
1022 | * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 | |
1023 | * plus 56 for the offset. | |
1024 | * | offset |0110|o|type |00| | |
1025 | * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 | |
1026 | * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 | |
1027 | */ | |
1028 | #ifndef __s390x__ | |
1029 | #define __SWP_OFFSET_MASK (~0UL >> 12) | |
1030 | #else | |
1031 | #define __SWP_OFFSET_MASK (~0UL >> 11) | |
1032 | #endif | |
4448aaf0 | 1033 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1034 | { |
1035 | pte_t pte; | |
1036 | offset &= __SWP_OFFSET_MASK; | |
9282ed92 | 1037 | pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | |
1da177e4 LT |
1038 | ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); |
1039 | return pte; | |
1040 | } | |
1041 | ||
1042 | #define __swp_type(entry) (((entry).val >> 2) & 0x1f) | |
1043 | #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) | |
1044 | #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) | |
1045 | ||
1046 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1047 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1048 | ||
1049 | #ifndef __s390x__ | |
1050 | # define PTE_FILE_MAX_BITS 26 | |
1051 | #else /* __s390x__ */ | |
1052 | # define PTE_FILE_MAX_BITS 59 | |
1053 | #endif /* __s390x__ */ | |
1054 | ||
1055 | #define pte_to_pgoff(__pte) \ | |
1056 | ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) | |
1057 | ||
1058 | #define pgoff_to_pte(__off) \ | |
1059 | ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ | |
9282ed92 | 1060 | | _PAGE_TYPE_FILE }) |
1da177e4 LT |
1061 | |
1062 | #endif /* !__ASSEMBLY__ */ | |
1063 | ||
1064 | #define kern_addr_valid(addr) (1) | |
1065 | ||
f4eb07c1 HC |
1066 | extern int add_shared_memory(unsigned long start, unsigned long size); |
1067 | extern int remove_shared_memory(unsigned long start, unsigned long size); | |
402b0862 | 1068 | extern int s390_enable_sie(void); |
f4eb07c1 | 1069 | |
1da177e4 LT |
1070 | /* |
1071 | * No page table caches to initialise | |
1072 | */ | |
1073 | #define pgtable_cache_init() do { } while (0) | |
1074 | ||
f4eb07c1 HC |
1075 | #define __HAVE_ARCH_MEMMAP_INIT |
1076 | extern void memmap_init(unsigned long, int, unsigned long, unsigned long); | |
1077 | ||
1da177e4 LT |
1078 | #include <asm-generic/pgtable.h> |
1079 | ||
1080 | #endif /* _S390_PAGE_H */ |