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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/spinlock.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/spinlock.h" | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_SPINLOCK_H | |
12 | #define __ASM_SPINLOCK_H | |
13 | ||
94c12cc7 MS |
14 | #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2) |
15 | ||
16 | static inline int | |
17 | _raw_compare_and_swap(volatile unsigned int *lock, | |
18 | unsigned int old, unsigned int new) | |
19 | { | |
20 | asm volatile( | |
21 | " cs %0,%3,%1" | |
22 | : "=d" (old), "=Q" (*lock) | |
23 | : "0" (old), "d" (new), "Q" (*lock) | |
24 | : "cc", "memory" ); | |
25 | return old; | |
26 | } | |
27 | ||
28 | #else /* __GNUC__ */ | |
29 | ||
951f22d5 MS |
30 | static inline int |
31 | _raw_compare_and_swap(volatile unsigned int *lock, | |
32 | unsigned int old, unsigned int new) | |
33 | { | |
94c12cc7 MS |
34 | asm volatile( |
35 | " cs %0,%3,0(%4)" | |
36 | : "=d" (old), "=m" (*lock) | |
37 | : "0" (old), "d" (new), "a" (lock), "m" (*lock) | |
38 | : "cc", "memory" ); | |
951f22d5 MS |
39 | return old; |
40 | } | |
1da177e4 | 41 | |
94c12cc7 MS |
42 | #endif /* __GNUC__ */ |
43 | ||
1da177e4 LT |
44 | /* |
45 | * Simple spin lock operations. There are two variants, one clears IRQ's | |
46 | * on the local processor, one does not. | |
47 | * | |
48 | * We make no fairness assumptions. They have a cost. | |
fb1c8f93 IM |
49 | * |
50 | * (the type definitions are in asm/spinlock_types.h) | |
1da177e4 LT |
51 | */ |
52 | ||
fb1c8f93 IM |
53 | #define __raw_spin_is_locked(x) ((x)->lock != 0) |
54 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) | |
55 | #define __raw_spin_unlock_wait(lock) \ | |
56 | do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) | |
1da177e4 | 57 | |
fb1c8f93 IM |
58 | extern void _raw_spin_lock_wait(raw_spinlock_t *lp, unsigned int pc); |
59 | extern int _raw_spin_trylock_retry(raw_spinlock_t *lp, unsigned int pc); | |
951f22d5 | 60 | |
fb1c8f93 | 61 | static inline void __raw_spin_lock(raw_spinlock_t *lp) |
1da177e4 | 62 | { |
9513e5e3 | 63 | unsigned long pc = 1 | (unsigned long) __builtin_return_address(0); |
951f22d5 MS |
64 | |
65 | if (unlikely(_raw_compare_and_swap(&lp->lock, 0, pc) != 0)) | |
66 | _raw_spin_lock_wait(lp, pc); | |
1da177e4 LT |
67 | } |
68 | ||
fb1c8f93 | 69 | static inline int __raw_spin_trylock(raw_spinlock_t *lp) |
1da177e4 | 70 | { |
9513e5e3 | 71 | unsigned long pc = 1 | (unsigned long) __builtin_return_address(0); |
951f22d5 MS |
72 | |
73 | if (likely(_raw_compare_and_swap(&lp->lock, 0, pc) == 0)) | |
74 | return 1; | |
75 | return _raw_spin_trylock_retry(lp, pc); | |
1da177e4 LT |
76 | } |
77 | ||
fb1c8f93 | 78 | static inline void __raw_spin_unlock(raw_spinlock_t *lp) |
1da177e4 | 79 | { |
951f22d5 | 80 | _raw_compare_and_swap(&lp->lock, lp->lock, 0); |
1da177e4 LT |
81 | } |
82 | ||
83 | /* | |
84 | * Read-write spinlocks, allowing multiple readers | |
85 | * but only one writer. | |
86 | * | |
87 | * NOTE! it is quite common to have readers in interrupts | |
88 | * but no interrupt writers. For those circumstances we | |
89 | * can "mix" irq-safe locks - any writer needs to get a | |
90 | * irq-safe write-lock, but readers can get non-irqsafe | |
91 | * read-locks. | |
92 | */ | |
1da177e4 LT |
93 | |
94 | /** | |
95 | * read_can_lock - would read_trylock() succeed? | |
96 | * @lock: the rwlock in question. | |
97 | */ | |
fb1c8f93 | 98 | #define __raw_read_can_lock(x) ((int)(x)->lock >= 0) |
1da177e4 LT |
99 | |
100 | /** | |
101 | * write_can_lock - would write_trylock() succeed? | |
102 | * @lock: the rwlock in question. | |
103 | */ | |
fb1c8f93 | 104 | #define __raw_write_can_lock(x) ((x)->lock == 0) |
1da177e4 | 105 | |
fb1c8f93 IM |
106 | extern void _raw_read_lock_wait(raw_rwlock_t *lp); |
107 | extern int _raw_read_trylock_retry(raw_rwlock_t *lp); | |
108 | extern void _raw_write_lock_wait(raw_rwlock_t *lp); | |
109 | extern int _raw_write_trylock_retry(raw_rwlock_t *lp); | |
951f22d5 | 110 | |
fb1c8f93 | 111 | static inline void __raw_read_lock(raw_rwlock_t *rw) |
951f22d5 MS |
112 | { |
113 | unsigned int old; | |
114 | old = rw->lock & 0x7fffffffU; | |
115 | if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old) | |
116 | _raw_read_lock_wait(rw); | |
117 | } | |
118 | ||
fb1c8f93 | 119 | static inline void __raw_read_unlock(raw_rwlock_t *rw) |
951f22d5 MS |
120 | { |
121 | unsigned int old, cmp; | |
122 | ||
123 | old = rw->lock; | |
124 | do { | |
125 | cmp = old; | |
126 | old = _raw_compare_and_swap(&rw->lock, old, old - 1); | |
127 | } while (cmp != old); | |
128 | } | |
129 | ||
fb1c8f93 | 130 | static inline void __raw_write_lock(raw_rwlock_t *rw) |
951f22d5 MS |
131 | { |
132 | if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0)) | |
133 | _raw_write_lock_wait(rw); | |
134 | } | |
135 | ||
fb1c8f93 | 136 | static inline void __raw_write_unlock(raw_rwlock_t *rw) |
951f22d5 MS |
137 | { |
138 | _raw_compare_and_swap(&rw->lock, 0x80000000, 0); | |
139 | } | |
140 | ||
fb1c8f93 | 141 | static inline int __raw_read_trylock(raw_rwlock_t *rw) |
951f22d5 MS |
142 | { |
143 | unsigned int old; | |
144 | old = rw->lock & 0x7fffffffU; | |
145 | if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old)) | |
146 | return 1; | |
147 | return _raw_read_trylock_retry(rw); | |
148 | } | |
149 | ||
fb1c8f93 | 150 | static inline int __raw_write_trylock(raw_rwlock_t *rw) |
1da177e4 | 151 | { |
951f22d5 MS |
152 | if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)) |
153 | return 1; | |
154 | return _raw_write_trylock_retry(rw); | |
1da177e4 LT |
155 | } |
156 | ||
ef6edc97 MS |
157 | #define _raw_spin_relax(lock) cpu_relax() |
158 | #define _raw_read_relax(lock) cpu_relax() | |
159 | #define _raw_write_relax(lock) cpu_relax() | |
160 | ||
1da177e4 | 161 | #endif /* __ASM_SPINLOCK_H */ |